1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __RADEON_DRM_H__ 7 #define __RADEON_DRM_H__ 8 #include "drm.h" 9 #if defined(__cplusplus) 10 extern "C" { 11 #endif 12 #ifndef __RADEON_SAREA_DEFINES__ 13 #define __RADEON_SAREA_DEFINES__ 14 #define RADEON_UPLOAD_CONTEXT 0x00000001 15 #define RADEON_UPLOAD_VERTFMT 0x00000002 16 #define RADEON_UPLOAD_LINE 0x00000004 17 #define RADEON_UPLOAD_BUMPMAP 0x00000008 18 #define RADEON_UPLOAD_MASKS 0x00000010 19 #define RADEON_UPLOAD_VIEWPORT 0x00000020 20 #define RADEON_UPLOAD_SETUP 0x00000040 21 #define RADEON_UPLOAD_TCL 0x00000080 22 #define RADEON_UPLOAD_MISC 0x00000100 23 #define RADEON_UPLOAD_TEX0 0x00000200 24 #define RADEON_UPLOAD_TEX1 0x00000400 25 #define RADEON_UPLOAD_TEX2 0x00000800 26 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 27 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 28 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 29 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 30 #define RADEON_REQUIRE_QUIESCENCE 0x00010000 31 #define RADEON_UPLOAD_ZBIAS 0x00020000 32 #define RADEON_UPLOAD_ALL 0x003effff 33 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 34 #define RADEON_EMIT_PP_MISC 0 35 #define RADEON_EMIT_PP_CNTL 1 36 #define RADEON_EMIT_RB3D_COLORPITCH 2 37 #define RADEON_EMIT_RE_LINE_PATTERN 3 38 #define RADEON_EMIT_SE_LINE_WIDTH 4 39 #define RADEON_EMIT_PP_LUM_MATRIX 5 40 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 41 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 42 #define RADEON_EMIT_SE_VPORT_XSCALE 8 43 #define RADEON_EMIT_SE_CNTL 9 44 #define RADEON_EMIT_SE_CNTL_STATUS 10 45 #define RADEON_EMIT_RE_MISC 11 46 #define RADEON_EMIT_PP_TXFILTER_0 12 47 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 48 #define RADEON_EMIT_PP_TXFILTER_1 14 49 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 50 #define RADEON_EMIT_PP_TXFILTER_2 16 51 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 52 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 53 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 54 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 55 #define R200_EMIT_PP_TXCBLEND_0 21 56 #define R200_EMIT_PP_TXCBLEND_1 22 57 #define R200_EMIT_PP_TXCBLEND_2 23 58 #define R200_EMIT_PP_TXCBLEND_3 24 59 #define R200_EMIT_PP_TXCBLEND_4 25 60 #define R200_EMIT_PP_TXCBLEND_5 26 61 #define R200_EMIT_PP_TXCBLEND_6 27 62 #define R200_EMIT_PP_TXCBLEND_7 28 63 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 64 #define R200_EMIT_TFACTOR_0 30 65 #define R200_EMIT_VTX_FMT_0 31 66 #define R200_EMIT_VAP_CTL 32 67 #define R200_EMIT_MATRIX_SELECT_0 33 68 #define R200_EMIT_TEX_PROC_CTL_2 34 69 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 70 #define R200_EMIT_PP_TXFILTER_0 36 71 #define R200_EMIT_PP_TXFILTER_1 37 72 #define R200_EMIT_PP_TXFILTER_2 38 73 #define R200_EMIT_PP_TXFILTER_3 39 74 #define R200_EMIT_PP_TXFILTER_4 40 75 #define R200_EMIT_PP_TXFILTER_5 41 76 #define R200_EMIT_PP_TXOFFSET_0 42 77 #define R200_EMIT_PP_TXOFFSET_1 43 78 #define R200_EMIT_PP_TXOFFSET_2 44 79 #define R200_EMIT_PP_TXOFFSET_3 45 80 #define R200_EMIT_PP_TXOFFSET_4 46 81 #define R200_EMIT_PP_TXOFFSET_5 47 82 #define R200_EMIT_VTE_CNTL 48 83 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 84 #define R200_EMIT_PP_TAM_DEBUG3 50 85 #define R200_EMIT_PP_CNTL_X 51 86 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 87 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 88 #define R200_EMIT_RE_SCISSOR_TL_0 54 89 #define R200_EMIT_RE_SCISSOR_TL_1 55 90 #define R200_EMIT_RE_SCISSOR_TL_2 56 91 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 92 #define R200_EMIT_SE_VTX_STATE_CNTL 58 93 #define R200_EMIT_RE_POINTSIZE 59 94 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 95 #define R200_EMIT_PP_CUBIC_FACES_0 61 96 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 97 #define R200_EMIT_PP_CUBIC_FACES_1 63 98 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 99 #define R200_EMIT_PP_CUBIC_FACES_2 65 100 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 101 #define R200_EMIT_PP_CUBIC_FACES_3 67 102 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 103 #define R200_EMIT_PP_CUBIC_FACES_4 69 104 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 105 #define R200_EMIT_PP_CUBIC_FACES_5 71 106 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 107 #define RADEON_EMIT_PP_TEX_SIZE_0 73 108 #define RADEON_EMIT_PP_TEX_SIZE_1 74 109 #define RADEON_EMIT_PP_TEX_SIZE_2 75 110 #define R200_EMIT_RB3D_BLENDCOLOR 76 111 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 112 #define RADEON_EMIT_PP_CUBIC_FACES_0 78 113 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 114 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 115 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 116 #define RADEON_EMIT_PP_CUBIC_FACES_2 82 117 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 118 #define R200_EMIT_PP_TRI_PERF_CNTL 84 119 #define R200_EMIT_PP_AFS_0 85 120 #define R200_EMIT_PP_AFS_1 86 121 #define R200_EMIT_ATF_TFACTOR 87 122 #define R200_EMIT_PP_TXCTLALL_0 88 123 #define R200_EMIT_PP_TXCTLALL_1 89 124 #define R200_EMIT_PP_TXCTLALL_2 90 125 #define R200_EMIT_PP_TXCTLALL_3 91 126 #define R200_EMIT_PP_TXCTLALL_4 92 127 #define R200_EMIT_PP_TXCTLALL_5 93 128 #define R200_EMIT_VAP_PVS_CNTL 94 129 #define RADEON_MAX_STATE_PACKETS 95 130 #define RADEON_CMD_PACKET 1 131 #define RADEON_CMD_SCALARS 2 132 #define RADEON_CMD_VECTORS 3 133 #define RADEON_CMD_DMA_DISCARD 4 134 #define RADEON_CMD_PACKET3 5 135 #define RADEON_CMD_PACKET3_CLIP 6 136 #define RADEON_CMD_SCALARS2 7 137 #define RADEON_CMD_WAIT 8 138 #define RADEON_CMD_VECLINEAR 9 139 typedef union { 140 int i; 141 struct { 142 unsigned char cmd_type, pad0, pad1, pad2; 143 } header; 144 struct { 145 unsigned char cmd_type, packet_id, pad0, pad1; 146 } packet; 147 struct { 148 unsigned char cmd_type, offset, stride, count; 149 } scalars; 150 struct { 151 unsigned char cmd_type, offset, stride, count; 152 } vectors; 153 struct { 154 unsigned char cmd_type, addr_lo, addr_hi, count; 155 } veclinear; 156 struct { 157 unsigned char cmd_type, buf_idx, pad0, pad1; 158 } dma; 159 struct { 160 unsigned char cmd_type, flags, pad0, pad1; 161 } wait; 162 } drm_radeon_cmd_header_t; 163 #define RADEON_WAIT_2D 0x1 164 #define RADEON_WAIT_3D 0x2 165 #define R300_CMD_PACKET3_CLEAR 0 166 #define R300_CMD_PACKET3_RAW 1 167 #define R300_CMD_PACKET0 1 168 #define R300_CMD_VPU 2 169 #define R300_CMD_PACKET3 3 170 #define R300_CMD_END3D 4 171 #define R300_CMD_CP_DELAY 5 172 #define R300_CMD_DMA_DISCARD 6 173 #define R300_CMD_WAIT 7 174 # define R300_WAIT_2D 0x1 175 # define R300_WAIT_3D 0x2 176 # define R300_WAIT_2D_CLEAN 0x3 177 # define R300_WAIT_3D_CLEAN 0x4 178 # define R300_NEW_WAIT_2D_3D 0x3 179 # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 180 # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 181 # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 182 #define R300_CMD_SCRATCH 8 183 #define R300_CMD_R500FP 9 184 typedef union { 185 unsigned int u; 186 struct { 187 unsigned char cmd_type, pad0, pad1, pad2; 188 } header; 189 struct { 190 unsigned char cmd_type, count, reglo, reghi; 191 } packet0; 192 struct { 193 unsigned char cmd_type, count, adrlo, adrhi; 194 } vpu; 195 struct { 196 unsigned char cmd_type, packet, pad0, pad1; 197 } packet3; 198 struct { 199 unsigned char cmd_type, packet; 200 unsigned short count; 201 } delay; 202 struct { 203 unsigned char cmd_type, buf_idx, pad0, pad1; 204 } dma; 205 struct { 206 unsigned char cmd_type, flags, pad0, pad1; 207 } wait; 208 struct { 209 unsigned char cmd_type, reg, n_bufs, flags; 210 } scratch; 211 struct { 212 unsigned char cmd_type, count, adrlo, adrhi_flags; 213 } r500fp; 214 } drm_r300_cmd_header_t; 215 #define RADEON_FRONT 0x1 216 #define RADEON_BACK 0x2 217 #define RADEON_DEPTH 0x4 218 #define RADEON_STENCIL 0x8 219 #define RADEON_CLEAR_FASTZ 0x80000000 220 #define RADEON_USE_HIERZ 0x40000000 221 #define RADEON_USE_COMP_ZBUF 0x20000000 222 #define R500FP_CONSTANT_TYPE (1 << 1) 223 #define R500FP_CONSTANT_CLAMP (1 << 2) 224 #define RADEON_POINTS 0x1 225 #define RADEON_LINES 0x2 226 #define RADEON_LINE_STRIP 0x3 227 #define RADEON_TRIANGLES 0x4 228 #define RADEON_TRIANGLE_FAN 0x5 229 #define RADEON_TRIANGLE_STRIP 0x6 230 #define RADEON_BUFFER_SIZE 65536 231 #define RADEON_INDEX_PRIM_OFFSET 20 232 #define RADEON_SCRATCH_REG_OFFSET 32 233 #define R600_SCRATCH_REG_OFFSET 256 234 #define RADEON_NR_SAREA_CLIPRECTS 12 235 #define RADEON_LOCAL_TEX_HEAP 0 236 #define RADEON_GART_TEX_HEAP 1 237 #define RADEON_NR_TEX_HEAPS 2 238 #define RADEON_NR_TEX_REGIONS 64 239 #define RADEON_LOG_TEX_GRANULARITY 16 240 #define RADEON_MAX_TEXTURE_LEVELS 12 241 #define RADEON_MAX_TEXTURE_UNITS 3 242 #define RADEON_MAX_SURFACES 8 243 #define RADEON_OFFSET_SHIFT 10 244 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 245 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 246 #endif 247 typedef struct { 248 unsigned int red; 249 unsigned int green; 250 unsigned int blue; 251 unsigned int alpha; 252 } radeon_color_regs_t; 253 typedef struct { 254 255 unsigned int pp_misc; 256 unsigned int pp_fog_color; 257 unsigned int re_solid_color; 258 unsigned int rb3d_blendcntl; 259 unsigned int rb3d_depthoffset; 260 unsigned int rb3d_depthpitch; 261 unsigned int rb3d_zstencilcntl; 262 unsigned int pp_cntl; 263 unsigned int rb3d_cntl; 264 unsigned int rb3d_coloroffset; 265 unsigned int re_width_height; 266 unsigned int rb3d_colorpitch; 267 unsigned int se_cntl; 268 269 unsigned int se_coord_fmt; 270 271 unsigned int re_line_pattern; 272 unsigned int re_line_state; 273 unsigned int se_line_width; 274 275 unsigned int pp_lum_matrix; 276 unsigned int pp_rot_matrix_0; 277 unsigned int pp_rot_matrix_1; 278 279 unsigned int rb3d_stencilrefmask; 280 unsigned int rb3d_ropcntl; 281 unsigned int rb3d_planemask; 282 283 unsigned int se_vport_xscale; 284 unsigned int se_vport_xoffset; 285 unsigned int se_vport_yscale; 286 unsigned int se_vport_yoffset; 287 unsigned int se_vport_zscale; 288 unsigned int se_vport_zoffset; 289 290 unsigned int se_cntl_status; 291 292 unsigned int re_top_left; 293 unsigned int re_misc; 294 } drm_radeon_context_regs_t; 295 typedef struct { 296 297 unsigned int se_zbias_factor; 298 unsigned int se_zbias_constant; 299 } drm_radeon_context2_regs_t; 300 typedef struct { 301 unsigned int pp_txfilter; 302 unsigned int pp_txformat; 303 unsigned int pp_txoffset; 304 unsigned int pp_txcblend; 305 unsigned int pp_txablend; 306 unsigned int pp_tfactor; 307 unsigned int pp_border_color; 308 } drm_radeon_texture_regs_t; 309 typedef struct { 310 unsigned int start; 311 unsigned int finish; 312 unsigned int prim:8; 313 unsigned int stateidx:8; 314 unsigned int numverts:16; 315 unsigned int vc_format; 316 } drm_radeon_prim_t; 317 typedef struct { 318 drm_radeon_context_regs_t context; 319 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 320 drm_radeon_context2_regs_t context2; 321 unsigned int dirty; 322 } drm_radeon_state_t; 323 typedef struct { 324 325 drm_radeon_context_regs_t context_state; 326 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 327 unsigned int dirty; 328 unsigned int vertsize; 329 unsigned int vc_format; 330 331 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 332 unsigned int nbox; 333 334 unsigned int last_frame; 335 unsigned int last_dispatch; 336 unsigned int last_clear; 337 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 338 1]; 339 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 340 int ctx_owner; 341 int pfState; 342 int pfCurrentPage; 343 int crtc2_base; 344 int tiling_enabled; 345 } drm_radeon_sarea_t; 346 #define DRM_RADEON_CP_INIT 0x00 347 #define DRM_RADEON_CP_START 0x01 348 #define DRM_RADEON_CP_STOP 0x02 349 #define DRM_RADEON_CP_RESET 0x03 350 #define DRM_RADEON_CP_IDLE 0x04 351 #define DRM_RADEON_RESET 0x05 352 #define DRM_RADEON_FULLSCREEN 0x06 353 #define DRM_RADEON_SWAP 0x07 354 #define DRM_RADEON_CLEAR 0x08 355 #define DRM_RADEON_VERTEX 0x09 356 #define DRM_RADEON_INDICES 0x0A 357 #define DRM_RADEON_NOT_USED 358 #define DRM_RADEON_STIPPLE 0x0C 359 #define DRM_RADEON_INDIRECT 0x0D 360 #define DRM_RADEON_TEXTURE 0x0E 361 #define DRM_RADEON_VERTEX2 0x0F 362 #define DRM_RADEON_CMDBUF 0x10 363 #define DRM_RADEON_GETPARAM 0x11 364 #define DRM_RADEON_FLIP 0x12 365 #define DRM_RADEON_ALLOC 0x13 366 #define DRM_RADEON_FREE 0x14 367 #define DRM_RADEON_INIT_HEAP 0x15 368 #define DRM_RADEON_IRQ_EMIT 0x16 369 #define DRM_RADEON_IRQ_WAIT 0x17 370 #define DRM_RADEON_CP_RESUME 0x18 371 #define DRM_RADEON_SETPARAM 0x19 372 #define DRM_RADEON_SURF_ALLOC 0x1a 373 #define DRM_RADEON_SURF_FREE 0x1b 374 #define DRM_RADEON_GEM_INFO 0x1c 375 #define DRM_RADEON_GEM_CREATE 0x1d 376 #define DRM_RADEON_GEM_MMAP 0x1e 377 #define DRM_RADEON_GEM_PREAD 0x21 378 #define DRM_RADEON_GEM_PWRITE 0x22 379 #define DRM_RADEON_GEM_SET_DOMAIN 0x23 380 #define DRM_RADEON_GEM_WAIT_IDLE 0x24 381 #define DRM_RADEON_CS 0x26 382 #define DRM_RADEON_INFO 0x27 383 #define DRM_RADEON_GEM_SET_TILING 0x28 384 #define DRM_RADEON_GEM_GET_TILING 0x29 385 #define DRM_RADEON_GEM_BUSY 0x2a 386 #define DRM_RADEON_GEM_VA 0x2b 387 #define DRM_RADEON_GEM_OP 0x2c 388 #define DRM_RADEON_GEM_USERPTR 0x2d 389 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 390 #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 391 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 392 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 393 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 394 #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 395 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 396 #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 397 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 398 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 399 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 400 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 401 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 402 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 403 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 404 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 405 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 406 #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 407 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 408 #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 409 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 410 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 411 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 412 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 413 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 414 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 415 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 416 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 417 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 418 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 419 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 420 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 421 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 422 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 423 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 424 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 425 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 426 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 427 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 428 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 429 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 430 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) 431 typedef struct drm_radeon_init { 432 enum { 433 RADEON_INIT_CP = 0x01, 434 RADEON_CLEANUP_CP = 0x02, 435 RADEON_INIT_R200_CP = 0x03, 436 RADEON_INIT_R300_CP = 0x04, 437 RADEON_INIT_R600_CP = 0x05 438 } func; 439 unsigned long sarea_priv_offset; 440 int is_pci; 441 int cp_mode; 442 int gart_size; 443 int ring_size; 444 int usec_timeout; 445 unsigned int fb_bpp; 446 unsigned int front_offset, front_pitch; 447 unsigned int back_offset, back_pitch; 448 unsigned int depth_bpp; 449 unsigned int depth_offset, depth_pitch; 450 unsigned long fb_offset; 451 unsigned long mmio_offset; 452 unsigned long ring_offset; 453 unsigned long ring_rptr_offset; 454 unsigned long buffers_offset; 455 unsigned long gart_textures_offset; 456 } drm_radeon_init_t; 457 typedef struct drm_radeon_cp_stop { 458 int flush; 459 int idle; 460 } drm_radeon_cp_stop_t; 461 typedef struct drm_radeon_fullscreen { 462 enum { 463 RADEON_INIT_FULLSCREEN = 0x01, 464 RADEON_CLEANUP_FULLSCREEN = 0x02 465 } func; 466 } drm_radeon_fullscreen_t; 467 #define CLEAR_X1 0 468 #define CLEAR_Y1 1 469 #define CLEAR_X2 2 470 #define CLEAR_Y2 3 471 #define CLEAR_DEPTH 4 472 typedef union drm_radeon_clear_rect { 473 float f[5]; 474 unsigned int ui[5]; 475 } drm_radeon_clear_rect_t; 476 typedef struct drm_radeon_clear { 477 unsigned int flags; 478 unsigned int clear_color; 479 unsigned int clear_depth; 480 unsigned int color_mask; 481 unsigned int depth_mask; 482 drm_radeon_clear_rect_t __user *depth_boxes; 483 } drm_radeon_clear_t; 484 typedef struct drm_radeon_vertex { 485 int prim; 486 int idx; 487 int count; 488 int discard; 489 } drm_radeon_vertex_t; 490 typedef struct drm_radeon_indices { 491 int prim; 492 int idx; 493 int start; 494 int end; 495 int discard; 496 } drm_radeon_indices_t; 497 typedef struct drm_radeon_vertex2 { 498 int idx; 499 int discard; 500 int nr_states; 501 drm_radeon_state_t __user *state; 502 int nr_prims; 503 drm_radeon_prim_t __user *prim; 504 } drm_radeon_vertex2_t; 505 typedef struct drm_radeon_cmd_buffer { 506 int bufsz; 507 char __user *buf; 508 int nbox; 509 struct drm_clip_rect __user *boxes; 510 } drm_radeon_cmd_buffer_t; 511 typedef struct drm_radeon_tex_image { 512 unsigned int x, y; 513 unsigned int width, height; 514 const void __user *data; 515 } drm_radeon_tex_image_t; 516 typedef struct drm_radeon_texture { 517 unsigned int offset; 518 int pitch; 519 int format; 520 int width; 521 int height; 522 drm_radeon_tex_image_t __user *image; 523 } drm_radeon_texture_t; 524 typedef struct drm_radeon_stipple { 525 unsigned int __user *mask; 526 } drm_radeon_stipple_t; 527 typedef struct drm_radeon_indirect { 528 int idx; 529 int start; 530 int end; 531 int discard; 532 } drm_radeon_indirect_t; 533 #define RADEON_CARD_PCI 0 534 #define RADEON_CARD_AGP 1 535 #define RADEON_CARD_PCIE 2 536 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 537 #define RADEON_PARAM_LAST_FRAME 2 538 #define RADEON_PARAM_LAST_DISPATCH 3 539 #define RADEON_PARAM_LAST_CLEAR 4 540 #define RADEON_PARAM_IRQ_NR 5 541 #define RADEON_PARAM_GART_BASE 6 542 #define RADEON_PARAM_REGISTER_HANDLE 7 543 #define RADEON_PARAM_STATUS_HANDLE 8 544 #define RADEON_PARAM_SAREA_HANDLE 9 545 #define RADEON_PARAM_GART_TEX_HANDLE 10 546 #define RADEON_PARAM_SCRATCH_OFFSET 11 547 #define RADEON_PARAM_CARD_TYPE 12 548 #define RADEON_PARAM_VBLANK_CRTC 13 549 #define RADEON_PARAM_FB_LOCATION 14 550 #define RADEON_PARAM_NUM_GB_PIPES 15 551 #define RADEON_PARAM_DEVICE_ID 16 552 #define RADEON_PARAM_NUM_Z_PIPES 17 553 typedef struct drm_radeon_getparam { 554 int param; 555 void __user *value; 556 } drm_radeon_getparam_t; 557 #define RADEON_MEM_REGION_GART 1 558 #define RADEON_MEM_REGION_FB 2 559 typedef struct drm_radeon_mem_alloc { 560 int region; 561 int alignment; 562 int size; 563 int __user *region_offset; 564 } drm_radeon_mem_alloc_t; 565 typedef struct drm_radeon_mem_free { 566 int region; 567 int region_offset; 568 } drm_radeon_mem_free_t; 569 typedef struct drm_radeon_mem_init_heap { 570 int region; 571 int size; 572 int start; 573 } drm_radeon_mem_init_heap_t; 574 typedef struct drm_radeon_irq_emit { 575 int __user *irq_seq; 576 } drm_radeon_irq_emit_t; 577 typedef struct drm_radeon_irq_wait { 578 int irq_seq; 579 } drm_radeon_irq_wait_t; 580 typedef struct drm_radeon_setparam { 581 unsigned int param; 582 __s64 value; 583 } drm_radeon_setparam_t; 584 #define RADEON_SETPARAM_FB_LOCATION 1 585 #define RADEON_SETPARAM_SWITCH_TILING 2 586 #define RADEON_SETPARAM_PCIGART_LOCATION 3 587 #define RADEON_SETPARAM_NEW_MEMMAP 4 588 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 589 #define RADEON_SETPARAM_VBLANK_CRTC 6 590 typedef struct drm_radeon_surface_alloc { 591 unsigned int address; 592 unsigned int size; 593 unsigned int flags; 594 } drm_radeon_surface_alloc_t; 595 typedef struct drm_radeon_surface_free { 596 unsigned int address; 597 } drm_radeon_surface_free_t; 598 #define DRM_RADEON_VBLANK_CRTC1 1 599 #define DRM_RADEON_VBLANK_CRTC2 2 600 #define RADEON_GEM_DOMAIN_CPU 0x1 601 #define RADEON_GEM_DOMAIN_GTT 0x2 602 #define RADEON_GEM_DOMAIN_VRAM 0x4 603 struct drm_radeon_gem_info { 604 __u64 gart_size; 605 __u64 vram_size; 606 __u64 vram_visible; 607 }; 608 #define RADEON_GEM_NO_BACKING_STORE (1 << 0) 609 #define RADEON_GEM_GTT_UC (1 << 1) 610 #define RADEON_GEM_GTT_WC (1 << 2) 611 #define RADEON_GEM_CPU_ACCESS (1 << 3) 612 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 613 struct drm_radeon_gem_create { 614 __u64 size; 615 __u64 alignment; 616 __u32 handle; 617 __u32 initial_domain; 618 __u32 flags; 619 }; 620 #define RADEON_GEM_USERPTR_READONLY (1 << 0) 621 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1) 622 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2) 623 #define RADEON_GEM_USERPTR_REGISTER (1 << 3) 624 struct drm_radeon_gem_userptr { 625 __u64 addr; 626 __u64 size; 627 __u32 flags; 628 __u32 handle; 629 }; 630 #define RADEON_TILING_MACRO 0x1 631 #define RADEON_TILING_MICRO 0x2 632 #define RADEON_TILING_SWAP_16BIT 0x4 633 #define RADEON_TILING_SWAP_32BIT 0x8 634 #define RADEON_TILING_SURFACE 0x10 635 #define RADEON_TILING_MICRO_SQUARE 0x20 636 #define RADEON_TILING_EG_BANKW_SHIFT 8 637 #define RADEON_TILING_EG_BANKW_MASK 0xf 638 #define RADEON_TILING_EG_BANKH_SHIFT 12 639 #define RADEON_TILING_EG_BANKH_MASK 0xf 640 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 641 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 642 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 643 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 644 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 645 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 646 struct drm_radeon_gem_set_tiling { 647 __u32 handle; 648 __u32 tiling_flags; 649 __u32 pitch; 650 }; 651 struct drm_radeon_gem_get_tiling { 652 __u32 handle; 653 __u32 tiling_flags; 654 __u32 pitch; 655 }; 656 struct drm_radeon_gem_mmap { 657 __u32 handle; 658 __u32 pad; 659 __u64 offset; 660 __u64 size; 661 __u64 addr_ptr; 662 }; 663 struct drm_radeon_gem_set_domain { 664 __u32 handle; 665 __u32 read_domains; 666 __u32 write_domain; 667 }; 668 struct drm_radeon_gem_wait_idle { 669 __u32 handle; 670 __u32 pad; 671 }; 672 struct drm_radeon_gem_busy { 673 __u32 handle; 674 __u32 domain; 675 }; 676 struct drm_radeon_gem_pread { 677 678 __u32 handle; 679 __u32 pad; 680 681 __u64 offset; 682 683 __u64 size; 684 685 686 __u64 data_ptr; 687 }; 688 struct drm_radeon_gem_pwrite { 689 690 __u32 handle; 691 __u32 pad; 692 693 __u64 offset; 694 695 __u64 size; 696 697 698 __u64 data_ptr; 699 }; 700 struct drm_radeon_gem_op { 701 __u32 handle; 702 __u32 op; 703 __u64 value; 704 }; 705 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 706 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 707 #define RADEON_VA_MAP 1 708 #define RADEON_VA_UNMAP 2 709 #define RADEON_VA_RESULT_OK 0 710 #define RADEON_VA_RESULT_ERROR 1 711 #define RADEON_VA_RESULT_VA_EXIST 2 712 #define RADEON_VM_PAGE_VALID (1 << 0) 713 #define RADEON_VM_PAGE_READABLE (1 << 1) 714 #define RADEON_VM_PAGE_WRITEABLE (1 << 2) 715 #define RADEON_VM_PAGE_SYSTEM (1 << 3) 716 #define RADEON_VM_PAGE_SNOOPED (1 << 4) 717 struct drm_radeon_gem_va { 718 __u32 handle; 719 __u32 operation; 720 __u32 vm_id; 721 __u32 flags; 722 __u64 offset; 723 }; 724 #define RADEON_CHUNK_ID_RELOCS 0x01 725 #define RADEON_CHUNK_ID_IB 0x02 726 #define RADEON_CHUNK_ID_FLAGS 0x03 727 #define RADEON_CHUNK_ID_CONST_IB 0x04 728 #define RADEON_CS_KEEP_TILING_FLAGS 0x01 729 #define RADEON_CS_USE_VM 0x02 730 #define RADEON_CS_END_OF_FRAME 0x04 731 #define RADEON_CS_RING_GFX 0 732 #define RADEON_CS_RING_COMPUTE 1 733 #define RADEON_CS_RING_DMA 2 734 #define RADEON_CS_RING_UVD 3 735 #define RADEON_CS_RING_VCE 4 736 struct drm_radeon_cs_chunk { 737 __u32 chunk_id; 738 __u32 length_dw; 739 __u64 chunk_data; 740 }; 741 #define RADEON_RELOC_PRIO_MASK (0xf << 0) 742 struct drm_radeon_cs_reloc { 743 __u32 handle; 744 __u32 read_domains; 745 __u32 write_domain; 746 __u32 flags; 747 }; 748 struct drm_radeon_cs { 749 __u32 num_chunks; 750 __u32 cs_id; 751 752 __u64 chunks; 753 754 __u64 gart_limit; 755 __u64 vram_limit; 756 }; 757 #define RADEON_INFO_DEVICE_ID 0x00 758 #define RADEON_INFO_NUM_GB_PIPES 0x01 759 #define RADEON_INFO_NUM_Z_PIPES 0x02 760 #define RADEON_INFO_ACCEL_WORKING 0x03 761 #define RADEON_INFO_CRTC_FROM_ID 0x04 762 #define RADEON_INFO_ACCEL_WORKING2 0x05 763 #define RADEON_INFO_TILING_CONFIG 0x06 764 #define RADEON_INFO_WANT_HYPERZ 0x07 765 #define RADEON_INFO_WANT_CMASK 0x08 766 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 767 #define RADEON_INFO_NUM_BACKENDS 0x0a 768 #define RADEON_INFO_NUM_TILE_PIPES 0x0b 769 #define RADEON_INFO_FUSION_GART_WORKING 0x0c 770 #define RADEON_INFO_BACKEND_MAP 0x0d 771 #define RADEON_INFO_VA_START 0x0e 772 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 773 #define RADEON_INFO_MAX_PIPES 0x10 774 #define RADEON_INFO_TIMESTAMP 0x11 775 #define RADEON_INFO_MAX_SE 0x12 776 #define RADEON_INFO_MAX_SH_PER_SE 0x13 777 #define RADEON_INFO_FASTFB_WORKING 0x14 778 #define RADEON_INFO_RING_WORKING 0x15 779 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 780 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 781 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 782 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 783 #define RADEON_INFO_MAX_SCLK 0x1a 784 #define RADEON_INFO_VCE_FW_VERSION 0x1b 785 #define RADEON_INFO_VCE_FB_VERSION 0x1c 786 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d 787 #define RADEON_INFO_VRAM_USAGE 0x1e 788 #define RADEON_INFO_GTT_USAGE 0x1f 789 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20 790 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21 791 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22 792 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23 793 #define RADEON_INFO_READ_REG 0x24 794 #define RADEON_INFO_VA_UNMAP_WORKING 0x25 795 #define RADEON_INFO_GPU_RESET_COUNTER 0x26 796 struct drm_radeon_info { 797 __u32 request; 798 __u32 pad; 799 __u64 value; 800 }; 801 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 802 #define SI_TILE_MODE_COLOR_1D 13 803 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9 804 #define SI_TILE_MODE_COLOR_2D_8BPP 14 805 #define SI_TILE_MODE_COLOR_2D_16BPP 15 806 #define SI_TILE_MODE_COLOR_2D_32BPP 16 807 #define SI_TILE_MODE_COLOR_2D_64BPP 17 808 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 809 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 810 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4 811 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0 812 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 813 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 814 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 815 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 816 #if defined(__cplusplus) 817 } 818 #endif 819 #endif 820