1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _GIC_V3_H_
33 #define _GIC_V3_H_
34
35 #include "stdint.h"
36 #include "target_config.h"
37 #include "los_hw_cpu.h"
38
39 #define BIT_32(bit) (1u << bit)
40 #define BIT_64(bit) (1ul << bit)
41
42 #define ICC_CTLR_EL1 "S3_0_C12_C12_4"
43 #define ICC_PMR_EL1 "S3_0_C4_C6_0"
44 #define ICC_IAR1_EL1 "S3_0_C12_C12_0"
45 #define ICC_SRE_EL1 "S3_0_C12_C12_5"
46 #define ICC_BPR0_EL1 "S3_0_C12_C8_3"
47 #define ICC_BPR1_EL1 "S3_0_C12_C12_3"
48 #define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6"
49 #define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
50 #define ICC_EOIR1_EL1 "S3_0_C12_C12_1"
51 #define ICC_SGI1R_EL1 "S3_0_C12_C11_5"
52 #define ICC_EOIR0_EL1 "S3_0_c12_c8_1"
53 #define ICC_IAR0_EL1 "S3_0_C12_C8_0"
54
55 #define ICC_CTLR_EL3 "S3_6_C12_C12_4"
56 #define ICC_SRE_EL3 "S3_6_C12_C12_5"
57 #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7"
58
59 /* GICD_CTLR bit definitions */
60 #define CTLR_ENALBE_G0 BIT_32(0)
61 #define CTLR_ENABLE_G1NS BIT_32(1)
62 #define CTLR_ENABLE_G1S BIT_32(2)
63 #define CTLR_RES0 BIT_32(3)
64 #define CTLR_ARE_S BIT_32(4)
65 #define CTLR_ARE_NS BIT_32(5)
66 #define CTLR_DS BIT_32(6)
67 #define CTLR_E1NWF BIT_32(7)
68 #define GICD_CTLR_RWP BIT_32(31)
69
70 /* peripheral identification registers */
71 #define GICD_CIDR0 (GICD_OFFSET + 0xfff0)
72 #define GICD_CIDR1 (GICD_OFFSET + 0xfff4)
73 #define GICD_CIDR2 (GICD_OFFSET + 0xfff8)
74 #define GICD_CIDR3 (GICD_OFFSET + 0xfffc)
75 #define GICD_PIDR0 (GICD_OFFSET + 0xffe0)
76 #define GICD_PIDR1 (GICD_OFFSET + 0xffe4)
77 #define GICD_PIDR2 (GICD_OFFSET + 0xffe8)
78 #define GICD_PIDR3 (GICD_OFFSET + 0xffec)
79
80 /* GICD_PIDR bit definitions and masks */
81 #define GICD_PIDR2_ARCHREV_SHIFT 4
82 #define GICD_PIDR2_ARCHREV_MASK 0xf
83
84 /* redistributor registers */
85 #define GICR_SGI_OFFSET (GICR_OFFSET + 0x10000)
86
87 #define GICR_CTLR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0000)
88 #define GICR_IIDR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0004)
89 #define GICR_TYPER(i, n) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0008 + (n)*4)
90 #define GICR_STATUSR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0010)
91 #define GICR_WAKER(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0014)
92 #define GICR_IGROUPR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0080)
93 #define GICR_IGRPMOD0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0d00)
94 #define GICR_ISENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0100)
95 #define GICR_ICENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0180)
96 #define GICR_ISPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0200)
97 #define GICR_ICPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0280)
98 #define GICR_ISACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0300)
99 #define GICR_ICACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0380)
100 #define GICR_IPRIORITYR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0400)
101 #define GICR_ICFGR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c00)
102 #define GICR_ICFGR1(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c04)
103 #define GICR_NSACR(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0e00)
104
105 #define GICR_WAKER_PROCESSORSLEEP_LEN 1U
106 #define GICR_WAKER_PROCESSORSLEEP_OFFSET 1
107 #define GICR_WAKER_CHILDRENASLEEP_LEN 1U
108 #define GICR_WAKER_CHILDRENASLEEP_OFFSET 2
109 #define GICR_WAKER_PROCESSORSLEEP (GICR_WAKER_PROCESSORSLEEP_LEN << GICR_WAKER_PROCESSORSLEEP_OFFSET)
110 #define GICR_WAKER_CHILDRENASLEEP (GICR_WAKER_CHILDRENASLEEP_LEN << GICR_WAKER_CHILDRENASLEEP_OFFSET)
111
GiccSetCtlr(UINT32 val)112 STATIC INLINE VOID GiccSetCtlr(UINT32 val)
113 {
114 #ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
115 __asm__ volatile("msr " ICC_CTLR_EL3 ", %0" ::"r"(val));
116 #else
117 __asm__ volatile("msr " ICC_CTLR_EL1 ", %0" ::"r"(val));
118 #endif
119 ISB;
120 }
121
GiccSetPmr(UINT32 val)122 STATIC INLINE VOID GiccSetPmr(UINT32 val)
123 {
124 __asm__ volatile("msr " ICC_PMR_EL1 ", %0" ::"r"(val));
125 ISB;
126 DSB;
127 }
128
GiccSetIgrpen0(UINT32 val)129 STATIC INLINE VOID GiccSetIgrpen0(UINT32 val)
130 {
131 __asm__ volatile("msr " ICC_IGRPEN0_EL1 ", %0" ::"r"(val));
132 ISB;
133 }
134
GiccSetIgrpen1(UINT32 val)135 STATIC INLINE VOID GiccSetIgrpen1(UINT32 val)
136 {
137 #ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
138 __asm__ volatile("msr " ICC_IGRPEN1_EL3 ", %0" ::"r"(val));
139 #else
140 __asm__ volatile("msr " ICC_IGRPEN1_EL1 ", %0" ::"r"(val));
141 #endif
142 ISB;
143 }
144
GiccGetSre(VOID)145 STATIC INLINE UINT32 GiccGetSre(VOID)
146 {
147 UINT32 temp;
148 #ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
149 __asm__ volatile("mrs %0, " ICC_SRE_EL3 : "=r"(temp));
150 #else
151 __asm__ volatile("mrs %0, " ICC_SRE_EL1 : "=r"(temp));
152 #endif
153 return temp;
154 }
155
GiccSetSre(UINT32 val)156 STATIC INLINE VOID GiccSetSre(UINT32 val)
157 {
158 #ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
159 __asm__ volatile("msr " ICC_SRE_EL3 ", %0" ::"r"(val));
160 #else
161 __asm__ volatile("msr " ICC_SRE_EL1 ", %0" ::"r"(val));
162 #endif
163 ISB;
164 }
165
GiccSetEoir(UINT32 val)166 STATIC INLINE VOID GiccSetEoir(UINT32 val)
167 {
168 #ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
169 __asm__ volatile("msr " ICC_EOIR0_EL1 ", %0" ::"r"(val));
170 #else
171 __asm__ volatile("msr " ICC_EOIR1_EL1 ", %0" ::"r"(val));
172 #endif
173 ISB;
174 }
175
GiccGetIar(VOID)176 STATIC INLINE UINT32 GiccGetIar(VOID)
177 {
178 UINT32 temp;
179
180 #ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
181 __asm__ volatile("mrs %0, " ICC_IAR0_EL1 : "=r"(temp));
182 #else
183 __asm__ volatile("mrs %0, " ICC_IAR1_EL1 : "=r"(temp));
184 #endif
185 DSB;
186
187 return temp;
188 }
189
GiccSetSgi1r(UINT64 val)190 STATIC INLINE VOID GiccSetSgi1r(UINT64 val)
191 {
192 __asm__ volatile("msr " ICC_SGI1R_EL1 ", %0" ::"r"(val));
193 ISB;
194 DSB;
195 }
196
GiccSetBpr0(UINT32 val)197 STATIC INLINE VOID GiccSetBpr0(UINT32 val)
198 {
199 __asm__ volatile("msr " ICC_BPR0_EL1 ", %0" ::"r"(val));
200 ISB;
201 DSB;
202 }
203 #endif
204