1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "los_timer.h"
33 #include "los_config.h"
34 #include "los_tick.h"
35 #include "los_arch_interrupt.h"
36 #include "los_debug.h"
37
38 typedef struct {
39 UINT32 CTRL;
40 UINT32 LOAD;
41 UINT32 VAL;
42 UINT32 CALIB;
43 } CORE_TIM_TYPE;
44
45 #define CORE_TIM_BASE (0xE000E010UL)
46 #define SysTick ((CORE_TIM_TYPE *)CORE_TIM_BASE)
47
48 #define CORETIM_ENABLE (1UL << 0)
49 #define CORETIM_INTMASK (1UL << 1)
50 #define CORETIM_SOURCE (1UL << 2)
51 #define CORETIM_MODE (1UL << 16)
52
53 #ifdef CPU_CK804
54 #define TIM_INT_NUM 25
55 #else
56 #define TIM_INT_NUM 1
57 #endif
58
59 STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
60 STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
61 STATIC UINT64 SysTickCycleGet(UINT32 *period);
62 STATIC VOID SysTickLock(VOID);
63 STATIC VOID SysTickUnlock(VOID);
64
65 STATIC ArchTickTimer g_archTickTimer = {
66 .freq = 0,
67 .irqNum = TIM_INT_NUM,
68 .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
69 .init = SysTickStart,
70 .getCycle = SysTickCycleGet,
71 .reload = SysTickReload,
72 .lock = SysTickLock,
73 .unlock = SysTickUnlock,
74 .tickHandler = NULL,
75 };
76
77 /* ****************************************************************************
78 Function : HalTickStart
79 Description : Configure Tick Interrupt Start
80 Input : none
81 output : none
82 return : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
83 **************************************************************************** */
SysTickStart(HWI_PROC_FUNC handler)84 STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
85 {
86 ArchTickTimer *tick = &g_archTickTimer;
87
88 tick->freq = OS_SYS_CLOCK;
89
90 SysTick->LOAD = (OS_CYCLE_PER_TICK - 1);
91 SysTick->VAL = 0;
92 SysTick->CTRL |= (CORETIM_SOURCE | CORETIM_ENABLE | CORETIM_INTMASK);
93
94 VIC_REG->IWER[0] = 0x1 << TIM_INT_NUM;
95
96 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
97 #if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
98 OsSetVector(tick->irqNum, handler, NULL);
99 #else
100 OsSetVector(tick->irqNum, handler);
101 #endif
102 #endif
103 return LOS_OK;
104 }
105
SysTickReload(UINT64 nextResponseTime)106 STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
107 {
108 if (nextResponseTime > g_archTickTimer.periodMax) {
109 nextResponseTime = g_archTickTimer.periodMax;
110 }
111 SysTick->CTRL &= ~CORETIM_ENABLE;
112 SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
113 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
114 SysTick->CTRL |= CORETIM_ENABLE;
115 return nextResponseTime;
116 }
117
SysTickCycleGet(UINT32 * period)118 STATIC UINT64 SysTickCycleGet(UINT32 *period)
119 {
120 UINT32 hwCycle;
121 UINT32 intSave = LOS_IntLock();
122 *period = SysTick->LOAD;
123 hwCycle = *period - SysTick->VAL;
124 LOS_IntRestore(intSave);
125 return (UINT64)hwCycle;
126 }
127
SysTickLock(VOID)128 STATIC VOID SysTickLock(VOID)
129 {
130 SysTick->CTRL &= ~CORETIM_ENABLE;
131 }
132
SysTickUnlock(VOID)133 STATIC VOID SysTickUnlock(VOID)
134 {
135 SysTick->CTRL |= CORETIM_ENABLE;
136 }
137
ArchSysTickTimerGet(VOID)138 ArchTickTimer *ArchSysTickTimerGet(VOID)
139 {
140 return &g_archTickTimer;
141 }
142
Wfi(VOID)143 VOID Wfi(VOID)
144 {
145 __asm__ volatile("wait");
146 }
147
Dsb(VOID)148 VOID Dsb(VOID)
149 {
150 __asm__ volatile("sync" : : : "memory");
151 }
152
ArchEnterSleep(VOID)153 UINT32 ArchEnterSleep(VOID)
154 {
155 Dsb();
156 Wfi();
157 return LOS_OK;
158 }
159