1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 }; 168 169 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 170 /* 171 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 172 * 173 * If the user does not pass priv level information via branch_sample_type, 174 * the kernel uses the event's priv level. Branch and event priv levels do 175 * not have to match. Branch priv level is checked for permissions. 176 * 177 * The branch types can be combined, however BRANCH_ANY covers all types 178 * of branches and therefore it supersedes all the other types. 179 */ 180 enum perf_branch_sample_type_shift { 181 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 182 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 183 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 184 185 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 186 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 187 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 188 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 189 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 190 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 191 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 192 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 193 194 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 195 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 196 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 197 198 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 199 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 200 201 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 202 203 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 204 205 PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ 206 207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 208 }; 209 210 enum perf_branch_sample_type { 211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 214 215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 223 224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 227 228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 230 231 PERF_SAMPLE_BRANCH_TYPE_SAVE = 232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 233 234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 235 236 PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, 237 238 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 239 }; 240 241 /* 242 * Common flow change classification 243 */ 244 enum { 245 PERF_BR_UNKNOWN = 0, /* unknown */ 246 PERF_BR_COND = 1, /* conditional */ 247 PERF_BR_UNCOND = 2, /* unconditional */ 248 PERF_BR_IND = 3, /* indirect */ 249 PERF_BR_CALL = 4, /* function call */ 250 PERF_BR_IND_CALL = 5, /* indirect function call */ 251 PERF_BR_RET = 6, /* function return */ 252 PERF_BR_SYSCALL = 7, /* syscall */ 253 PERF_BR_SYSRET = 8, /* syscall return */ 254 PERF_BR_COND_CALL = 9, /* conditional function call */ 255 PERF_BR_COND_RET = 10, /* conditional function return */ 256 PERF_BR_ERET = 11, /* exception return */ 257 PERF_BR_IRQ = 12, /* irq */ 258 PERF_BR_SERROR = 13, /* system error */ 259 PERF_BR_NO_TX = 14, /* not in transaction */ 260 PERF_BR_EXTEND_ABI = 15, /* extend ABI */ 261 PERF_BR_MAX, 262 }; 263 264 /* 265 * Common branch speculation outcome classification 266 */ 267 enum { 268 PERF_BR_SPEC_NA = 0, /* Not available */ 269 PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */ 270 PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */ 271 PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */ 272 PERF_BR_SPEC_MAX, 273 }; 274 275 enum { 276 PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 277 PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 278 PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 279 PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 280 PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 281 PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 282 PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 283 PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 284 PERF_BR_NEW_MAX, 285 }; 286 287 enum { 288 PERF_BR_PRIV_UNKNOWN = 0, 289 PERF_BR_PRIV_USER = 1, 290 PERF_BR_PRIV_KERNEL = 2, 291 PERF_BR_PRIV_HV = 3, 292 }; 293 294 #define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1 295 #define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2 296 #define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3 297 #define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4 298 #define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5 299 300 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 301 (PERF_SAMPLE_BRANCH_USER|\ 302 PERF_SAMPLE_BRANCH_KERNEL|\ 303 PERF_SAMPLE_BRANCH_HV) 304 305 /* 306 * Values to determine ABI of the registers dump. 307 */ 308 enum perf_sample_regs_abi { 309 PERF_SAMPLE_REGS_ABI_NONE = 0, 310 PERF_SAMPLE_REGS_ABI_32 = 1, 311 PERF_SAMPLE_REGS_ABI_64 = 2, 312 }; 313 314 /* 315 * Values for the memory transaction event qualifier, mostly for 316 * abort events. Multiple bits can be set. 317 */ 318 enum { 319 PERF_TXN_ELISION = (1 << 0), /* From elision */ 320 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 321 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 322 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 323 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 324 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 325 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 326 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 327 328 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 329 330 /* bits 32..63 are reserved for the abort code */ 331 332 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 333 PERF_TXN_ABORT_SHIFT = 32, 334 }; 335 336 /* 337 * The format of the data returned by read() on a perf event fd, 338 * as specified by attr.read_format: 339 * 340 * struct read_format { 341 * { u64 value; 342 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 343 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 344 * { u64 id; } && PERF_FORMAT_ID 345 * { u64 lost; } && PERF_FORMAT_LOST 346 * } && !PERF_FORMAT_GROUP 347 * 348 * { u64 nr; 349 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 350 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 351 * { u64 value; 352 * { u64 id; } && PERF_FORMAT_ID 353 * { u64 lost; } && PERF_FORMAT_LOST 354 * } cntr[nr]; 355 * } && PERF_FORMAT_GROUP 356 * }; 357 */ 358 enum perf_event_read_format { 359 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 360 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 361 PERF_FORMAT_ID = 1U << 2, 362 PERF_FORMAT_GROUP = 1U << 3, 363 PERF_FORMAT_LOST = 1U << 4, 364 365 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 366 }; 367 368 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 369 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 370 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 371 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 372 /* add: sample_stack_user */ 373 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 374 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 375 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 376 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 377 378 /* 379 * Hardware event_id to monitor via a performance monitoring event: 380 * 381 * @sample_max_stack: Max number of frame pointers in a callchain, 382 * should be < /proc/sys/kernel/perf_event_max_stack 383 */ 384 struct perf_event_attr { 385 386 /* 387 * Major type: hardware/software/tracepoint/etc. 388 */ 389 __u32 type; 390 391 /* 392 * Size of the attr structure, for fwd/bwd compat. 393 */ 394 __u32 size; 395 396 /* 397 * Type specific configuration information. 398 */ 399 __u64 config; 400 401 union { 402 __u64 sample_period; 403 __u64 sample_freq; 404 }; 405 406 __u64 sample_type; 407 __u64 read_format; 408 409 __u64 disabled : 1, /* off by default */ 410 inherit : 1, /* children inherit it */ 411 pinned : 1, /* must always be on PMU */ 412 exclusive : 1, /* only group on PMU */ 413 exclude_user : 1, /* don't count user */ 414 exclude_kernel : 1, /* ditto kernel */ 415 exclude_hv : 1, /* ditto hypervisor */ 416 exclude_idle : 1, /* don't count when idle */ 417 mmap : 1, /* include mmap data */ 418 comm : 1, /* include comm data */ 419 freq : 1, /* use freq, not period */ 420 inherit_stat : 1, /* per task counts */ 421 enable_on_exec : 1, /* next exec enables */ 422 task : 1, /* trace fork/exit */ 423 watermark : 1, /* wakeup_watermark */ 424 /* 425 * precise_ip: 426 * 427 * 0 - SAMPLE_IP can have arbitrary skid 428 * 1 - SAMPLE_IP must have constant skid 429 * 2 - SAMPLE_IP requested to have 0 skid 430 * 3 - SAMPLE_IP must have 0 skid 431 * 432 * See also PERF_RECORD_MISC_EXACT_IP 433 */ 434 precise_ip : 2, /* skid constraint */ 435 mmap_data : 1, /* non-exec mmap data */ 436 sample_id_all : 1, /* sample_type all events */ 437 438 exclude_host : 1, /* don't count in host */ 439 exclude_guest : 1, /* don't count in guest */ 440 441 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 442 exclude_callchain_user : 1, /* exclude user callchains */ 443 mmap2 : 1, /* include mmap with inode data */ 444 comm_exec : 1, /* flag comm events that are due to an exec */ 445 use_clockid : 1, /* use @clockid for time fields */ 446 context_switch : 1, /* context switch data */ 447 write_backward : 1, /* Write ring buffer from end to beginning */ 448 namespaces : 1, /* include namespaces data */ 449 ksymbol : 1, /* include ksymbol events */ 450 bpf_event : 1, /* include bpf events */ 451 aux_output : 1, /* generate AUX records instead of events */ 452 cgroup : 1, /* include cgroup events */ 453 text_poke : 1, /* include text poke events */ 454 build_id : 1, /* use build id in mmap2 events */ 455 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 456 remove_on_exec : 1, /* event is removed from task on exec */ 457 sigtrap : 1, /* send synchronous SIGTRAP on event */ 458 __reserved_1 : 26; 459 460 union { 461 __u32 wakeup_events; /* wakeup every n events */ 462 __u32 wakeup_watermark; /* bytes before wakeup */ 463 }; 464 465 __u32 bp_type; 466 union { 467 __u64 bp_addr; 468 __u64 kprobe_func; /* for perf_kprobe */ 469 __u64 uprobe_path; /* for perf_uprobe */ 470 __u64 config1; /* extension of config */ 471 }; 472 union { 473 __u64 bp_len; 474 __u64 kprobe_addr; /* when kprobe_func == NULL */ 475 __u64 probe_offset; /* for perf_[k,u]probe */ 476 __u64 config2; /* extension of config1 */ 477 }; 478 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 479 480 /* 481 * Defines set of user regs to dump on samples. 482 * See asm/perf_regs.h for details. 483 */ 484 __u64 sample_regs_user; 485 486 /* 487 * Defines size of the user stack to dump on samples. 488 */ 489 __u32 sample_stack_user; 490 491 __s32 clockid; 492 /* 493 * Defines set of regs to dump for each sample 494 * state captured on: 495 * - precise = 0: PMU interrupt 496 * - precise > 0: sampled instruction 497 * 498 * See asm/perf_regs.h for details. 499 */ 500 __u64 sample_regs_intr; 501 502 /* 503 * Wakeup watermark for AUX area 504 */ 505 __u32 aux_watermark; 506 __u16 sample_max_stack; 507 __u16 __reserved_2; 508 __u32 aux_sample_size; 509 __u32 __reserved_3; 510 511 /* 512 * User provided data if sigtrap=1, passed back to user via 513 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 514 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 515 * truncated accordingly on 32 bit architectures. 516 */ 517 __u64 sig_data; 518 }; 519 520 /* 521 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 522 * to query bpf programs attached to the same perf tracepoint 523 * as the given perf event. 524 */ 525 struct perf_event_query_bpf { 526 /* 527 * The below ids array length 528 */ 529 __u32 ids_len; 530 /* 531 * Set by the kernel to indicate the number of 532 * available programs 533 */ 534 __u32 prog_cnt; 535 /* 536 * User provided buffer to store program ids 537 */ 538 __u32 ids[]; 539 }; 540 541 /* 542 * Ioctls that can be done on a perf event fd: 543 */ 544 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 545 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 546 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 547 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 548 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 549 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 550 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 551 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 552 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 553 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 554 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 555 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 556 557 enum perf_event_ioc_flags { 558 PERF_IOC_FLAG_GROUP = 1U << 0, 559 }; 560 561 /* 562 * Structure of the page that can be mapped via mmap 563 */ 564 struct perf_event_mmap_page { 565 __u32 version; /* version number of this structure */ 566 __u32 compat_version; /* lowest version this is compat with */ 567 568 /* 569 * Bits needed to read the hw events in user-space. 570 * 571 * u32 seq, time_mult, time_shift, index, width; 572 * u64 count, enabled, running; 573 * u64 cyc, time_offset; 574 * s64 pmc = 0; 575 * 576 * do { 577 * seq = pc->lock; 578 * barrier() 579 * 580 * enabled = pc->time_enabled; 581 * running = pc->time_running; 582 * 583 * if (pc->cap_usr_time && enabled != running) { 584 * cyc = rdtsc(); 585 * time_offset = pc->time_offset; 586 * time_mult = pc->time_mult; 587 * time_shift = pc->time_shift; 588 * } 589 * 590 * index = pc->index; 591 * count = pc->offset; 592 * if (pc->cap_user_rdpmc && index) { 593 * width = pc->pmc_width; 594 * pmc = rdpmc(index - 1); 595 * } 596 * 597 * barrier(); 598 * } while (pc->lock != seq); 599 * 600 * NOTE: for obvious reason this only works on self-monitoring 601 * processes. 602 */ 603 __u32 lock; /* seqlock for synchronization */ 604 __u32 index; /* hardware event identifier */ 605 __s64 offset; /* add to hardware event value */ 606 __u64 time_enabled; /* time event active */ 607 __u64 time_running; /* time event on cpu */ 608 union { 609 __u64 capabilities; 610 struct { 611 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 612 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 613 614 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 615 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 616 cap_user_time_zero : 1, /* The time_zero field is used */ 617 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 618 cap_____res : 58; 619 }; 620 }; 621 622 /* 623 * If cap_user_rdpmc this field provides the bit-width of the value 624 * read using the rdpmc() or equivalent instruction. This can be used 625 * to sign extend the result like: 626 * 627 * pmc <<= 64 - width; 628 * pmc >>= 64 - width; // signed shift right 629 * count += pmc; 630 */ 631 __u16 pmc_width; 632 633 /* 634 * If cap_usr_time the below fields can be used to compute the time 635 * delta since time_enabled (in ns) using rdtsc or similar. 636 * 637 * u64 quot, rem; 638 * u64 delta; 639 * 640 * quot = (cyc >> time_shift); 641 * rem = cyc & (((u64)1 << time_shift) - 1); 642 * delta = time_offset + quot * time_mult + 643 * ((rem * time_mult) >> time_shift); 644 * 645 * Where time_offset,time_mult,time_shift and cyc are read in the 646 * seqcount loop described above. This delta can then be added to 647 * enabled and possible running (if index), improving the scaling: 648 * 649 * enabled += delta; 650 * if (index) 651 * running += delta; 652 * 653 * quot = count / running; 654 * rem = count % running; 655 * count = quot * enabled + (rem * enabled) / running; 656 */ 657 __u16 time_shift; 658 __u32 time_mult; 659 __u64 time_offset; 660 /* 661 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 662 * from sample timestamps. 663 * 664 * time = timestamp - time_zero; 665 * quot = time / time_mult; 666 * rem = time % time_mult; 667 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 668 * 669 * And vice versa: 670 * 671 * quot = cyc >> time_shift; 672 * rem = cyc & (((u64)1 << time_shift) - 1); 673 * timestamp = time_zero + quot * time_mult + 674 * ((rem * time_mult) >> time_shift); 675 */ 676 __u64 time_zero; 677 678 __u32 size; /* Header size up to __reserved[] fields. */ 679 __u32 __reserved_1; 680 681 /* 682 * If cap_usr_time_short, the hardware clock is less than 64bit wide 683 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 684 * 685 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 686 * 687 * NOTE: this form is explicitly chosen such that cap_usr_time_short 688 * is a correction on top of cap_usr_time, and code that doesn't 689 * know about cap_usr_time_short still works under the assumption 690 * the counter doesn't wrap. 691 */ 692 __u64 time_cycles; 693 __u64 time_mask; 694 695 /* 696 * Hole for extension of the self monitor capabilities 697 */ 698 699 __u8 __reserved[116*8]; /* align to 1k. */ 700 701 /* 702 * Control data for the mmap() data buffer. 703 * 704 * User-space reading the @data_head value should issue an smp_rmb(), 705 * after reading this value. 706 * 707 * When the mapping is PROT_WRITE the @data_tail value should be 708 * written by userspace to reflect the last read data, after issueing 709 * an smp_mb() to separate the data read from the ->data_tail store. 710 * In this case the kernel will not over-write unread data. 711 * 712 * See perf_output_put_handle() for the data ordering. 713 * 714 * data_{offset,size} indicate the location and size of the perf record 715 * buffer within the mmapped area. 716 */ 717 __u64 data_head; /* head in the data section */ 718 __u64 data_tail; /* user-space written tail */ 719 __u64 data_offset; /* where the buffer starts */ 720 __u64 data_size; /* data buffer size */ 721 722 /* 723 * AUX area is defined by aux_{offset,size} fields that should be set 724 * by the userspace, so that 725 * 726 * aux_offset >= data_offset + data_size 727 * 728 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 729 * 730 * Ring buffer pointers aux_{head,tail} have the same semantics as 731 * data_{head,tail} and same ordering rules apply. 732 */ 733 __u64 aux_head; 734 __u64 aux_tail; 735 __u64 aux_offset; 736 __u64 aux_size; 737 }; 738 739 /* 740 * The current state of perf_event_header::misc bits usage: 741 * ('|' used bit, '-' unused bit) 742 * 743 * 012 CDEF 744 * |||---------|||| 745 * 746 * Where: 747 * 0-2 CPUMODE_MASK 748 * 749 * C PROC_MAP_PARSE_TIMEOUT 750 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 751 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 752 * F (reserved) 753 */ 754 755 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 756 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 757 #define PERF_RECORD_MISC_KERNEL (1 << 0) 758 #define PERF_RECORD_MISC_USER (2 << 0) 759 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 760 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 761 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 762 763 /* 764 * Indicates that /proc/PID/maps parsing are truncated by time out. 765 */ 766 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 767 /* 768 * Following PERF_RECORD_MISC_* are used on different 769 * events, so can reuse the same bit position: 770 * 771 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 772 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 773 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 774 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 775 */ 776 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 777 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 778 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 779 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 780 /* 781 * These PERF_RECORD_MISC_* flags below are safely reused 782 * for the following events: 783 * 784 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 785 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 786 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 787 * 788 * 789 * PERF_RECORD_MISC_EXACT_IP: 790 * Indicates that the content of PERF_SAMPLE_IP points to 791 * the actual instruction that triggered the event. See also 792 * perf_event_attr::precise_ip. 793 * 794 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 795 * Indicates that thread was preempted in TASK_RUNNING state. 796 * 797 * PERF_RECORD_MISC_MMAP_BUILD_ID: 798 * Indicates that mmap2 event carries build id data. 799 */ 800 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 801 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 802 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 803 /* 804 * Reserve the last bit to indicate some extended misc field 805 */ 806 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 807 808 struct perf_event_header { 809 __u32 type; 810 __u16 misc; 811 __u16 size; 812 }; 813 814 struct perf_ns_link_info { 815 __u64 dev; 816 __u64 ino; 817 }; 818 819 enum { 820 NET_NS_INDEX = 0, 821 UTS_NS_INDEX = 1, 822 IPC_NS_INDEX = 2, 823 PID_NS_INDEX = 3, 824 USER_NS_INDEX = 4, 825 MNT_NS_INDEX = 5, 826 CGROUP_NS_INDEX = 6, 827 828 NR_NAMESPACES, /* number of available namespaces */ 829 }; 830 831 enum perf_event_type { 832 833 /* 834 * If perf_event_attr.sample_id_all is set then all event types will 835 * have the sample_type selected fields related to where/when 836 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 837 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 838 * just after the perf_event_header and the fields already present for 839 * the existing fields, i.e. at the end of the payload. That way a newer 840 * perf.data file will be supported by older perf tools, with these new 841 * optional fields being ignored. 842 * 843 * struct sample_id { 844 * { u32 pid, tid; } && PERF_SAMPLE_TID 845 * { u64 time; } && PERF_SAMPLE_TIME 846 * { u64 id; } && PERF_SAMPLE_ID 847 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 848 * { u32 cpu, res; } && PERF_SAMPLE_CPU 849 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 850 * } && perf_event_attr::sample_id_all 851 * 852 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 853 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 854 * relative to header.size. 855 */ 856 857 /* 858 * The MMAP events record the PROT_EXEC mappings so that we can 859 * correlate userspace IPs to code. They have the following structure: 860 * 861 * struct { 862 * struct perf_event_header header; 863 * 864 * u32 pid, tid; 865 * u64 addr; 866 * u64 len; 867 * u64 pgoff; 868 * char filename[]; 869 * struct sample_id sample_id; 870 * }; 871 */ 872 PERF_RECORD_MMAP = 1, 873 874 /* 875 * struct { 876 * struct perf_event_header header; 877 * u64 id; 878 * u64 lost; 879 * struct sample_id sample_id; 880 * }; 881 */ 882 PERF_RECORD_LOST = 2, 883 884 /* 885 * struct { 886 * struct perf_event_header header; 887 * 888 * u32 pid, tid; 889 * char comm[]; 890 * struct sample_id sample_id; 891 * }; 892 */ 893 PERF_RECORD_COMM = 3, 894 895 /* 896 * struct { 897 * struct perf_event_header header; 898 * u32 pid, ppid; 899 * u32 tid, ptid; 900 * u64 time; 901 * struct sample_id sample_id; 902 * }; 903 */ 904 PERF_RECORD_EXIT = 4, 905 906 /* 907 * struct { 908 * struct perf_event_header header; 909 * u64 time; 910 * u64 id; 911 * u64 stream_id; 912 * struct sample_id sample_id; 913 * }; 914 */ 915 PERF_RECORD_THROTTLE = 5, 916 PERF_RECORD_UNTHROTTLE = 6, 917 918 /* 919 * struct { 920 * struct perf_event_header header; 921 * u32 pid, ppid; 922 * u32 tid, ptid; 923 * u64 time; 924 * struct sample_id sample_id; 925 * }; 926 */ 927 PERF_RECORD_FORK = 7, 928 929 /* 930 * struct { 931 * struct perf_event_header header; 932 * u32 pid, tid; 933 * 934 * struct read_format values; 935 * struct sample_id sample_id; 936 * }; 937 */ 938 PERF_RECORD_READ = 8, 939 940 /* 941 * struct { 942 * struct perf_event_header header; 943 * 944 * # 945 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 946 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 947 * # is fixed relative to header. 948 * # 949 * 950 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 951 * { u64 ip; } && PERF_SAMPLE_IP 952 * { u32 pid, tid; } && PERF_SAMPLE_TID 953 * { u64 time; } && PERF_SAMPLE_TIME 954 * { u64 addr; } && PERF_SAMPLE_ADDR 955 * { u64 id; } && PERF_SAMPLE_ID 956 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 957 * { u32 cpu, res; } && PERF_SAMPLE_CPU 958 * { u64 period; } && PERF_SAMPLE_PERIOD 959 * 960 * { struct read_format values; } && PERF_SAMPLE_READ 961 * 962 * { u64 nr, 963 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 964 * 965 * # 966 * # The RAW record below is opaque data wrt the ABI 967 * # 968 * # That is, the ABI doesn't make any promises wrt to 969 * # the stability of its content, it may vary depending 970 * # on event, hardware, kernel version and phase of 971 * # the moon. 972 * # 973 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 974 * # 975 * 976 * { u32 size; 977 * char data[size];}&& PERF_SAMPLE_RAW 978 * 979 * { u64 nr; 980 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 981 * { u64 from, to, flags } lbr[nr]; 982 * } && PERF_SAMPLE_BRANCH_STACK 983 * 984 * { u64 abi; # enum perf_sample_regs_abi 985 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 986 * 987 * { u64 size; 988 * char data[size]; 989 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 990 * 991 * { union perf_sample_weight 992 * { 993 * u64 full; && PERF_SAMPLE_WEIGHT 994 * #if defined(__LITTLE_ENDIAN_BITFIELD) 995 * struct { 996 * u32 var1_dw; 997 * u16 var2_w; 998 * u16 var3_w; 999 * } && PERF_SAMPLE_WEIGHT_STRUCT 1000 * #elif defined(__BIG_ENDIAN_BITFIELD) 1001 * struct { 1002 * u16 var3_w; 1003 * u16 var2_w; 1004 * u32 var1_dw; 1005 * } && PERF_SAMPLE_WEIGHT_STRUCT 1006 * #endif 1007 * } 1008 * } 1009 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 1010 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 1011 * { u64 abi; # enum perf_sample_regs_abi 1012 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 1013 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 1014 * { u64 size; 1015 * char data[size]; } && PERF_SAMPLE_AUX 1016 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 1017 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 1018 * }; 1019 */ 1020 PERF_RECORD_SAMPLE = 9, 1021 1022 /* 1023 * The MMAP2 records are an augmented version of MMAP, they add 1024 * maj, min, ino numbers to be used to uniquely identify each mapping 1025 * 1026 * struct { 1027 * struct perf_event_header header; 1028 * 1029 * u32 pid, tid; 1030 * u64 addr; 1031 * u64 len; 1032 * u64 pgoff; 1033 * union { 1034 * struct { 1035 * u32 maj; 1036 * u32 min; 1037 * u64 ino; 1038 * u64 ino_generation; 1039 * }; 1040 * struct { 1041 * u8 build_id_size; 1042 * u8 __reserved_1; 1043 * u16 __reserved_2; 1044 * u8 build_id[20]; 1045 * }; 1046 * }; 1047 * u32 prot, flags; 1048 * char filename[]; 1049 * struct sample_id sample_id; 1050 * }; 1051 */ 1052 PERF_RECORD_MMAP2 = 10, 1053 1054 /* 1055 * Records that new data landed in the AUX buffer part. 1056 * 1057 * struct { 1058 * struct perf_event_header header; 1059 * 1060 * u64 aux_offset; 1061 * u64 aux_size; 1062 * u64 flags; 1063 * struct sample_id sample_id; 1064 * }; 1065 */ 1066 PERF_RECORD_AUX = 11, 1067 1068 /* 1069 * Indicates that instruction trace has started 1070 * 1071 * struct { 1072 * struct perf_event_header header; 1073 * u32 pid; 1074 * u32 tid; 1075 * struct sample_id sample_id; 1076 * }; 1077 */ 1078 PERF_RECORD_ITRACE_START = 12, 1079 1080 /* 1081 * Records the dropped/lost sample number. 1082 * 1083 * struct { 1084 * struct perf_event_header header; 1085 * 1086 * u64 lost; 1087 * struct sample_id sample_id; 1088 * }; 1089 */ 1090 PERF_RECORD_LOST_SAMPLES = 13, 1091 1092 /* 1093 * Records a context switch in or out (flagged by 1094 * PERF_RECORD_MISC_SWITCH_OUT). See also 1095 * PERF_RECORD_SWITCH_CPU_WIDE. 1096 * 1097 * struct { 1098 * struct perf_event_header header; 1099 * struct sample_id sample_id; 1100 * }; 1101 */ 1102 PERF_RECORD_SWITCH = 14, 1103 1104 /* 1105 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1106 * next_prev_tid that are the next (switching out) or previous 1107 * (switching in) pid/tid. 1108 * 1109 * struct { 1110 * struct perf_event_header header; 1111 * u32 next_prev_pid; 1112 * u32 next_prev_tid; 1113 * struct sample_id sample_id; 1114 * }; 1115 */ 1116 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1117 1118 /* 1119 * struct { 1120 * struct perf_event_header header; 1121 * u32 pid; 1122 * u32 tid; 1123 * u64 nr_namespaces; 1124 * { u64 dev, inode; } [nr_namespaces]; 1125 * struct sample_id sample_id; 1126 * }; 1127 */ 1128 PERF_RECORD_NAMESPACES = 16, 1129 1130 /* 1131 * Record ksymbol register/unregister events: 1132 * 1133 * struct { 1134 * struct perf_event_header header; 1135 * u64 addr; 1136 * u32 len; 1137 * u16 ksym_type; 1138 * u16 flags; 1139 * char name[]; 1140 * struct sample_id sample_id; 1141 * }; 1142 */ 1143 PERF_RECORD_KSYMBOL = 17, 1144 1145 /* 1146 * Record bpf events: 1147 * enum perf_bpf_event_type { 1148 * PERF_BPF_EVENT_UNKNOWN = 0, 1149 * PERF_BPF_EVENT_PROG_LOAD = 1, 1150 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1151 * }; 1152 * 1153 * struct { 1154 * struct perf_event_header header; 1155 * u16 type; 1156 * u16 flags; 1157 * u32 id; 1158 * u8 tag[BPF_TAG_SIZE]; 1159 * struct sample_id sample_id; 1160 * }; 1161 */ 1162 PERF_RECORD_BPF_EVENT = 18, 1163 1164 /* 1165 * struct { 1166 * struct perf_event_header header; 1167 * u64 id; 1168 * char path[]; 1169 * struct sample_id sample_id; 1170 * }; 1171 */ 1172 PERF_RECORD_CGROUP = 19, 1173 1174 /* 1175 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1176 * the number of old bytes, 'new_len' is the number of new bytes. Either 1177 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1178 * addition or removal of a trampoline. 'bytes' contains the old bytes 1179 * followed immediately by the new bytes. 1180 * 1181 * struct { 1182 * struct perf_event_header header; 1183 * u64 addr; 1184 * u16 old_len; 1185 * u16 new_len; 1186 * u8 bytes[]; 1187 * struct sample_id sample_id; 1188 * }; 1189 */ 1190 PERF_RECORD_TEXT_POKE = 20, 1191 1192 /* 1193 * Data written to the AUX area by hardware due to aux_output, may need 1194 * to be matched to the event by an architecture-specific hardware ID. 1195 * This records the hardware ID, but requires sample_id to provide the 1196 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1197 * records from multiple events. 1198 * 1199 * struct { 1200 * struct perf_event_header header; 1201 * u64 hw_id; 1202 * struct sample_id sample_id; 1203 * }; 1204 */ 1205 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1206 1207 PERF_RECORD_MAX, /* non-ABI */ 1208 }; 1209 1210 enum perf_record_ksymbol_type { 1211 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1212 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1213 /* 1214 * Out of line code such as kprobe-replaced instructions or optimized 1215 * kprobes or ftrace trampolines. 1216 */ 1217 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1218 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1219 }; 1220 1221 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1222 1223 enum perf_bpf_event_type { 1224 PERF_BPF_EVENT_UNKNOWN = 0, 1225 PERF_BPF_EVENT_PROG_LOAD = 1, 1226 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1227 PERF_BPF_EVENT_MAX, /* non-ABI */ 1228 }; 1229 1230 #define PERF_MAX_STACK_DEPTH 127 1231 #define PERF_MAX_CONTEXTS_PER_STACK 8 1232 1233 enum perf_callchain_context { 1234 PERF_CONTEXT_HV = (__u64)-32, 1235 PERF_CONTEXT_KERNEL = (__u64)-128, 1236 PERF_CONTEXT_USER = (__u64)-512, 1237 1238 PERF_CONTEXT_GUEST = (__u64)-2048, 1239 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1240 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1241 1242 PERF_CONTEXT_MAX = (__u64)-4095, 1243 }; 1244 1245 /** 1246 * PERF_RECORD_AUX::flags bits 1247 */ 1248 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1249 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1250 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1251 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1252 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1253 1254 /* CoreSight PMU AUX buffer formats */ 1255 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1256 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1257 1258 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1259 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1260 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1261 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1262 1263 #if defined(__LITTLE_ENDIAN_BITFIELD) 1264 union perf_mem_data_src { 1265 __u64 val; 1266 struct { 1267 __u64 mem_op:5, /* type of opcode */ 1268 mem_lvl:14, /* memory hierarchy level */ 1269 mem_snoop:5, /* snoop mode */ 1270 mem_lock:2, /* lock instr */ 1271 mem_dtlb:7, /* tlb access */ 1272 mem_lvl_num:4, /* memory hierarchy level number */ 1273 mem_remote:1, /* remote */ 1274 mem_snoopx:2, /* snoop mode, ext */ 1275 mem_blk:3, /* access blocked */ 1276 mem_hops:3, /* hop level */ 1277 mem_rsvd:18; 1278 }; 1279 }; 1280 #elif defined(__BIG_ENDIAN_BITFIELD) 1281 union perf_mem_data_src { 1282 __u64 val; 1283 struct { 1284 __u64 mem_rsvd:18, 1285 mem_hops:3, /* hop level */ 1286 mem_blk:3, /* access blocked */ 1287 mem_snoopx:2, /* snoop mode, ext */ 1288 mem_remote:1, /* remote */ 1289 mem_lvl_num:4, /* memory hierarchy level number */ 1290 mem_dtlb:7, /* tlb access */ 1291 mem_lock:2, /* lock instr */ 1292 mem_snoop:5, /* snoop mode */ 1293 mem_lvl:14, /* memory hierarchy level */ 1294 mem_op:5; /* type of opcode */ 1295 }; 1296 }; 1297 #else 1298 #error "Unknown endianness" 1299 #endif 1300 1301 /* type of opcode (load/store/prefetch,code) */ 1302 #define PERF_MEM_OP_NA 0x01 /* not available */ 1303 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1304 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1305 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1306 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1307 #define PERF_MEM_OP_SHIFT 0 1308 1309 /* 1310 * PERF_MEM_LVL_* namespace being depricated to some extent in the 1311 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1312 * Supporting this namespace inorder to not break defined ABIs. 1313 * 1314 * memory hierarchy (memory level, hit or miss) 1315 */ 1316 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1317 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1318 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1319 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1320 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1321 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1322 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1323 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1324 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1325 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1326 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1327 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1328 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1329 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1330 #define PERF_MEM_LVL_SHIFT 5 1331 1332 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1333 #define PERF_MEM_REMOTE_SHIFT 37 1334 1335 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1336 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1337 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1338 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1339 /* 5-0x8 available */ 1340 #define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ 1341 #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ 1342 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1343 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1344 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1345 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1346 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1347 1348 #define PERF_MEM_LVLNUM_SHIFT 33 1349 1350 /* snoop mode */ 1351 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1352 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1353 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1354 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1355 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1356 #define PERF_MEM_SNOOP_SHIFT 19 1357 1358 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1359 #define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ 1360 #define PERF_MEM_SNOOPX_SHIFT 38 1361 1362 /* locked instruction */ 1363 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1364 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1365 #define PERF_MEM_LOCK_SHIFT 24 1366 1367 /* TLB access */ 1368 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1369 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1370 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1371 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1372 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1373 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1374 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1375 #define PERF_MEM_TLB_SHIFT 26 1376 1377 /* Access blocked */ 1378 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1379 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1380 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1381 #define PERF_MEM_BLK_SHIFT 40 1382 1383 /* hop level */ 1384 #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1385 #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1386 #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1387 #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1388 /* 5-7 available */ 1389 #define PERF_MEM_HOPS_SHIFT 43 1390 1391 #define PERF_MEM_S(a, s) \ 1392 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1393 1394 /* 1395 * single taken branch record layout: 1396 * 1397 * from: source instruction (may not always be a branch insn) 1398 * to: branch target 1399 * mispred: branch target was mispredicted 1400 * predicted: branch target was predicted 1401 * 1402 * support for mispred, predicted is optional. In case it 1403 * is not supported mispred = predicted = 0. 1404 * 1405 * in_tx: running in a hardware transaction 1406 * abort: aborting a hardware transaction 1407 * cycles: cycles from last branch (or 0 if not supported) 1408 * type: branch type 1409 * spec: branch speculation info (or 0 if not supported) 1410 */ 1411 struct perf_branch_entry { 1412 __u64 from; 1413 __u64 to; 1414 __u64 mispred:1, /* target mispredicted */ 1415 predicted:1,/* target predicted */ 1416 in_tx:1, /* in transaction */ 1417 abort:1, /* transaction abort */ 1418 cycles:16, /* cycle count to last branch */ 1419 type:4, /* branch type */ 1420 spec:2, /* branch speculation info */ 1421 new_type:4, /* additional branch type */ 1422 priv:3, /* privilege level */ 1423 reserved:31; 1424 }; 1425 1426 union perf_sample_weight { 1427 __u64 full; 1428 #if defined(__LITTLE_ENDIAN_BITFIELD) 1429 struct { 1430 __u32 var1_dw; 1431 __u16 var2_w; 1432 __u16 var3_w; 1433 }; 1434 #elif defined(__BIG_ENDIAN_BITFIELD) 1435 struct { 1436 __u16 var3_w; 1437 __u16 var2_w; 1438 __u32 var1_dw; 1439 }; 1440 #else 1441 #error "Unknown endianness" 1442 #endif 1443 }; 1444 1445 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1446