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1{
2 "enums": {
3  "COMMAND__SAIC": {
4   "entries": [
5    {"name": "INCREMENT", "value": 0},
6    {"name": "NO_INCREMENT", "value": 1}
7   ]
8  },
9  "COMMAND__SAS": {
10   "entries": [
11    {"name": "MEMORY", "value": 0},
12    {"name": "REGISTER", "value": 1}
13   ]
14  },
15  "COMMAND__SRC_SWAP": {
16   "entries": [
17    {"name": "NONE", "value": 0},
18    {"name": "8_IN_16", "value": 1},
19    {"name": "8_IN_32", "value": 2},
20    {"name": "8_IN_64", "value": 3}
21   ]
22  },
23  "CONTROL__DST_SEL": {
24   "entries": [
25    {"name": "MEM_MAPPED_REGISTER", "value": 0},
26    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
27    {"name": "TC_L2", "value": 2},
28    {"name": "GDS", "value": 3},
29    {"name": "RESERVED", "value": 4}
30   ]
31  },
32  "CONTROL__DST_SEL_cik": {
33   "entries": [
34    {"name": "MEM_MAPPED_REGISTER", "value": 0},
35    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
36    {"name": "TC_L2", "value": 2},
37    {"name": "GDS", "value": 3},
38    {"name": "RESERVED", "value": 4},
39    {"name": "MEM", "value": 5}
40   ]
41  },
42  "CONTROL__ENGINE_SEL": {
43   "entries": [
44    {"name": "ME", "value": 0},
45    {"name": "PFP", "value": 1},
46    {"name": "CE", "value": 2},
47    {"name": "DE", "value": 3}
48   ]
49  },
50  "CP_DMA_WORD1__DST_SEL": {
51   "entries": [
52    {"name": "DST_ADDR", "value": 0},
53    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
54   ]
55  },
56  "CP_DMA_WORD1__DST_SEL_cik": {
57   "entries": [
58    {"name": "DST_ADDR", "value": 0},
59    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
60    {"name": "DST_ADDR_TC_L2", "value": 3}
61   ]
62  },
63  "CP_DMA_WORD1__DST_SEL_gfx9": {
64   "entries": [
65    {"name": "DST_ADDR", "value": 0},
66    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
67    {"name": "NOWHERE", "value": 2},
68    {"name": "DST_ADDR_TC_L2", "value": 3}
69   ]
70  },
71  "CP_DMA_WORD1__ENGINE": {
72   "entries": [
73    {"name": "ME", "value": 0},
74    {"name": "PFP", "value": 1}
75   ]
76  },
77  "CP_DMA_WORD1__SRC_SEL": {
78   "entries": [
79    {"name": "SRC_ADDR", "value": 0},
80    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
81    {"name": "DATA", "value": 2}
82   ]
83  },
84  "CP_DMA_WORD1__SRC_SEL_cik": {
85   "entries": [
86    {"name": "SRC_ADDR", "value": 0},
87    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
88    {"name": "DATA", "value": 2},
89    {"name": "SRC_ADDR_TC_L2", "value": 3}
90   ]
91  },
92  "GCR_GL1_RANGE": {
93   "entries": [
94    {"name": "GL1_ALL", "value": 0},
95    {"name": "GL1_RANGE", "value": 2},
96    {"name": "GL1_FIRST_LAST", "value": 3}
97   ]
98  },
99  "GCR_GL2_RANGE": {
100   "entries": [
101    {"name": "GL2_ALL", "value": 0},
102    {"name": "GL2_VOL", "value": 1},
103    {"name": "GL2_RANGE", "value": 2},
104    {"name": "GL2_FIRST_LAST", "value": 3}
105   ]
106  },
107  "GCR_GLI_INV": {
108   "entries": [
109    {"name": "GLI_NOP", "value": 0},
110    {"name": "GLI_ALL", "value": 1},
111    {"name": "GLI_RANGE", "value": 2},
112    {"name": "GLI_FIRST_LAST", "value": 3}
113   ]
114  },
115  "GCR_SEQ": {
116   "entries": [
117    {"name": "SEQ_PARALLEL", "value": 0},
118    {"name": "SEQ_FORWARD", "value": 1},
119    {"name": "SEQ_REVERSE", "value": 2}
120   ]
121  },
122  "PWS_STAGE_SEL": {
123   "entries": [
124    {"name": "PRE_DEPTH", "value": 0},
125    {"name": "PRE_SHADER", "value": 1},
126    {"name": "PRE_COLOR", "value": 2},
127    {"name": "PRE_PIX_SHADER", "value": 3},
128    {"name": "CP_PFP", "value": 4},
129    {"name": "CP_ME", "value": 5}
130   ]
131  },
132  "PWS_COUNTER_SEL": {
133   "entries": [
134    {"name": "TS_SELECT", "value": 0},
135    {"name": "PS_SELECT", "value": 1},
136    {"name": "CS_SELECT", "value": 2}
137   ]
138  },
139  "VGT_EVENT_TYPE_gfx11": {
140   "entries": [
141    {"name": "Reserved_0x00", "value": 0},
142    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
143    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
144    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
145    {"name": "CACHE_FLUSH_TS", "value": 4},
146    {"name": "CONTEXT_DONE", "value": 5},
147    {"name": "CACHE_FLUSH", "value": 6},
148    {"name": "CS_PARTIAL_FLUSH", "value": 7},
149    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
150    {"name": "Reserved_0x09", "value": 9},
151    {"name": "VGT_STREAMOUT_RESET", "value": 10},
152    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
153    {"name": "END_OF_PIPE_IB_END", "value": 12},
154    {"name": "RST_PIX_CNT", "value": 13},
155    {"name": "BREAK_BATCH", "value": 14},
156    {"name": "VS_PARTIAL_FLUSH", "value": 15},
157    {"name": "PS_PARTIAL_FLUSH", "value": 16},
158    {"name": "FLUSH_HS_OUTPUT", "value": 17},
159    {"name": "FLUSH_DFSM", "value": 18},
160    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
161    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
162    {"name": "WAIT_SYNC", "value": 21},
163    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
164    {"name": "PERFCOUNTER_START", "value": 23},
165    {"name": "PERFCOUNTER_STOP", "value": 24},
166    {"name": "PIPELINESTAT_START", "value": 25},
167    {"name": "PIPELINESTAT_STOP", "value": 26},
168    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
169    {"name": "FLUSH_ES_OUTPUT", "value": 28},
170    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
171    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
172    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
173    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
174    {"name": "RESET_VTX_CNT", "value": 33},
175    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
176    {"name": "CS_CONTEXT_DONE", "value": 35},
177    {"name": "VGT_FLUSH", "value": 36},
178    {"name": "TGID_ROLLOVER", "value": 37},
179    {"name": "SQ_NON_EVENT", "value": 38},
180    {"name": "SC_SEND_DB_VPZ", "value": 39},
181    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
182    {"name": "FLUSH_SX_TS", "value": 41},
183    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
184    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
185    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
186    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
187    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
188    {"name": "CS_DONE", "value": 47},
189    {"name": "PS_DONE", "value": 48},
190    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
191    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
192    {"name": "THREAD_TRACE_START", "value": 51},
193    {"name": "THREAD_TRACE_STOP", "value": 52},
194    {"name": "THREAD_TRACE_MARKER", "value": 53},
195    {"name": "THREAD_TRACE_DRAW", "value": 54},
196    {"name": "THREAD_TRACE_FINISH", "value": 55},
197    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
198    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
199    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
200    {"name": "CONTEXT_SUSPEND", "value": 59},
201    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
202    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
203    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
204    {"name": "DRAW_DONE", "value": 63}
205   ]
206  }
207 },
208 "register_mappings": [
209  {
210   "comment": "This is at offset 0x415 instead of 0x414 due to a conflict with SQ_WAVE_GPR_ALLOC",
211   "chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
212   "map": {"at": 1045, "to": "pkt3"},
213   "name": "COMMAND",
214   "type_ref": "COMMAND"
215  },
216  {
217   "chips": ["gfx9", "gfx10", "gfx103", "gfx11"],
218   "map": {"at": 1045, "to": "pkt3"},
219   "name": "COMMAND",
220   "type_ref": "COMMAND_gfx9"
221  },
222  {
223   "chips": ["gfx6"],
224   "map": {"at": 880, "to": "pkt3"},
225   "name": "CONTROL",
226   "type_ref": "CONTROL"
227  },
228  {
229   "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
230   "map": {"at": 880, "to": "pkt3"},
231   "name": "CONTROL",
232   "type_ref": "CONTROL_cik"
233  },
234  {
235   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
236   "map": {"at": 1040, "to": "pkt3"},
237   "name": "CP_DMA_WORD0",
238   "type_ref": "CP_DMA_WORD0"
239  },
240  {
241   "chips": ["gfx6"],
242   "map": {"at": 1041, "to": "pkt3"},
243   "name": "CP_DMA_WORD1",
244   "type_ref": "CP_DMA_WORD1"
245  },
246  {
247   "chips": ["gfx7", "gfx8", "gfx81"],
248   "map": {"at": 1041, "to": "pkt3"},
249   "name": "CP_DMA_WORD1",
250   "type_ref": "CP_DMA_WORD1_cik"
251  },
252  {
253   "chips": ["gfx9", "gfx10", "gfx103", "gfx11"],
254   "map": {"at": 1041, "to": "pkt3"},
255   "name": "CP_DMA_WORD1",
256   "type_ref": "CP_DMA_WORD1_gfx9"
257  },
258  {
259   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
260   "map": {"at": 1042, "to": "pkt3"},
261   "name": "CP_DMA_WORD2",
262   "type_ref": "CP_DMA_WORD2"
263  },
264  {
265   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
266   "map": {"at": 1043, "to": "pkt3"},
267   "name": "CP_DMA_WORD3",
268   "type_ref": "CP_DMA_WORD3"
269  },
270  {
271   "chips": ["gfx6"],
272   "map": {"at": 1280, "to": "pkt3"},
273   "name": "DMA_DATA_WORD0",
274   "type_ref": "DMA_DATA_WORD0"
275  },
276  {
277   "chips": ["gfx7", "gfx8", "gfx81"],
278   "map": {"at": 1280, "to": "pkt3"},
279   "name": "DMA_DATA_WORD0",
280   "type_ref": "DMA_DATA_WORD0_cik"
281  },
282  {
283   "chips": ["gfx9", "gfx10", "gfx103", "gfx11"],
284   "map": {"at": 1280, "to": "pkt3"},
285   "name": "DMA_DATA_WORD0",
286   "type_ref": "DMA_DATA_WORD0_gfx9"
287  },
288  {
289   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
290   "map": {"at": 882, "to": "pkt3"},
291   "name": "DST_ADDR_HI"
292  },
293  {
294   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
295   "map": {"at": 1284, "to": "pkt3"},
296   "name": "DST_ADDR_HI"
297  },
298  {
299   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
300   "map": {"at": 881, "to": "pkt3"},
301   "name": "DST_ADDR_LO"
302  },
303  {
304   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
305   "map": {"at": 1283, "to": "pkt3"},
306   "name": "DST_ADDR_LO"
307  },
308  {
309   "chips": ["gfx10", "gfx103", "gfx11"],
310   "map": {"at": 1414, "to": "pkt3"},
311   "name": "GCR_CNTL",
312   "type_ref": "GCR_CNTL"
313  },
314  {
315   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
316   "map": {"at": 1009, "to": "pkt3"},
317   "name": "IB_BASE_HI"
318  },
319  {
320   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
321   "map": {"at": 1008, "to": "pkt3"},
322   "name": "IB_BASE_LO"
323  },
324  {
325   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
326   "map": {"at": 1010, "to": "pkt3"},
327   "name": "IB_CONTROL",
328   "type_ref": "IB_CONTROL"
329  },
330  {
331   "chips": ["gfx10", "gfx103"],
332   "map": {"at": 1168, "to": "pkt3"},
333   "name": "RELEASE_MEM_OP",
334   "type_ref": "RELEASE_MEM_OP"
335  },
336  {
337   "chips": ["gfx11"],
338   "map": {"at": 1168, "to": "pkt3"},
339   "name": "RELEASE_MEM_OP",
340   "type_ref": "RELEASE_MEM_OP_gfx11"
341  },
342  {
343   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
344   "map": {"at": 1282, "to": "pkt3"},
345   "name": "SRC_ADDR_HI"
346  },
347  {
348   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
349   "map": {"at": 1281, "to": "pkt3"},
350   "name": "SRC_ADDR_LO"
351  },
352  {
353   "chips": ["gfx11"],
354   "map": {"at": 1408, "to": "pkt3"},
355   "name": "ACQUIRE_MEM_PWS_2",
356   "type_ref": "ACQUIRE_MEM_PWS_2"
357  },
358  {
359   "chips": ["gfx11"],
360   "map": {"at": 1413, "to": "pkt3"},
361   "name": "ACQUIRE_MEM_PWS_7",
362   "type_ref": "ACQUIRE_MEM_PWS_7"
363  }
364 ],
365 "register_types": {
366  "COMMAND": {
367   "fields": [
368    {"bits": [0, 20], "name": "BYTE_COUNT"},
369    {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
370    {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
371    {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
372    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
373    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
374    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
375    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
376    {"bits": [30, 30], "name": "RAW_WAIT"}
377   ]
378  },
379  "COMMAND_gfx9": {
380   "fields": [
381    {"bits": [0, 25], "name": "BYTE_COUNT"},
382    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
383    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
384    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
385    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
386    {"bits": [30, 30], "name": "RAW_WAIT"},
387    {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
388   ]
389  },
390  "CONTROL": {
391   "fields": [
392    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
393    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
394    {"bits": [20, 20], "name": "WR_CONFIRM"},
395    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
396   ]
397  },
398  "CONTROL_cik": {
399   "fields": [
400    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
401    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
402    {"bits": [20, 20], "name": "WR_CONFIRM"},
403    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
404   ]
405  },
406  "CP_DMA_WORD0": {
407   "fields": [
408    {"bits": [0, 31], "name": "SRC_ADDR_LO"}
409   ]
410  },
411  "CP_DMA_WORD1": {
412   "fields": [
413    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
414    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
415    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
416    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
417    {"bits": [31, 31], "name": "CP_SYNC"}
418   ]
419  },
420  "CP_DMA_WORD1_cik": {
421   "fields": [
422    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
423    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
424    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
425    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
426    {"bits": [31, 31], "name": "CP_SYNC"}
427   ]
428  },
429  "CP_DMA_WORD1_gfx9": {
430   "fields": [
431    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
432    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
433    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
434    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
435    {"bits": [31, 31], "name": "CP_SYNC"}
436   ]
437  },
438  "CP_DMA_WORD2": {
439   "fields": [
440    {"bits": [0, 31], "name": "DST_ADDR_LO"}
441   ]
442  },
443  "CP_DMA_WORD3": {
444   "fields": [
445    {"bits": [0, 15], "name": "DST_ADDR_HI"}
446   ]
447  },
448  "DMA_DATA_WORD0": {
449   "fields": [
450    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
451    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
452    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
453    {"bits": [31, 31], "name": "CP_SYNC"}
454   ]
455  },
456  "DMA_DATA_WORD0_cik": {
457   "fields": [
458    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
459    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
460    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
461    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
462    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
463    {"bits": [31, 31], "name": "CP_SYNC"}
464   ]
465  },
466  "DMA_DATA_WORD0_gfx9": {
467   "fields": [
468    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
469    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
470    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
471    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
472    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
473    {"bits": [31, 31], "name": "CP_SYNC"}
474   ]
475  },
476  "GCR_CNTL": {
477   "fields": [
478    {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
479    {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
480    {"bits": [4, 4], "name": "GLM_WB"},
481    {"bits": [5, 5], "name": "GLM_INV"},
482    {"bits": [6, 6], "name": "GLK_WB"},
483    {"bits": [7, 7], "name": "GLK_INV"},
484    {"bits": [8, 8], "name": "GLV_INV"},
485    {"bits": [9, 9], "name": "GL1_INV"},
486    {"bits": [10, 10], "name": "GL2_US"},
487    {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
488    {"bits": [13, 13], "name": "GL2_DISCARD"},
489    {"bits": [14, 14], "name": "GL2_INV"},
490    {"bits": [15, 15], "name": "GL2_WB"},
491    {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
492    {"bits": [18, 18], "name": "RANGE_IS_PA"}
493   ]
494  },
495  "IB_CONTROL": {
496   "fields": [
497    {"bits": [0, 19], "name": "IB_SIZE"},
498    {"bits": [20, 20], "name": "CHAIN"},
499    {"bits": [23, 23], "name": "VALID"}
500   ]
501  },
502  "RELEASE_MEM_OP": {
503   "fields": [
504    {"bits": [0, 5], "name": "EVENT_TYPE"},
505    {"bits": [8, 11], "name": "EVENT_INDEX"},
506    {"bits": [12, 12], "name": "GLM_WB"},
507    {"bits": [13, 13], "name": "GLM_INV"},
508    {"bits": [14, 14], "name": "GLV_INV"},
509    {"bits": [15, 15], "name": "GL1_INV"},
510    {"bits": [16, 16], "name": "GL2_US"},
511    {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
512    {"bits": [19, 19], "name": "GL2_DISCARD"},
513    {"bits": [20, 20], "name": "GL2_INV"},
514    {"bits": [21, 21], "name": "GL2_WB"},
515    {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
516   ]
517  },
518  "RELEASE_MEM_OP_gfx11": {
519   "fields": [
520    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE_gfx11", "name": "EVENT_TYPE"},
521    {"bits": [7, 7], "name": "WAIT_SYNC"},
522    {"bits": [8, 11], "name": "EVENT_INDEX"},
523    {"bits": [12, 12], "name": "GLM_WB"},
524    {"bits": [13, 13], "name": "GLM_INV"},
525    {"bits": [14, 14], "name": "GLV_INV"},
526    {"bits": [15, 15], "name": "GL1_INV"},
527    {"bits": [16, 16], "name": "GL2_US"},
528    {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
529    {"bits": [19, 19], "name": "GL2_DISCARD"},
530    {"bits": [20, 20], "name": "GL2_INV"},
531    {"bits": [21, 21], "name": "GL2_WB"},
532    {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"},
533    {"bits": [24, 24], "name": "GLK_WB"},
534    {"bits": [25, 26], "name": "CACHE_POLICY"},
535    {"bits": [28, 29], "name": "EXECUTE"},
536    {"bits": [30, 30], "name": "GLK_INV"},
537    {"bits": [31, 31], "name": "PWS_ENABLE"}
538   ]
539  },
540  "ACQUIRE_MEM_PWS_2": {
541   "fields": [
542    {"bits": [11, 13], "enum_ref": "PWS_STAGE_SEL", "name": "PWS_STAGE_SEL"},
543    {"bits": [14, 15], "enum_ref": "PWS_COUNTER_SEL", "name": "PWS_COUNTER_SEL"},
544    {"bits": [17, 17], "name": "PWS_ENA2"},
545    {"bits": [18, 23], "name": "PWS_COUNT"}
546   ]
547  },
548  "ACQUIRE_MEM_PWS_7": {
549   "fields": [
550    {"bits": [31, 31], "name": "PWS_ENA"}
551   ]
552  }
553 }
554}
555