1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<isa> 26 27<!-- 28 Cat3 Instructions: three-source ALU instructions 29 --> 30 31<bitset name="#cat3-src" size="13"> 32 <doc> 33 cat3 src1 and src2, some parts are similar to cat2/cat4 src 34 encoding, but a few extra bits trimmed out to squeeze in the 35 3rd src register (dropping (abs), immed encoding, and moving 36 a few other bits elsewhere) 37 </doc> 38 <encode type="struct ir3_register *" case-prefix="REG_"/> 39</bitset> 40 41<bitset name="#cat3-src-gpr" extends="#cat3-src"> 42 <display> 43 {HALF}{SRC} 44 </display> 45 <field name="SRC" low="0" high="7" type="#reg-gpr"/> 46 <pattern low="8" high="12">00000</pattern> 47 <encode> 48 <map name="SRC">src</map> 49 </encode> 50</bitset> 51 52 53<bitset name="#cat3-src-const-or-immed" extends="#cat3-src"> 54 <override> 55 <expr>{IMMED_ENCODING}</expr> 56 <display> 57 {IMMED} 58 </display> 59 <field name="IMMED" low="0" high="11" type="uint"/> 60 <pattern pos="12">1</pattern> 61 </override> 62 63 <display> 64 {HALF}c{CONST}.{SWIZ} 65 </display> 66 <field name="SWIZ" low="0" high="1" type="#swiz"/> 67 <field name="CONST" low="2" high="10" type="uint"/> 68 <pattern low="11" high="12">10</pattern> 69 <encode> 70 <map name="CONST">src->num >> 2</map> 71 <map name="SWIZ">src->num & 0x3</map> 72 <map name="IMMED">extract_reg_uim(src)</map> 73 </encode> 74</bitset> 75 76<bitset name="#cat3-src-relative" extends="#cat3-src"> 77 <pattern low="11" high="12">01</pattern> 78 <encode> 79 <map name="OFFSET">src->array.offset</map> 80 </encode> 81</bitset> 82 83<bitset name="#cat3-src-relative-gpr" extends="#cat3-src-relative"> 84 <display> 85 {HALF}r<a0.x + {OFFSET}> 86 </display> 87 <field name="OFFSET" low="0" high="9" type="int"/> 88 <pattern pos="10">0</pattern> 89</bitset> 90 91<bitset name="#cat3-src-relative-const" extends="#cat3-src-relative"> 92 <display> 93 {HALF}c<a0.x + {OFFSET}> 94 </display> 95 <field name="OFFSET" low="0" high="9" type="int"/> 96 <pattern pos="10">1</pattern> 97</bitset> 98 99<bitset name="#instruction-cat3-base" extends="#instruction"> 100 <override expr="#cat2-cat3-nop-encoding"> 101 <display> 102 {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1}, {SRC2_NEG}{HALF}{SRC2}, {SRC3_NEG}{SRC3} 103 </display> 104 <derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/> 105 </override> 106 <display> 107 {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1_R}{SRC1}, {SRC2_NEG}{SRC2_R}{HALF}{SRC2}, {SRC3_NEG}{SRC3_R}{SRC3} 108 </display> 109 <field name="SRC2_R" pos="15" type="bool" display="(r)"/> 110 <field name="SRC3_R" pos="29" type="bool" display="(r)"/> 111 <field name="DST" low="32" high="39" type="#reg-gpr"/> 112 <field name="REPEAT" low="40" high="41" type="#rptN"/> 113 <field name="SRC1_R" pos="43" type="bool" display="(r)"/> 114 <field name="SS" pos="44" type="bool" display="(ss)"/> 115 <field name="UL" pos="45" type="bool" display="(ul)"/> 116 <field name="SRC2" low="47" high="54" type="#reg-gpr"/> 117 <!-- opcode, 4 bits --> 118 <field name="JP" pos="59" type="bool" display="(jp)"/> 119 <field name="SY" pos="60" type="bool" display="(sy)"/> 120 <pattern low="61" high="63">011</pattern> <!-- cat3 --> 121 <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> 122 <derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/> 123 <encode> 124 <map name="SRC1_NEG">!!(src->srcs[0]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 125 <map name="SRC1_R">extract_SRC1_R(src)</map> 126 <map name="SRC2_R">extract_SRC2_R(src)</map> 127 <map name="SRC3_R">!!(src->srcs[2]->flags & IR3_REG_R)</map> 128 <map name="SRC2_NEG">!!(src->srcs[1]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 129 <map name="SRC3_NEG">!!(src->srcs[2]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 130 <map name="SRC1">src->srcs[0]</map> 131 </encode> 132</bitset> 133 134<bitset name="#instruction-cat3" extends="#instruction-cat3-base"> 135 <derived name="IMMED_ENCODING" expr="#false" type="bool" display="h"/> 136 137 <field name="SRC1" low="0" high="12" type="#cat3-src"> 138 <param name="HALF"/> 139 <param name="IMMED_ENCODING"/> 140 </field> 141 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 142 143 <pattern pos="13">0</pattern> 144 145 <field name="SRC3" low="16" high="28" type="#cat3-src"> 146 <param name="HALF"/> 147 <param name="IMMED_ENCODING"/> 148 </field> 149 150 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 151 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 152 <field name="SAT" pos="42" type="bool" display="(sat)"/> 153 154 <field name="DST_CONV" pos="46" type="bool"> 155 <doc> 156 The source precision is determined by the instruction 157 opcode. If {DST_CONV} the result is widened/narrowed 158 to the opposite precision. 159 </doc> 160 </field> 161 162 <encode> 163 <map name="DST_CONV"> 164 ((src->dsts[0]->num >> 2) == 62) ? 0 : 165 !!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 166 </map> 167 </encode> 168</bitset> 169 170<!-- TODO check on pre a6xx gens --> 171<bitset name="#instruction-cat3-alt" extends="#instruction-cat3-base"> 172 <doc> 173 The difference is that this cat3 version does not support plain 174 const registers as src1/src3 but does support inmidiate values. 175 On the other hand it still supports relative gpr and consts. 176 </doc> 177 178 <gen min="600"/> 179 180 <derived name="IMMED_ENCODING" expr="#true" type="bool" display="h"/> 181 <derived name="SAT" expr="#false" type="bool" display=""/> 182 183 <field name="SRC1" low="0" high="12" type="#cat3-src"> 184 <param name="HALF"/> 185 <param name="IMMED_ENCODING"/> 186 </field> 187 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 188 189 <pattern pos="13">1</pattern> 190 191 <field name="SRC3" low="16" high="28" type="#cat3-src"> 192 <param name="HALF"/> 193 <param name="IMMED_ENCODING"/> 194 </field> 195 196 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 197 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 198 <field name="FULL" pos="42" type="bool"/> 199 <field name="DST_CONV" pos="46" type="bool"/> 200 201 <encode> 202 <map name="SRC3">src->srcs[2]</map> 203 <map name="FULL">!(src->srcs[1]->flags & IR3_REG_HALF)</map> 204 <map name="DST_CONV"> 205 ((src->dsts[0]->num >> 2) == 62) ? 0 : 206 !!((src->srcs[1]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 207 </map> 208 </encode> 209</bitset> 210 211<bitset name="mad.u16" extends="#instruction-cat3"> 212 <pattern low="55" high="58">0000</pattern> <!-- OPC --> 213 <derived name="FULL" expr="#false" type="bool"/> 214</bitset> 215 216<bitset name="madsh.u16" extends="#instruction-cat3"> 217 <pattern low="55" high="58">0001</pattern> <!-- OPC --> 218 <derived name="FULL" expr="#true" type="bool"/> 219</bitset> 220 221<bitset name="mad.s16" extends="#instruction-cat3"> 222 <pattern low="55" high="58">0010</pattern> <!-- OPC --> 223 <derived name="FULL" expr="#false" type="bool"/> 224</bitset> 225 226<bitset name="madsh.m16" extends="#instruction-cat3"> 227 <pattern low="55" high="58">0011</pattern> <!-- OPC --> 228 <derived name="FULL" expr="#true" type="bool"/> 229</bitset> 230 231<bitset name="mad.u24" extends="#instruction-cat3"> 232 <pattern low="55" high="58">0100</pattern> <!-- OPC --> 233 <derived name="FULL" expr="#true" type="bool"/> 234</bitset> 235 236<bitset name="mad.s24" extends="#instruction-cat3"> 237 <pattern low="55" high="58">0101</pattern> <!-- OPC --> 238 <derived name="FULL" expr="#true" type="bool"/> 239</bitset> 240 241<bitset name="mad.f16" extends="#instruction-cat3"> 242 <pattern low="55" high="58">0110</pattern> <!-- OPC --> 243 <derived name="FULL" expr="#false" type="bool"/> 244</bitset> 245 246<bitset name="mad.f32" extends="#instruction-cat3"> 247 <pattern low="55" high="58">0111</pattern> <!-- OPC --> 248 <derived name="FULL" expr="#true" type="bool"/> 249</bitset> 250 251<bitset name="sel.b16" extends="#instruction-cat3"> 252 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 253 <derived name="FULL" expr="#false" type="bool"/> 254</bitset> 255 256<bitset name="sel.b32" extends="#instruction-cat3"> 257 <pattern low="55" high="58">1001</pattern> <!-- OPC --> 258 <derived name="FULL" expr="#true" type="bool"/> 259</bitset> 260 261<bitset name="sel.s16" extends="#instruction-cat3"> 262 <pattern low="55" high="58">1010</pattern> <!-- OPC --> 263 <derived name="FULL" expr="#false" type="bool"/> 264</bitset> 265 266<bitset name="sel.s32" extends="#instruction-cat3"> 267 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 268 <derived name="FULL" expr="#true" type="bool"/> 269</bitset> 270 271<bitset name="sel.f16" extends="#instruction-cat3"> 272 <pattern low="55" high="58">1100</pattern> <!-- OPC --> 273 <derived name="FULL" expr="#false" type="bool"/> 274</bitset> 275 276<bitset name="sel.f32" extends="#instruction-cat3"> 277 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 278 <derived name="FULL" expr="#true" type="bool"/> 279</bitset> 280 281<bitset name="sad.s16" extends="#instruction-cat3"> 282 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 283 <derived name="FULL" expr="#false" type="bool"/> 284</bitset> 285 286<bitset name="sad.s32" extends="#instruction-cat3"> 287 <pattern low="55" high="58">1111</pattern> <!-- OPC --> 288 <derived name="FULL" expr="#false" type="bool"/> <!-- We think? --> 289</bitset> 290 291<bitset name="shrm" extends="#instruction-cat3-alt"> 292 <doc> 293 (src2 >> src1) & src3 294 </doc> 295 296 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 297</bitset> 298 299<bitset name="shlm" extends="#instruction-cat3-alt"> 300 <doc> 301 (src2 << src1) & src3 302 </doc> 303 304 <pattern low="55" high="58">1001</pattern> <!-- OPC --> 305</bitset> 306 307<bitset name="shrg" extends="#instruction-cat3-alt"> 308 <doc> 309 (src2 >> src1) | src3 310 </doc> 311 312 <pattern low="55" high="58">1010</pattern> <!-- OPC --> 313</bitset> 314 315<bitset name="shlg" extends="#instruction-cat3-alt"> 316 <doc> 317 (src2 << src1) | src3 318 </doc> 319 320 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 321</bitset> 322 323<bitset name="andg" extends="#instruction-cat3-alt"> 324 <doc> 325 (src2 & src1) | src3 326 </doc> 327 328 <pattern low="55" high="58">1100</pattern> <!-- OPC --> 329</bitset> 330 331<enum name="#signedness"> 332 <value val="0" display=".unsigned"/> 333 <value val="1" display=".mixed"/> 334</enum> 335 336<enum name="#8bitvec2pack"> 337 <value val="0" display=".low"/> 338 <value val="1" display=".high"/> 339</enum> 340 341<bitset name="#instruction-cat3-dp" extends="#instruction-cat3-base"> 342 <gen min="600"/> 343 344 <display> 345 {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME}{SRC_SIGN}{SRC_PACK} {DST}, {SRC1}, {SRC2}, {SRC3_NEG}{SRC3} 346 </display> 347 348 <derived name="FULL" expr="#true" type="bool"/> 349 350 <field name="SRC1" low="0" high="12" type="#cat3-src"> 351 <param name="HALF"/> 352 </field> 353 <field name="SRC_SIGN" pos="14" type="#signedness"/> 354 355 <pattern pos="13">1</pattern> 356 357 <field name="SRC3" low="16" high="28" type="#cat3-src"> 358 <param name="HALF"/> 359 </field> 360 <field name="SRC_PACK" pos="30" type="#8bitvec2pack"/> 361 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 362 <field name="SAT" pos="42" type="bool" display="(sat)"/> 363 364 <encode> 365 <map name="SRC3">src->srcs[2]</map> 366 <map name="SRC_SIGN">src->cat3.signedness</map> 367 <map name="SRC_PACK">src->cat3.packed</map> 368 </encode> 369</bitset> 370 371<bitset name="dp2acc" extends="#instruction-cat3-dp"> 372 <doc> 373 Given: 374 SRC1 is a i8vec2 or u8vec2 375 SRC2 is a u8vec2 376 SRC1 and SRC2 are packed into low or high halves of the registers. 377 SRC3 is a int32_t or uint32_t 378 Do: 379 DST = dot(SRC1, SRC2) + SRC3 380 </doc> 381 382 <pattern pos="46">0</pattern> 383 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 384</bitset> 385 386<bitset name="dp4acc" extends="#instruction-cat3-dp"> 387 <doc> 388 Same a dp2acc but for vec4 instead of vec2. 389 Corresponds to packed variantes of OpUDotKHR and OpSUDotKHR. 390 </doc> 391 392 <pattern pos="46">1</pattern> 393 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 394</bitset> 395 396<expr name="#wmm-dest-half"> 397 (!{DST_FULL}) 398</expr> 399 400<bitset name="#instruction-cat3-wmm" extends="#instruction-cat3-base"> 401 <gen min="600"/> 402 403 <derived name="IMMED_ENCODING" expr="#true" type="bool" display="h"/> 404 <derived name="SAT" expr="#false" type="bool" display=""/> 405 <derived name="SRC3_NEG" expr="#false" type="bool" display=""/> 406 <derived name="DST_HALF" expr="#wmm-dest-half" type="bool" display="h"/> 407 408 <field name="SRC1" low="0" high="12" type="#cat3-src"> 409 <param name="HALF"/> 410 </field> 411 412 <pattern pos="13">1</pattern> 413 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 414 415 <field name="SRC3" low="16" high="28" type="#cat3-src"> 416 <param name="HALF"/> 417 <param name="IMMED_ENCODING"/> 418 </field> 419 420 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 421 <field name="FULL" pos="31" type="bool" display=""/> 422 <field name="DST_FULL" pos="46" type="bool"/> 423 424 <encode> 425 <map name="SRC3">src->srcs[2]</map> 426 <map name="FULL">!(src->srcs[0]->flags & IR3_REG_HALF)</map> 427 <map name="DST_FULL"> 428 ((src->dsts[0]->num >> 2) == 62) ? 1 : 429 !(src->dsts[0]->flags & IR3_REG_HALF) 430 </map> 431 </encode> 432</bitset> 433 434<bitset name="wmm" extends="#instruction-cat3-wmm"> 435 <doc> 436 Given: 437 SRC1 = (x_1, x_2, x_3, x_4) - 4 consecutive registers 438 SRC2 = (y_1, y_2, y_3, y_4) - 4 consecutive registers 439 SRC3 is an immediate in range of [0, 160] 440 441 Do: 442 float y_sum = y_1 + y_2 + y_3 + y_4 443 vec4 result = (x_1 * y_sum, x_2 * y_sum, x_3 * y_sum, x_4 * y_sum) 444 445 Starting from DST reg duplicate *result* into consecutive registers 446 (1 << (SRC3 / 32)) times. 447 </doc> 448 449 <pattern pos="42">0</pattern> 450 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 451</bitset> 452 453<bitset name="wmm.accu" extends="#instruction-cat3-wmm"> 454 <doc> 455 Same as wmm but instead of overwriting DST - the result is 456 added to DST registers, however the first reg of the result 457 is always overwritten. 458 </doc> 459 460 <pattern pos="42">1</pattern> 461 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 462</bitset> 463 464</isa> 465