1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8 9<domain name="A7XX" width="32"> 10 <reg32 offset="0x0011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/> 11 <reg32 offset="0x0016" name="RBBM_GBIF_HALT"/> 12 <reg32 offset="0x0017" name="RBBM_GBIF_HALT_ACK"/> 13 <reg32 offset="0x001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> 14 <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/> 15 <reg32 offset="0x0038" name="RBBM_INT_0_MASK"> 16 <bitfield name="GPUIDLE" pos="0" type="boolean"/> 17 <bitfield name="AHBERROR" pos="1" type="boolean"/> 18 <bitfield name="CPIPCINT0" pos="4" type="boolean"/> 19 <bitfield name="CPIPCINT1" pos="5" type="boolean"/> 20 <bitfield name="ATBASYNCFIFOOVERFLOW" pos="6" type="boolean"/> 21 <bitfield name="GPCERROR" pos="7" type="boolean"/> 22 <bitfield name="SWINTERRUPT" pos="8" type="boolean"/> 23 <bitfield name="HWERROR" pos="9" type="boolean"/> 24 <bitfield name="CCU_CLEAN_DEPTH_TS" pos="10" type="boolean"/> 25 <bitfield name="CCU_CLEAN_COLOR_TS" pos="11" type="boolean"/> 26 <bitfield name="CCU_RESOLVE_CLEAN_TS" pos="12" type="boolean"/> 27 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean"/> 28 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean"/> 29 <bitfield name="RB_DONE_TS" pos="17" type="boolean"/> 30 <bitfield name="CACHE_CLEAN_TS" pos="20" type="boolean"/> 31 <bitfield name="CACHE_CLEAN_TS_LPAC" pos="21" type="boolean"/> 32 <bitfield name="ATBBUSOVERFLOW" pos="22" type="boolean"/> 33 <bitfield name="HANGDETECTINTERRUPT" pos="23" type="boolean"/> 34 <bitfield name="OUTOFBOUNDACCESS" pos="24" type="boolean"/> 35 <bitfield name="UCHETRAPINTERRUPT" pos="25" type="boolean"/> 36 <bitfield name="DEBUGBUSINTERRUPT0" pos="26" type="boolean"/> 37 <bitfield name="DEBUGBUSINTERRUPT1" pos="27" type="boolean"/> 38 <bitfield name="TSBWRITEERROR" pos="28" type="boolean"/> 39 <bitfield name="ISDBCPUIRQ" pos="30" type="boolean"/> 40 <bitfield name="ISDBUNDERDEBUG" pos="31" type="boolean"/> 41 </reg32> 42 <reg32 offset="0x003a" name="RBBM_INT_2_MASK"/> 43 <reg32 offset="0x0042" name="RBBM_SP_HYST_CNT"/> 44 <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/> 45 <reg32 offset="0x0044" name="RBBM_RAC_THRESHOLD_CNT"/> 46 <reg32 offset="0x00ae" name="RBBM_CLOCK_CNTL"/> 47 <reg32 offset="0x00b0" name="RBBM_CLOCK_CNTL_SP0"/> 48 <reg32 offset="0x00b4" name="RBBM_CLOCK_CNTL2_SP0"/> 49 <reg32 offset="0x00b8" name="RBBM_CLOCK_DELAY_SP0"/> 50 <reg32 offset="0x00bc" name="RBBM_CLOCK_HYST_SP0"/> 51 <reg32 offset="0x00c0" name="RBBM_CLOCK_CNTL_TP0"/> 52 <reg32 offset="0x00c4" name="RBBM_CLOCK_CNTL2_TP0"/> 53 <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL3_TP0"/> 54 <reg32 offset="0x00cc" name="RBBM_CLOCK_CNTL4_TP0"/> 55 <reg32 offset="0x00d0" name="RBBM_CLOCK_DELAY_TP0"/> 56 <reg32 offset="0x00d4" name="RBBM_CLOCK_DELAY2_TP0"/> 57 <reg32 offset="0x00d8" name="RBBM_CLOCK_DELAY3_TP0"/> 58 <reg32 offset="0x00dc" name="RBBM_CLOCK_DELAY4_TP0"/> 59 <reg32 offset="0x00e0" name="RBBM_CLOCK_HYST_TP0"/> 60 <reg32 offset="0x00e4" name="RBBM_CLOCK_HYST2_TP0"/> 61 <reg32 offset="0x00e8" name="RBBM_CLOCK_HYST3_TP0"/> 62 <reg32 offset="0x00ec" name="RBBM_CLOCK_HYST4_TP0"/> 63 <reg32 offset="0x00f0" name="RBBM_CLOCK_CNTL_RB0"/> 64 <reg32 offset="0x00f4" name="RBBM_CLOCK_CNTL2_RB0"/> 65 <reg32 offset="0x00f8" name="RBBM_CLOCK_CNTL_CCU0"/> 66 <reg32 offset="0x0100" name="RBBM_CLOCK_HYST_RB_CCU0"/> 67 <reg32 offset="0x0104" name="RBBM_CLOCK_CNTL_RAC"/> 68 <reg32 offset="0x0105" name="RBBM_CLOCK_CNTL2_RAC"/> 69 <reg32 offset="0x0106" name="RBBM_CLOCK_DELAY_RAC"/> 70 <reg32 offset="0x0107" name="RBBM_CLOCK_HYST_RAC"/> 71 <reg32 offset="0x0108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> 72 <reg32 offset="0x0109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> 73 <reg32 offset="0x010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> 74 <reg32 offset="0x010b" name="RBBM_CLOCK_CNTL_UCHE"/> 75 <reg32 offset="0x010f" name="RBBM_CLOCK_DELAY_UCHE"/> 76 <reg32 offset="0x0110" name="RBBM_CLOCK_HYST_UCHE"/> 77 <reg32 offset="0x0111" name="RBBM_CLOCK_MODE_VFD"/> 78 <reg32 offset="0x0112" name="RBBM_CLOCK_DELAY_VFD"/> 79 <reg32 offset="0x0113" name="RBBM_CLOCK_HYST_VFD"/> 80 <reg32 offset="0x0114" name="RBBM_CLOCK_MODE_GPC"/> 81 <reg32 offset="0x0115" name="RBBM_CLOCK_DELAY_GPC"/> 82 <reg32 offset="0x0116" name="RBBM_CLOCK_HYST_GPC"/> 83 <reg32 offset="0x0117" name="RBBM_CLOCK_DELAY_HLSQ_2"/> 84 <reg32 offset="0x0118" name="RBBM_CLOCK_CNTL_GMU_GX"/> 85 <reg32 offset="0x0119" name="RBBM_CLOCK_DELAY_GMU_GX"/> 86 <reg32 offset="0x011a" name="RBBM_CLOCK_HYST_GMU_GX"/> 87 <reg32 offset="0x011b" name="RBBM_CLOCK_MODE_HLSQ"/> 88 <reg32 offset="0x011c" name="RBBM_CLOCK_DELAY_HLSQ"/> 89 <reg32 offset="0x011d" name="RBBM_CLOCK_HYST_HLSQ"/> 90 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/> 91 <reg32 offset="0x0210" name="RBBM_STATUS"> 92 <bitfield name="CPAHBBUSYCXMASTER" pos="0" type="boolean"/> 93 <bitfield name="CPAHBBUSYCPMASTER" pos="1" type="boolean"/> 94 <bitfield name="CPBUSY" pos="2" type="boolean"/> 95 <bitfield name="GFXDBGCBUSY" pos="3" type="boolean"/> 96 <bitfield name="VBIFGXFPARTBUSY" pos="4" type="boolean"/> 97 <bitfield name="TSEBUSY" pos="5" type="boolean"/> 98 <bitfield name="RASBUSY" pos="6" type="boolean"/> 99 <bitfield name="RBBUSY" pos="7" type="boolean"/> 100 <bitfield name="CCUBUSY" pos="8" type="boolean"/> 101 <bitfield name="A2DBUSY" pos="9" type="boolean"/> 102 <bitfield name="LRZBUSY" pos="10" type="boolean"/> 103 <bitfield name="COMDCOMBUSY" pos="11" type="boolean"/> 104 <bitfield name="PCDCALLBUSY" pos="12" type="boolean"/> 105 <bitfield name="PCVSDBUSY" pos="13" type="boolean"/> 106 <bitfield name="TESSBUSY" pos="14" type="boolean"/> 107 <bitfield name="VFDBUSY" pos="15" type="boolean"/> 108 <bitfield name="VPCBUSY" pos="16" type="boolean"/> 109 <bitfield name="UCHEBUSY" pos="17" type="boolean"/> 110 <bitfield name="SPBUSY" pos="18" type="boolean"/> 111 <bitfield name="TPL1BUSY" pos="19" type="boolean"/> 112 <bitfield name="VSCBUSY" pos="20" type="boolean"/> 113 <bitfield name="HLSQBUSY" pos="21" type="boolean"/> 114 <bitfield name="GPUBUSYIGNAHBCP" pos="22" type="boolean"/> 115 <bitfield name="GPUBUSYIGNAHB" pos="23" type="boolean"/> 116 </reg32> 117 <reg32 offset="0x0213" name="RBBM_STATUS3"/> 118 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP"/> 119 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ"/> 120 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS"/> 121 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS"/> 122 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD"/> 123 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC"/> 124 <reg64 offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14"/> 125 <reg64 offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/> 126 <reg64 offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8"/> 127 <reg64 offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8"/> 128 <reg64 offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/> 129 <reg64 offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6"/> 130 <reg64 offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/> 131 <reg64 offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4"/> 132 <reg64 offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/> 133 <reg64 offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/> 134 <reg64 offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12"/> 135 <reg64 offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/> 136 <reg64 offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/> 137 <reg64 offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/> 138 <reg64 offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/> 139 <reg64 offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/> 140 <reg64 offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4"/> 141 <reg64 offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6"/> 142 <reg64 offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7"/> 143 <reg64 offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12"/> 144 <reg64 offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6"/> 145 <reg64 offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2"/> 146 <reg64 offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8"/> 147 <reg64 offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8"/> 148 <reg64 offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6"/> 149 <reg64 offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4"/> 150 <reg64 offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4"/> 151 <reg64 offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4"/> 152 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/> 153 <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/> 154 <reg32 offset="0x050b" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> 155 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> 156 <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/> 157 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS"/> 158 <reg64 offset="0x0800" name="CP_RB_BASE"/> 159 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 160 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 161 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 162 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 163 <reg32 offset="0x0808" name="CP_SQE_CNTL"/> 164 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS"/> 165 <reg32 offset="0x0821" name="CP_HW_FAULT"/> 166 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"> 167 <bitfield name="OPCODEERROR" pos="0" type="boolean"/> 168 <bitfield name="UCODEERROR" pos="1" type="boolean"/> 169 <bitfield name="CPHWFAULT" pos="2" type="boolean"/> 170 <bitfield name="REGISTERPROTECTION" pos="4" type="boolean"/> 171 <bitfield name="VSDPARITYERROR" pos="6" type="boolean"/> 172 <bitfield name="ILLEGALINSTRUCTION" pos="7" type="boolean"/> 173 <bitfield name="OPCODEERRORLPAC" pos="8" type="boolean"/> 174 <bitfield name="UCODEERRORLPAC" pos="9" type="boolean"/> 175 <bitfield name="CPHWFAULTLPAC" pos="10" type="boolean"/> 176 <bitfield name="REGISTERPROTECTIONLPAC" pos="11" type="boolean"/> 177 <bitfield name="ILLEGALINSTRUCTIONLPAC" pos="12" type="boolean"/> 178 <bitfield name="OPCODEERRORBV" pos="13" type="boolean"/> 179 <bitfield name="UCODEERRORBV" pos="14" type="boolean"/> 180 <bitfield name="CPHWFAULTBV" pos="15" type="boolean"/> 181 <bitfield name="REGISTERPROTECTIONBV" pos="16" type="boolean"/> 182 <bitfield name="ILLEGALINSTRUCTIONBV" pos="17" type="boolean"/> 183 </reg32> 184 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/> 185 <reg32 offset="0x0825" name="CP_STATUS_1"/> 186 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/> 187 <reg32 offset="0x0840" name="CP_MISC_CNTL"/> 188 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/> 189 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/> 190 <reg32 offset="0x0844" name="CP_APRIV_CNTL"/> 191 <reg32 offset="0x084f" name="CP_PROTECT_CNTL"/> 192 <reg32 offset="0x0850" name="CP_PROTECT_REG" stride="1" length="48"/> 193 <reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL"/> 194 <reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> 195 <reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> 196 <reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> 197 <reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/> 198 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS"/> 199 <reg32 offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> 200 <reg32 offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7"/> 201 <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/> 202 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> 203 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> 204 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> 205 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/> 206 <reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR"/> 207 <reg32 offset="0x090b" name="CP_DRAW_STATE_DATA"/> 208 <reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR"/> 209 <reg32 offset="0x090d" name="CP_ROQ_DBG_DATA"/> 210 <reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR"/> 211 <reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA"/> 212 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/> 213 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/> 214 <reg64 offset="0x0928" name="CP_IB1_BASE"/> 215 <reg32 offset="0x092a" name="CP_IB1_REM_SIZE"/> 216 <reg64 offset="0x092b" name="CP_IB2_BASE"/> 217 <reg32 offset="0x092d" name="CP_IB2_REM_SIZE"/> 218 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/> 219 <reg32 offset="0x098d" name="CP_AHB_CNTL"/> 220 <reg32 offset="0x0a00" name="CP_APERTURE_CNTL_HOST"/> 221 <reg32 offset="0x0a03" name="CP_APERTURE_CNTL_CD"/> 222 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS"/> 223 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT"/> 224 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR"/> 225 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA"/> 226 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR"/> 227 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA"/> 228 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR"/> 229 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA"/> 230 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR"/> 231 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA"/> 232 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR"/> 233 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA"/> 234 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR"/> 235 <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR"/> 236 <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA"/> 237 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL"/> 238 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG"/> 239 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR"/> 240 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA"/> 241 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR"/> 242 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR"/> 243 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA"/> 244 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR"/> 245 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA"/> 246 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL"/> 247 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA"/> 248 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA"/> 249 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR"/> 250 <reg32 offset="0x0cd8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 251 <reg32 offset="0x0e01" name="UCHE_MODE_CNTL"/> 252 <reg64 offset="0x0e07" name="UCHE_WRITE_THRU_BASE"/> 253 <reg64 offset="0x0e09" name="UCHE_TRAP_BASE"/> 254 <reg64 offset="0x0e0b" name="UCHE_GMEM_RANGE_MIN"/> 255 <reg64 offset="0x0e0d" name="UCHE_GMEM_RANGE_MAX"/> 256 <reg32 offset="0x0e17" name="UCHE_CACHE_WAYS"/> 257 <reg32 offset="0x0e19" name="UCHE_CLIENT_PF"/> 258 <reg32 offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/> 259 <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/> 260 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/> 261 <reg32 offset="0x1140" name="PDC_GPU_ENABLE_PDC"/> 262 <reg32 offset="0x1148" name="PDC_GPU_SEQ_START_ADDR"/> 263 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> 264 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> 265 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> 266 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/> 267 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> 268 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/> 269 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> 270 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/> 271 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/> 272 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/> 273 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/> 274 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> 275 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> 276 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> 277 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> 278 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> 279 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> 280 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> 281 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> 282 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> 283 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> 284 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> 285 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> 286 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> 287 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> 288 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> 289 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> 290 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> 291 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 292 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 293 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> 294 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/> 295 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/> 296 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 297 <reg32 offset="0x3c45" name="GBIF_HALT"/> 298 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 299 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 300 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/> 301 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 302 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/> 303 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/> 304 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/> 305 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/> 306 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/> 307 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/> 308 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/> 309 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/> 310 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/> 311 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/> 312 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/> 313 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/> 314 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/> 315 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/> 316 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/> 317 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL"/> 318 <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/> 319 <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/> 320 <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/> 321 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"/> 322 <reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 323 <reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 324 <reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/> 325 <reg32 offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6"/> 326 <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/> 327 <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> 328 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/> 329 <reg32 offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12"/> 330 <reg32 offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16"/> 331 <reg32 offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16"/> 332 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"/> 333 <reg32 offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 334 <reg32 offset="0xae6d" name="SP_READ_SEL"/> 335 <reg32 offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36"/> 336 <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"/> 337 <reg32 offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18"/> 338 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE"/> 339 <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/> 340 <reg64 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 341 <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 342 <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/> 343 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS"/> 344</domain> 345 346</database> 347