1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5 6<enum name="chip" bare="yes"> 7 <value name="A2XX"/> 8 <value name="A3XX"/> 9 <value name="A4XX"/> 10 <value name="A5XX"/> 11 <value name="A6XX"/> 12 <value name="A7XX"/> 13</enum> 14 15<enum name="adreno_pa_su_sc_draw"> 16 <value name="PC_DRAW_POINTS" value="0"/> 17 <value name="PC_DRAW_LINES" value="1"/> 18 <value name="PC_DRAW_TRIANGLES" value="2"/> 19</enum> 20 21<enum name="adreno_compare_func"> 22 <value name="FUNC_NEVER" value="0"/> 23 <value name="FUNC_LESS" value="1"/> 24 <value name="FUNC_EQUAL" value="2"/> 25 <value name="FUNC_LEQUAL" value="3"/> 26 <value name="FUNC_GREATER" value="4"/> 27 <value name="FUNC_NOTEQUAL" value="5"/> 28 <value name="FUNC_GEQUAL" value="6"/> 29 <value name="FUNC_ALWAYS" value="7"/> 30</enum> 31 32<enum name="adreno_stencil_op"> 33 <value name="STENCIL_KEEP" value="0"/> 34 <value name="STENCIL_ZERO" value="1"/> 35 <value name="STENCIL_REPLACE" value="2"/> 36 <value name="STENCIL_INCR_CLAMP" value="3"/> 37 <value name="STENCIL_DECR_CLAMP" value="4"/> 38 <value name="STENCIL_INVERT" value="5"/> 39 <value name="STENCIL_INCR_WRAP" value="6"/> 40 <value name="STENCIL_DECR_WRAP" value="7"/> 41</enum> 42 43<enum name="adreno_rb_blend_factor"> 44 <value name="FACTOR_ZERO" value="0"/> 45 <value name="FACTOR_ONE" value="1"/> 46 <value name="FACTOR_SRC_COLOR" value="4"/> 47 <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/> 48 <value name="FACTOR_SRC_ALPHA" value="6"/> 49 <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/> 50 <value name="FACTOR_DST_COLOR" value="8"/> 51 <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/> 52 <value name="FACTOR_DST_ALPHA" value="10"/> 53 <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/> 54 <value name="FACTOR_CONSTANT_COLOR" value="12"/> 55 <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/> 56 <value name="FACTOR_CONSTANT_ALPHA" value="14"/> 57 <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/> 58 <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/> 59 <value name="FACTOR_SRC1_COLOR" value="20"/> 60 <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/> 61 <value name="FACTOR_SRC1_ALPHA" value="22"/> 62 <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/> 63</enum> 64 65<bitset name="adreno_rb_stencilrefmask" inline="yes"> 66 <bitfield name="STENCILREF" low="0" high="7" type="hex"/> 67 <bitfield name="STENCILMASK" low="8" high="15" type="hex"/> 68 <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/> 69</bitset> 70 71<enum name="adreno_rb_surface_endian"> 72 <value name="ENDIAN_NONE" value="0"/> 73 <value name="ENDIAN_8IN16" value="1"/> 74 <value name="ENDIAN_8IN32" value="2"/> 75 <value name="ENDIAN_16IN32" value="3"/> 76 <value name="ENDIAN_8IN64" value="4"/> 77 <value name="ENDIAN_8IN128" value="5"/> 78</enum> 79 80<enum name="adreno_rb_dither_mode"> 81 <value name="DITHER_DISABLE" value="0"/> 82 <value name="DITHER_ALWAYS" value="1"/> 83 <value name="DITHER_IF_ALPHA_OFF" value="2"/> 84</enum> 85 86<enum name="adreno_rb_depth_format"> 87 <value name="DEPTHX_16" value="0"/> 88 <value name="DEPTHX_24_8" value="1"/> 89 <value name="DEPTHX_32" value="2"/> 90</enum> 91 92<enum name="adreno_rb_copy_control_mode"> 93 <value name="RB_COPY_RESOLVE" value="1"/> 94 <value name="RB_COPY_CLEAR" value="2"/> 95 <value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? --> 96</enum> 97 98<bitset name="adreno_reg_xy" inline="yes"> 99 <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/> 100 <bitfield name="X" low="0" high="14" type="uint"/> 101 <bitfield name="Y" low="16" high="30" type="uint"/> 102</bitset> 103 104<bitset name="adreno_cp_protect" inline="yes"> 105 <bitfield name="BASE_ADDR" low="0" high="16"/> 106 <bitfield name="MASK_LEN" low="24" high="28"/> 107 <bitfield name="TRAP_WRITE" pos="29"/> 108 <bitfield name="TRAP_READ" pos="30"/> 109</bitset> 110 111<domain name="AXXX" width="32"> 112 <brief>Registers in common between a2xx and a3xx</brief> 113 114 <reg32 offset="0x01c0" name="CP_RB_BASE"/> 115 <reg32 offset="0x01c1" name="CP_RB_CNTL"> 116 <bitfield name="BUFSZ" low="0" high="5"/> 117 <bitfield name="BLKSZ" low="8" high="13"/> 118 <bitfield name="BUF_SWAP" low="16" high="17"/> 119 <bitfield name="POLL_EN" pos="20" type="boolean"/> 120 <bitfield name="NO_UPDATE" pos="27" type="boolean"/> 121 <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/> 122 </reg32> 123 <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR"> 124 <bitfield name="SWAP" low="0" high="1" type="uint"/> 125 <bitfield name="ADDR" low="2" high="31" shr="2"/> 126 </reg32> 127 <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/> 128 <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/> 129 <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/> 130 <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/> 131 <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/> 132 <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS"> 133 <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/> 134 <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/> 135 <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/> 136 </reg32> 137 <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS"> 138 <bitfield name="MEQ_END" low="16" high="20" type="uint"/> 139 <bitfield name="ROQ_END" low="24" high="28" type="uint"/> 140 </reg32> 141 <reg32 offset="0x01d7" name="CP_CSQ_AVAIL"> 142 <bitfield name="RING" low="0" high="6" type="uint"/> 143 <bitfield name="IB1" low="8" high="14" type="uint"/> 144 <bitfield name="IB2" low="16" high="22" type="uint"/> 145 </reg32> 146 <reg32 offset="0x01d8" name="CP_STQ_AVAIL"> 147 <bitfield name="ST" low="0" high="6" type="uint"/> 148 </reg32> 149 <reg32 offset="0x01d9" name="CP_MEQ_AVAIL"> 150 <bitfield name="MEQ" low="0" high="4" type="uint"/> 151 </reg32> 152 <reg32 offset="0x01dc" name="SCRATCH_UMSK"> 153 <bitfield name="UMSK" low="0" high="7" type="uint"/> 154 <bitfield name="SWAP" low="16" high="17" type="uint"/> 155 </reg32> 156 <reg32 offset="0x01dd" name="SCRATCH_ADDR"/> 157 <reg32 offset="0x01ea" name="CP_ME_RDADDR"/> 158 159 <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/> 160 <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/> 161 <reg32 offset="0x01f2" name="CP_INT_CNTL"> 162 <bitfield name="SW_INT_MASK" pos="19" type="boolean"/> 163 <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/> 164 <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/> 165 <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/> 166 <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/> 167 <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/> 168 <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/> 169 <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/> 170 <bitfield name="RB_INT_MASK" pos="31" type="boolean"/> 171 </reg32> 172 <reg32 offset="0x01f3" name="CP_INT_STATUS"/> 173 <reg32 offset="0x01f4" name="CP_INT_ACK"/> 174 <reg32 offset="0x01f6" name="CP_ME_CNTL"> 175 <bitfield name="BUSY" pos="29" type="boolean"/> 176 <bitfield name="HALT" pos="28" type="boolean"/> 177 </reg32> 178 <reg32 offset="0x01f7" name="CP_ME_STATUS"/> 179 <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/> 180 <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/> 181 <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/> 182 <reg32 offset="0x01fc" name="CP_DEBUG"> 183 <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/> 184 <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/> 185 <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/> 186 <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/> 187 <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/> 188 <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/> 189 <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/> 190 <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/> 191 </reg32> 192 <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT"> 193 <bitfield name="RPTR" low="0" high="6" type="uint"/> 194 <bitfield name="WPTR" low="16" high="22" type="uint"/> 195 </reg32> 196 <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT"> 197 <bitfield name="RPTR" low="0" high="6" type="uint"/> 198 <bitfield name="WPTR" low="16" high="22" type="uint"/> 199 </reg32> 200 <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT"> 201 <bitfield name="RPTR" low="0" high="6" type="uint"/> 202 <bitfield name="WPTR" low="16" high="22" type="uint"/> 203 </reg32> 204 205 <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/> 206 <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/> 207 <reg32 offset="0x044d" name="CP_ST_BASE"/> 208 <reg32 offset="0x044e" name="CP_ST_BUFSZ"/> 209 <reg32 offset="0x044f" name="CP_MEQ_STAT"/> 210 <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/> 211 <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/> 212 <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/> 213 <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/> 214 <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/> 215 <reg32 offset="0x0458" name="CP_IB1_BASE"/> 216 <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/> 217 <reg32 offset="0x045a" name="CP_IB2_BASE"/> 218 <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/> 219 <reg32 offset="0x047f" name="CP_STAT"> 220 <bitfield pos="31" name="CP_BUSY"/> 221 <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/> 222 <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/> 223 <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/> 224 <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/> 225 <bitfield pos="26" name="ME_BUSY"/> 226 <bitfield pos="25" name="MIU_WR_C_BUSY"/> 227 <bitfield pos="23" name="CP_3D_BUSY"/> 228 <bitfield pos="22" name="CP_NRT_BUSY"/> 229 <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/> 230 <bitfield pos="20" name="RCIU_ME_BUSY"/> 231 <bitfield pos="19" name="RCIU_PFP_BUSY"/> 232 <bitfield pos="18" name="MEQ_RING_BUSY"/> 233 <bitfield pos="17" name="PFP_BUSY"/> 234 <bitfield pos="16" name="ST_QUEUE_BUSY"/> 235 <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/> 236 <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/> 237 <bitfield pos="11" name="RING_QUEUE_BUSY"/> 238 <bitfield pos="10" name="CSF_BUSY"/> 239 <bitfield pos="9" name="CSF_ST_BUSY"/> 240 <bitfield pos="8" name="EVENT_BUSY"/> 241 <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/> 242 <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/> 243 <bitfield pos="5" name="CSF_RING_BUSY"/> 244 <bitfield pos="4" name="RCIU_BUSY"/> 245 <bitfield pos="3" name="RBIU_BUSY"/> 246 <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/> 247 <bitfield pos="1" name="MIU_RD_REQ_BUSY"/> 248 <bitfield pos="0" name="MIU_WR_BUSY"/> 249 </reg32> 250 <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/> 251 <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/> 252 <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/> 253 <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/> 254 <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/> 255 <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/> 256 <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/> 257 <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/> 258 259 <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/> 260 <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/> 261 <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/> 262 <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/> 263 <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/> 264 <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/> 265 <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/> 266 <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/> 267 <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/> 268 <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/> 269 <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/> 270 <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/> 271 <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/> 272 <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/> 273 <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/> 274 <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/> 275 <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/> 276 <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/> 277 278</domain> 279 280<!-- 281 Common between A3xx and A4xx: 282 --> 283 284<enum name="a3xx_rop_code"> 285 <value name="ROP_CLEAR" value="0"/> 286 <value name="ROP_NOR" value="1"/> 287 <value name="ROP_AND_INVERTED" value="2"/> 288 <value name="ROP_COPY_INVERTED" value="3"/> 289 <value name="ROP_AND_REVERSE" value="4"/> 290 <value name="ROP_INVERT" value="5"/> 291 <value name="ROP_XOR" value="6"/> 292 <value name="ROP_NAND" value="7"/> 293 <value name="ROP_AND" value="8"/> 294 <value name="ROP_EQUIV" value="9"/> 295 <value name="ROP_NOOP" value="10"/> 296 <value name="ROP_OR_INVERTED" value="11"/> 297 <value name="ROP_COPY" value="12"/> 298 <value name="ROP_OR_REVERSE" value="13"/> 299 <value name="ROP_OR" value="14"/> 300 <value name="ROP_SET" value="15"/> 301</enum> 302 303<enum name="a3xx_render_mode"> 304 <value name="RB_RENDERING_PASS" value="0"/> 305 <value name="RB_TILING_PASS" value="1"/> 306 <value name="RB_RESOLVE_PASS" value="2"/> 307 <value name="RB_COMPUTE_PASS" value="3"/> 308</enum> 309 310<enum name="a3xx_msaa_samples"> 311 <value name="MSAA_ONE" value="0"/> 312 <value name="MSAA_TWO" value="1"/> 313 <value name="MSAA_FOUR" value="2"/> 314 <value name="MSAA_EIGHT" value="3"/> 315</enum> 316 317<enum name="a3xx_threadmode"> 318 <value value="0" name="MULTI"/> 319 <value value="1" name="SINGLE"/> 320</enum> 321 322<enum name="a3xx_instrbuffermode"> 323 <!-- 324 When shader size goes above ~128 or so, blob switches to '0' 325 and doesn't emit shader in cmdstream. When either is '0' it 326 doesn't get emitted via CP_LOAD_STATE. When only one is 327 '0' the other gets size 256-others_size. So I think that: 328 BUFFER => execute out of state memory 329 CACHE => use available state memory as local cache 330 NOTE that when CACHE mode, also set CACHEINVALID flag! 331 332 TODO check if that 256 size is same for all a3xx 333 --> 334 <value value="0" name="CACHE"/> 335 <value value="1" name="BUFFER"/> 336</enum> 337 338<enum name="a3xx_threadsize"> 339 <value value="0" name="TWO_QUADS"/> 340 <value value="1" name="FOUR_QUADS"/> 341</enum> 342 343<enum name="a3xx_color_swap"> 344 <value name="WZYX" value="0"/> 345 <value name="WXYZ" value="1"/> 346 <value name="ZYXW" value="2"/> 347 <value name="XYZW" value="3"/> 348</enum> 349 350<enum name="a3xx_rb_blend_opcode"> 351 <value name="BLEND_DST_PLUS_SRC" value="0"/> 352 <value name="BLEND_SRC_MINUS_DST" value="1"/> 353 <value name="BLEND_DST_MINUS_SRC" value="2"/> 354 <value name="BLEND_MIN_DST_SRC" value="3"/> 355 <value name="BLEND_MAX_DST_SRC" value="4"/> 356</enum> 357 358<enum name="a4xx_tess_spacing"> 359 <value name="EQUAL_SPACING" value="0"/> 360 <value name="ODD_SPACING" value="2"/> 361 <value name="EVEN_SPACING" value="3"/> 362</enum> 363 364<doc>Address mode for a5xx+</doc> 365<enum name="a5xx_address_mode"> 366 <value name="ADDR_32B" value="0"/> 367 <value name="ADDR_64B" value="1"/> 368</enum> 369 370<doc> 371 Line mode for a5xx+ 372 Note that Bresenham lines are only supported with MSAA disabled. 373</doc> 374<enum name="a5xx_line_mode"> 375 <value value="0x0" name="BRESENHAM"/> 376 <value value="0x1" name="RECTANGULAR"/> 377</enum> 378 379</database> 380 381