1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5 6<!-- 7 This documents the internal register space used by the CP firmware since 8 the afuc instruction set was introduced. 9--> 10 11<domain name="A5XX_CONTROL_REG" width="32"> 12 <reg64 name="IB1_BASE" offset="0x0b0"/> 13 <reg32 name="IB1_DWORDS" offset="0x0b2"/> 14 <reg64 name="IB2_BASE" offset="0x0b4"/> 15 <reg32 name="IB2_DWORDS" offset="0x0b6"/> 16 17 <doc> 18 To use these, write the address and number of dwords, then read 19 the result from $addr. 20 </doc> 21 <reg64 name="MEM_READ_ADDR" offset="0x0b8"/> 22 <reg32 name="MEM_READ_DWORDS" offset="0x0ba"/> 23</domain> 24 25<domain name="A6XX_CONTROL_REG" width="32"> 26 <reg32 name="RB_RPTR" offset="0x001"/> 27 <doc> 28 Instruction to jump to when the CP is preempted to perform a 29 context switch, initialized to entry 15 of the jump table at 30 bootup. 31 </doc> 32 <reg32 name="PREEMPT_INSTR" offset="0x004"/> 33 34 <reg64 name="IB1_BASE" offset="0x010"/> 35 <reg32 name="IB1_DWORDS" offset="0x012"/> 36 <reg64 name="IB2_BASE" offset="0x014"/> 37 <reg32 name="IB2_DWORDS" offset="0x016"/> 38 39 <reg64 name="MEM_READ_ADDR" offset="0x018"/> 40 <reg32 name="MEM_READ_DWORDS" offset="0x01a"/> 41 42 <reg32 name="REG_WRITE_ADDR" offset="0x024"/> 43 <doc> 44 Writing to this triggers a register write and auto-increments 45 REG_WRITE_ADDR. 46 47 Note that there seems to be some upper bits that are possilby 48 flags, ie: 49 50 l284: 0d12: 8a8c0003 mov $0c, 0x0003 << 20 51 GPR: $0c: 00300000 52 0d13: 318c9e0b or $0c, $0c, 0x9e0b 53 GPR: $0c: 00309e0b 54 0d14: a80c0024 cwrite $0c, [$00 + @REG_WRITE_ADDR], 0x0 55 CTRL: @REG_WRITE_ADDR: 00309e0b 56 57 </doc> 58 <reg32 name="REG_WRITE" offset="0x025"/> 59 60 <doc> After setting these, read result from $addr2 </doc> 61 <reg32 name="REG_READ_DWORDS" offset="0x026"/> 62 <reg32 name="REG_READ_ADDR" offset="0x027"/> 63 64 <doc> 65 Write to increase WFI_PEND_CTR, decremented by WFI_PEND_DECR 66 pipe register. 67 </doc> 68 <reg32 name="WFI_PEND_INCR" offset="0x030"/> 69 <reg32 name="QUERY_PEND_INCR" offset="0x031"/> 70 <reg32 name="CACHE_FLUSH_PEND_INCR" offset="0x031"/> 71 72 <reg32 name="WFI_PEND_CTR" offset="0x038"/> 73 <reg32 name="QUERY_PEND_CTR" offset="0x039"/> 74 <reg32 name="CACHE_FLUSH_PEND_CTR" offset="0x03a"/> 75 76 <reg32 name="DRAW_STATE_SEL" offset="0x041"> 77 <doc> 78 SQE writes DRAW_STATE_SEL to select the SDS state group, and 79 then reads out the SDS header (DRAW_STATE_HDR), ie. the first 80 dword in the state group entry (see CP_SET_DRAW_STATE), and 81 base address of the state group cmdstream (DRAW_STATE_BASE) 82 </doc> 83 </reg32> 84 <reg64 name="SDS_BASE" offset="0x042"> 85 <doc> 86 base address for executing draw state group when IB_LEVEL 87 is set to 3 (ie. it's a bit like IB3 equiv of IBn_BASE) 88 89 Note that SDS_BASE/SDS_DWORDS seem to be per-state-group, 90 the values reflected switch when DRAW_STATE_SEL is written. 91 </doc> 92 </reg64> 93 <reg32 name="SDS_DWORDS" offset="0x044"> 94 <doc> 95 state group equiv of IBn_DWORDS 96 </doc> 97 </reg32> 98 99 <reg64 name="DRAW_STATE_BASE" offset="0x045"/> 100 <reg32 name="DRAW_STATE_HDR" offset="0x047"> 101 <doc> 102 Contains information from the first dword of the state group 103 entry in CP_SET_DRAW_STATE, but format isn't exactly the 104 same. The # of dwords is in low 16b, and mode mask is in 105 high 16 bits 106 </doc> 107 </reg32> 108 <reg32 name="DRAW_STATE_ACTIVE_BITMASK" offset="0x049"/> 109 <reg32 name="DRAW_STATE_SET" offset="0x04a"/> 110 111 <doc> Controls whether RB, IB1, or IB2 is executed </doc> 112 <reg32 name="IB_LEVEL" offset="0x054"/> 113 114 <doc> Controls high 32 bits used by load and store afuc instructions </doc> 115 <reg32 name="LOAD_STORE_HI" offset="0x058"/> 116 117 <doc> Used to initialize the jump table for handling packets at bootup </doc> 118 <reg32 name="PACKET_TABLE_WRITE_ADDR" offset="0x060"/> 119 <reg32 name="PACKET_TABLE_WRITE" offset="0x061"/> 120 121 <reg32 name="PREEMPT_ENABLE" offset="0x071"/> 122 <reg32 name="SECURE_MODE" offset="0x075"/> 123 124 <!-- 125 Note: I think that registers above 0x100 are actually just a 126 scratch space which can be used by firmware however it wants, 127 so these might change if the the firmware is updated. 128 --> 129 130 <doc> 131 These are addresses of various preemption records for the 132 current context. When context switching, the CP will save the 133 current state into these buffers, restore the state of the 134 next context from the buffers in the corresponding 135 CP_CONTEXT_SWITCH_PRIV_* registers written by the kernel, 136 then set these internal registers to the contents of 137 those registers. The kernel sets the initial values via 138 CP_SET_PSEUDO_REG on startup, and from then on the firmware 139 keeps track of them. 140 </doc> 141 <reg64 name="SAVE_REGISTER_SMMU_INFO" offset="0x110"/> 142 <reg64 name="SAVE_REGISTER_PRIV_NON_SECURE" offset="0x112"/> 143 <reg64 name="SAVE_REGISTER_PRIV_SECURE" offset="0x114"/> 144 <reg64 name="SAVE_REGISTER_NON_PRIV" offset="0x116"/> 145 <reg64 name="SAVE_REGISTER_COUNTER" offset="0x118"/> 146 147 <doc> 148 Used only during preemption, saved and restored from the "info" 149 field of a6xx_preemption_record. From the downstream kernel: 150 151 "Type of record. Written non-zero (usually) by CP. 152 we must set to zero for all ringbuffers." 153 </doc> 154 155 <reg32 name="PREEMPTION_INFO" offset="0x126"/> 156 157 <doc> 158 Seems to be a shadow for PC_MARKER 159 </doc> 160 <reg32 name="MARKER" offset="0x12a"/> 161 162 <doc> 163 Set by SET_MARKER, used to conditionally execute 164 CP_COND_REG_EXEC and draw states. 165 </doc> 166 <reg32 name="MODE_BITMASK" offset="0x12b"/> 167 168 <reg32 name="SCRATCH_REG0" offset="0x170"/> 169 <reg32 name="SCRATCH_REG1" offset="0x171"/> 170 <reg32 name="SCRATCH_REG2" offset="0x172"/> 171 <reg32 name="SCRATCH_REG3" offset="0x173"/> 172 <reg32 name="SCRATCH_REG4" offset="0x174"/> 173 <reg32 name="SCRATCH_REG5" offset="0x175"/> 174 <reg32 name="SCRATCH_REG6" offset="0x176"/> 175 <reg32 name="SCRATCH_REG7" offset="0x177"/> 176</domain> 177 178</database> 179