1 /* 2 * Copyright 2022 Google LLC 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef DRM_HW_H_ 7 #define DRM_HW_H_ 8 9 struct virgl_renderer_capset_drm { 10 uint32_t wire_format_version; 11 /* Underlying drm device version: */ 12 uint32_t version_major; 13 uint32_t version_minor; 14 uint32_t version_patchlevel; 15 #define VIRTGPU_DRM_CONTEXT_MSM 1 16 uint32_t context_type; 17 uint32_t pad; 18 union { 19 struct { 20 uint32_t has_cached_coherent; 21 uint32_t priorities; 22 uint64_t va_start; 23 uint64_t va_size; 24 uint32_t gpu_id; 25 uint32_t gmem_size; 26 uint64_t gmem_base; 27 uint64_t chip_id; 28 uint32_t max_freq; 29 } msm; /* context_type == VIRTGPU_DRM_CONTEXT_MSM */ 30 } u; 31 }; 32 33 #endif /* DRM_HW_H_ */ 34