Lines Matching +full:sd +full:- +full:uhs +full:- +full:ddr50
1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
135 * open ended multi-blk IO. Otherwise the TC INT wouldn't
169 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
170 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
300 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
301 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
302 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
303 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
304 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
305 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
306 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
307 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
308 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
309 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
310 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
311 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
312 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
319 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
324 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
329 return data->socdata == &usdhc_imx6q_data; in is_imx6q_usdhc()
334 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
339 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
345 #define DRIVER_NAME "sdhci-esdhc-imx"
347 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
366 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); in esdhc_dump_debug_regs()
378 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, in esdhc_wait_for_card_clock_gate_off()
380 if (ret == -ETIMEDOUT) in esdhc_wait_for_card_clock_gate_off()
381 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); in esdhc_wait_for_card_clock_gate_off()
388 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
394 /* move dat[0-3] bits */ in esdhc_readl_le()
401 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
402 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
420 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
421 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
430 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in esdhc_readl_le()
434 * Do not advertise faster UHS modes if there are no in esdhc_readl_le()
437 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || in esdhc_readl_le()
438 IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
461 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
464 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
466 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
486 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
488 * re-sample it by the following steps. in esdhc_writel_le()
490 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
492 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
494 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
503 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
507 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
509 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
511 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
516 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
517 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
521 writel(val, host->ioaddr + reg); in esdhc_writel_le()
543 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
548 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
549 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
550 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
552 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
567 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
575 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
581 return readw(host->ioaddr + reg); in esdhc_readw_le()
592 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
597 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
602 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
607 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
608 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_writew_le()
609 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
617 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
618 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
619 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
620 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
637 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
638 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
642 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
643 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
644 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
645 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
647 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
649 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
654 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
661 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
667 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
690 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
696 imx_data->scratchpad = val; in esdhc_writew_le()
700 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
703 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
704 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
705 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
709 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
711 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
712 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
728 val = readl(host->ioaddr + reg); in esdhc_readb_le()
737 return readb(host->ioaddr + reg); in esdhc_readb_le()
777 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
802 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
804 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
805 imx_data->is_ddr = 0; in esdhc_writeb_le()
823 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
830 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
838 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
839 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
846 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
848 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
853 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
863 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
864 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
865 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
866 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
876 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { in esdhc_pltfm_set_clock()
879 max_clock = imx_data->is_ddr ? 45000000 : 150000000; in esdhc_pltfm_set_clock()
891 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
892 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
893 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
896 div--; in esdhc_pltfm_set_clock()
905 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, in esdhc_pltfm_set_clock()
907 if (ret == -ETIMEDOUT) in esdhc_pltfm_set_clock()
908 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); in esdhc_pltfm_set_clock()
911 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
913 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
922 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
924 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
926 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
928 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
934 return -ENOSYS; in esdhc_pltfm_get_ro()
963 * DDR50, normally does not require tuning for DDR50 mode. in usdhc_execute_tuning()
965 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
982 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, in esdhc_prepare_tuning()
984 if (ret == -ETIMEDOUT) in esdhc_prepare_tuning()
985 dev_warn(mmc_dev(host->mmc), in esdhc_prepare_tuning()
988 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
991 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
992 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
993 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
995 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
1002 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1005 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1016 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
1025 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
1026 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
1035 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
1038 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
1049 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1050 if (ios->enhanced_strobe) in esdhc_hs400_enhanced_strobe()
1054 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1058 unsigned int uhs) in esdhc_change_pinstate() argument
1064 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
1066 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
1067 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
1068 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
1069 return -EINVAL; in esdhc_change_pinstate()
1071 switch (uhs) { in esdhc_change_pinstate()
1074 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
1079 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
1083 return pinctrl_select_default_state(mmc_dev(host->mmc)); in esdhc_change_pinstate()
1086 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
1107 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
1109 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
1114 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1116 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1122 if (imx_data->boarddata.strobe_dll_delay_target) in esdhc_set_strobe_dll()
1123 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; in esdhc_set_strobe_dll()
1129 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1132 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, in esdhc_set_strobe_dll()
1134 if (ret == -ETIMEDOUT) in esdhc_set_strobe_dll()
1135 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
1148 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
1149 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1152 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1153 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
1154 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
1155 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1158 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1160 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, in esdhc_reset_tuning()
1162 if (ret == -ETIMEDOUT) in esdhc_reset_tuning()
1163 dev_warn(mmc_dev(host->mmc), in esdhc_reset_tuning()
1170 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1172 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1182 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
1185 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1187 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
1196 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1201 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1202 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1203 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
1205 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1210 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1215 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1216 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1218 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1266 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in esdhc_cqhci_irq()
1303 struct cqhci_host *cq_host = host->mmc->cqe_private; in sdhci_esdhc_imx_hwinit()
1311 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1324 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1326 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1332 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1333 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1336 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1347 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_hwinit()
1348 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1350 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1352 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_imx_hwinit()
1355 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1356 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1364 if (imx_data->boarddata.tuning_start_tap) in sdhci_esdhc_imx_hwinit()
1365 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1369 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1370 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1388 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1389 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in sdhci_esdhc_imx_hwinit()
1395 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1397 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1401 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card in sdhci_esdhc_imx_hwinit()
1420 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable()
1433 if (count-- == 0) { in esdhc_cqe_enable()
1434 dev_warn(mmc_dev(host->mmc), in esdhc_cqe_enable()
1447 if (host->flags & SDHCI_REQ_USE_DMA) in esdhc_cqe_enable()
1449 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) in esdhc_cqe_enable()
1461 dev_err(mmc_dev(host->mmc), in esdhc_cqe_enable()
1485 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1486 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1489 if (of_get_property(np, "fsl,wp-controller", NULL)) in sdhci_esdhc_imx_probe_dt()
1490 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1497 if (of_property_read_bool(np, "wp-gpios")) in sdhci_esdhc_imx_probe_dt()
1498 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1500 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1501 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1502 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1504 of_property_read_u32(np, "fsl,strobe-dll-delay-target", in sdhci_esdhc_imx_probe_dt()
1505 &boarddata->strobe_dll_delay_target); in sdhci_esdhc_imx_probe_dt()
1506 if (of_find_property(np, "no-1-8-v", NULL)) in sdhci_esdhc_imx_probe_dt()
1507 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1509 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1510 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1512 mmc_of_parse_voltage(np, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1514 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { in sdhci_esdhc_imx_probe_dt()
1515 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1517 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1522 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1526 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1527 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1537 return -ENODEV; in sdhci_esdhc_imx_probe_dt()
1544 of_match_device(imx_esdhc_dt_ids, &pdev->dev); in sdhci_esdhc_imx_probe()
1560 imx_data->socdata = of_id->data; in sdhci_esdhc_imx_probe()
1562 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1563 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_imx_probe()
1565 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1566 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1567 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1571 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1572 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1573 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1577 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1578 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1579 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1583 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1584 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1585 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1588 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1591 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1595 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1596 if (IS_ERR(imx_data->pinctrl)) in sdhci_esdhc_imx_probe()
1597 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); in sdhci_esdhc_imx_probe()
1600 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1601 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1604 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_esdhc_imx_probe()
1606 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1607 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1610 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1611 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1612 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1618 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; in sdhci_esdhc_imx_probe()
1625 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1629 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1630 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1632 if (host->mmc->caps & MMC_CAP_8_BIT_DATA && in sdhci_esdhc_imx_probe()
1633 imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1634 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; in sdhci_esdhc_imx_probe()
1636 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) in sdhci_esdhc_imx_probe()
1637 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; in sdhci_esdhc_imx_probe()
1639 if (host->mmc->caps & MMC_CAP_8_BIT_DATA && in sdhci_esdhc_imx_probe()
1640 imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { in sdhci_esdhc_imx_probe()
1641 host->mmc->caps2 |= MMC_CAP2_HS400_ES; in sdhci_esdhc_imx_probe()
1642 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_esdhc_imx_probe()
1646 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_probe()
1647 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_esdhc_imx_probe()
1648 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe()
1650 err = -ENOMEM; in sdhci_esdhc_imx_probe()
1654 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; in sdhci_esdhc_imx_probe()
1655 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe()
1657 err = cqhci_init(cq_host, host->mmc, false); in sdhci_esdhc_imx_probe()
1668 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1669 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1670 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1671 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1672 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1677 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1679 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1681 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1683 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1684 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_probe()
1696 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1697 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1698 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1699 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1703 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1704 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1705 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1707 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_remove()
1708 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_remove()
1723 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_suspend()
1724 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_suspend()
1729 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && in sdhci_esdhc_suspend()
1730 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { in sdhci_esdhc_suspend()
1731 mmc_retune_timer_stop(host->mmc); in sdhci_esdhc_suspend()
1732 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1735 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1736 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1746 ret = mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_esdhc_suspend()
1760 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1767 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_resume()
1768 ret = cqhci_resume(host->mmc); in sdhci_esdhc_resume()
1771 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_esdhc_resume()
1785 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_runtime_suspend()
1786 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_runtime_suspend()
1795 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1796 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1798 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1800 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1801 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1802 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1804 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_suspend()
1805 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_suspend()
1817 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1818 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_runtime_resume()
1820 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) in sdhci_esdhc_runtime_resume()
1821 clk_set_rate(imx_data->clk_per, pltfm_host->clock); in sdhci_esdhc_runtime_resume()
1823 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1827 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1831 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1835 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
1841 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_runtime_resume()
1842 err = cqhci_resume(host->mmc); in sdhci_esdhc_runtime_resume()
1847 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1849 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1851 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1853 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1854 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_resume()
1867 .name = "sdhci-esdhc-imx",