1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/pm_qos.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
28 #include <linux/pm_runtime.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
32 #include "cqhci.h"
33
34 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
35 #define ESDHC_CTRL_D3CD 0x08
36 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
37 /* VENDOR SPEC register */
38 #define ESDHC_VENDOR_SPEC 0xc0
39 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
40 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
41 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
42 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
43 #define ESDHC_DEBUG_SEL_REG 0xc3
44 #define ESDHC_DEBUG_SEL_MASK 0xf
45 #define ESDHC_DEBUG_SEL_CMD_STATE 1
46 #define ESDHC_DEBUG_SEL_DATA_STATE 2
47 #define ESDHC_DEBUG_SEL_TRANS_STATE 3
48 #define ESDHC_DEBUG_SEL_DMA_STATE 4
49 #define ESDHC_DEBUG_SEL_ADMA_STATE 5
50 #define ESDHC_DEBUG_SEL_FIFO_STATE 6
51 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
52 #define ESDHC_WTMK_LVL 0x44
53 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
54 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
55 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
56 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
57 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
58 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
59 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
60 #define ESDHC_MIX_CTRL 0x48
61 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
62 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
63 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
64 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
65 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
66 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
67 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
68 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
69 /* Bits 3 and 6 are not SDHCI standard definitions */
70 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
71 /* Tuning bits */
72 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
73
74 /* dll control register */
75 #define ESDHC_DLL_CTRL 0x60
76 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
77 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
78
79 /* tune control register */
80 #define ESDHC_TUNE_CTRL_STATUS 0x68
81 #define ESDHC_TUNE_CTRL_STEP 1
82 #define ESDHC_TUNE_CTRL_MIN 0
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
84
85 /* strobe dll register */
86 #define ESDHC_STROBE_DLL_CTRL 0x70
87 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
88 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
90 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
91 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
92
93 #define ESDHC_STROBE_DLL_STATUS 0x74
94 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
95 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
96
97 #define ESDHC_VEND_SPEC2 0xc8
98 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
99
100 #define ESDHC_TUNING_CTRL 0xcc
101 #define ESDHC_STD_TUNING_EN (1 << 24)
102 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
103 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
104 #define ESDHC_TUNING_START_TAP_MASK 0x7f
105 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
106 #define ESDHC_TUNING_STEP_DEFAULT 0x1
107 #define ESDHC_TUNING_STEP_MASK 0x00070000
108 #define ESDHC_TUNING_STEP_SHIFT 16
109
110 /* pinctrl state */
111 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
112 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
113
114 /*
115 * Our interpretation of the SDHCI_HOST_CONTROL register
116 */
117 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
118 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
119 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
120
121 /*
122 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
123 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
124 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
125 * Define this macro DMA error INT for fsl eSDHC
126 */
127 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
128
129 /* the address offset of CQHCI */
130 #define ESDHC_CQHCI_ADDR_OFFSET 0x100
131
132 /*
133 * The CMDTYPE of the CMD register (offset 0xE) should be set to
134 * "11" when the STOP CMD12 is issued on imx53 to abort one
135 * open ended multi-blk IO. Otherwise the TC INT wouldn't
136 * be generated.
137 * In exact block transfer, the controller doesn't complete the
138 * operations automatically as required at the end of the
139 * transfer and remains on hold if the abort command is not sent.
140 * As a result, the TC flag is not asserted and SW received timeout
141 * exception. Bit1 of Vendor Spec register is used to fix it.
142 */
143 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
144 /*
145 * The flag tells that the ESDHC controller is an USDHC block that is
146 * integrated on the i.MX6 series.
147 */
148 #define ESDHC_FLAG_USDHC BIT(3)
149 /* The IP supports manual tuning process */
150 #define ESDHC_FLAG_MAN_TUNING BIT(4)
151 /* The IP supports standard tuning process */
152 #define ESDHC_FLAG_STD_TUNING BIT(5)
153 /* The IP has SDHCI_CAPABILITIES_1 register */
154 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
155 /*
156 * The IP has erratum ERR004536
157 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
158 * when reading data from the card
159 * This flag is also set for i.MX25 and i.MX35 in order to get
160 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
161 */
162 #define ESDHC_FLAG_ERR004536 BIT(7)
163 /* The IP supports HS200 mode */
164 #define ESDHC_FLAG_HS200 BIT(8)
165 /* The IP supports HS400 mode */
166 #define ESDHC_FLAG_HS400 BIT(9)
167 /*
168 * The IP has errata ERR010450
169 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
170 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
171 */
172 #define ESDHC_FLAG_ERR010450 BIT(10)
173 /* The IP supports HS400ES mode */
174 #define ESDHC_FLAG_HS400_ES BIT(11)
175 /* The IP has Host Controller Interface for Command Queuing */
176 #define ESDHC_FLAG_CQHCI BIT(12)
177 /* need request pmqos during low power */
178 #define ESDHC_FLAG_PMQOS BIT(13)
179 /* The IP state got lost in low power mode */
180 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
181 /* The IP lost clock rate in PM_RUNTIME */
182 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
183 /*
184 * The IP do not support the ACMD23 feature completely when use ADMA mode.
185 * In ADMA mode, it only use the 16 bit block count of the register 0x4
186 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
187 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
188 * write operation in RPMB, because RPMB reliable write need to set the bit31
189 * of the CMD23's argument.
190 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
191 * do not has this limitation. so when these SoC use ADMA mode, it need to
192 * disable the ACMD23 feature.
193 */
194 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
195
196 struct esdhc_soc_data {
197 u32 flags;
198 };
199
200 static const struct esdhc_soc_data esdhc_imx25_data = {
201 .flags = ESDHC_FLAG_ERR004536,
202 };
203
204 static const struct esdhc_soc_data esdhc_imx35_data = {
205 .flags = ESDHC_FLAG_ERR004536,
206 };
207
208 static const struct esdhc_soc_data esdhc_imx51_data = {
209 .flags = 0,
210 };
211
212 static const struct esdhc_soc_data esdhc_imx53_data = {
213 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
214 };
215
216 static const struct esdhc_soc_data usdhc_imx6q_data = {
217 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
218 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
219 };
220
221 static const struct esdhc_soc_data usdhc_imx6sl_data = {
222 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
223 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
224 | ESDHC_FLAG_HS200
225 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
226 };
227
228 static const struct esdhc_soc_data usdhc_imx6sll_data = {
229 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
230 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
231 | ESDHC_FLAG_HS400
232 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
233 };
234
235 static const struct esdhc_soc_data usdhc_imx6sx_data = {
236 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
237 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
238 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
239 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
240 };
241
242 static const struct esdhc_soc_data usdhc_imx6ull_data = {
243 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
244 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
245 | ESDHC_FLAG_ERR010450
246 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
247 };
248
249 static const struct esdhc_soc_data usdhc_imx7d_data = {
250 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
251 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
252 | ESDHC_FLAG_HS400
253 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
254 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
255 };
256
257 static struct esdhc_soc_data usdhc_imx7ulp_data = {
258 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
259 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
260 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
261 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
262 };
263
264 static struct esdhc_soc_data usdhc_imx8qxp_data = {
265 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
266 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
267 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
268 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
269 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
270 };
271
272 static struct esdhc_soc_data usdhc_imx8mm_data = {
273 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
274 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
275 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
276 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
277 };
278
279 struct pltfm_imx_data {
280 u32 scratchpad;
281 struct pinctrl *pinctrl;
282 struct pinctrl_state *pins_100mhz;
283 struct pinctrl_state *pins_200mhz;
284 const struct esdhc_soc_data *socdata;
285 struct esdhc_platform_data boarddata;
286 struct clk *clk_ipg;
287 struct clk *clk_ahb;
288 struct clk *clk_per;
289 unsigned int actual_clock;
290 enum {
291 NO_CMD_PENDING, /* no multiblock command pending */
292 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
293 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
294 } multiblock_status;
295 u32 is_ddr;
296 struct pm_qos_request pm_qos_req;
297 };
298
299 static const struct of_device_id imx_esdhc_dt_ids[] = {
300 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
301 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
302 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
303 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
304 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
305 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
306 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
307 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
308 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
309 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
310 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
311 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
312 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
313 { /* sentinel */ }
314 };
315 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
316
is_imx25_esdhc(struct pltfm_imx_data * data)317 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
318 {
319 return data->socdata == &esdhc_imx25_data;
320 }
321
is_imx53_esdhc(struct pltfm_imx_data * data)322 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
323 {
324 return data->socdata == &esdhc_imx53_data;
325 }
326
is_imx6q_usdhc(struct pltfm_imx_data * data)327 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
328 {
329 return data->socdata == &usdhc_imx6q_data;
330 }
331
esdhc_is_usdhc(struct pltfm_imx_data * data)332 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
333 {
334 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
335 }
336
esdhc_clrset_le(struct sdhci_host * host,u32 mask,u32 val,int reg)337 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
338 {
339 void __iomem *base = host->ioaddr + (reg & ~0x3);
340 u32 shift = (reg & 0x3) * 8;
341
342 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
343 }
344
345 #define DRIVER_NAME "sdhci-esdhc-imx"
346 #define ESDHC_IMX_DUMP(f, x...) \
347 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
esdhc_dump_debug_regs(struct sdhci_host * host)348 static void esdhc_dump_debug_regs(struct sdhci_host *host)
349 {
350 int i;
351 char *debug_status[7] = {
352 "cmd debug status",
353 "data debug status",
354 "trans debug status",
355 "dma debug status",
356 "adma debug status",
357 "fifo debug status",
358 "async fifo debug status"
359 };
360
361 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
362 for (i = 0; i < 7; i++) {
363 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
364 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
365 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
366 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
367 }
368
369 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
370
371 }
372
esdhc_wait_for_card_clock_gate_off(struct sdhci_host * host)373 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
374 {
375 u32 present_state;
376 int ret;
377
378 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
379 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
380 if (ret == -ETIMEDOUT)
381 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
382 }
383
esdhc_readl_le(struct sdhci_host * host,int reg)384 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
385 {
386 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
387 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
388 u32 val = readl(host->ioaddr + reg);
389
390 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
391 u32 fsl_prss = val;
392 /* save the least 20 bits */
393 val = fsl_prss & 0x000FFFFF;
394 /* move dat[0-3] bits */
395 val |= (fsl_prss & 0x0F000000) >> 4;
396 /* move cmd line bit */
397 val |= (fsl_prss & 0x00800000) << 1;
398 }
399
400 if (unlikely(reg == SDHCI_CAPABILITIES)) {
401 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
402 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
403 val &= 0xffff0000;
404
405 /* In FSL esdhc IC module, only bit20 is used to indicate the
406 * ADMA2 capability of esdhc, but this bit is messed up on
407 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
408 * don't actually support ADMA2). So set the BROKEN_ADMA
409 * quirk on MX25/35 platforms.
410 */
411
412 if (val & SDHCI_CAN_DO_ADMA1) {
413 val &= ~SDHCI_CAN_DO_ADMA1;
414 val |= SDHCI_CAN_DO_ADMA2;
415 }
416 }
417
418 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
419 if (esdhc_is_usdhc(imx_data)) {
420 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
421 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
422 else
423 /* imx6q/dl does not have cap_1 register, fake one */
424 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
425 | SDHCI_SUPPORT_SDR50
426 | SDHCI_USE_SDR50_TUNING
427 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
428 SDHCI_TUNING_MODE_3);
429
430 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
431 val |= SDHCI_SUPPORT_HS400;
432
433 /*
434 * Do not advertise faster UHS modes if there are no
435 * pinctrl states for 100MHz/200MHz.
436 */
437 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
438 IS_ERR_OR_NULL(imx_data->pins_200mhz))
439 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
440 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
441 }
442 }
443
444 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
445 val = 0;
446 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
447 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
448 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
449 }
450
451 if (unlikely(reg == SDHCI_INT_STATUS)) {
452 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
453 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
454 val |= SDHCI_INT_ADMA_ERROR;
455 }
456
457 /*
458 * mask off the interrupt we get in response to the manually
459 * sent CMD12
460 */
461 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
462 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
463 val &= ~SDHCI_INT_RESPONSE;
464 writel(SDHCI_INT_RESPONSE, host->ioaddr +
465 SDHCI_INT_STATUS);
466 imx_data->multiblock_status = NO_CMD_PENDING;
467 }
468 }
469
470 return val;
471 }
472
esdhc_writel_le(struct sdhci_host * host,u32 val,int reg)473 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
474 {
475 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
476 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
477 u32 data;
478
479 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
480 reg == SDHCI_INT_STATUS)) {
481 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
482 /*
483 * Clear and then set D3CD bit to avoid missing the
484 * card interrupt. This is an eSDHC controller problem
485 * so we need to apply the following workaround: clear
486 * and set D3CD bit will make eSDHC re-sample the card
487 * interrupt. In case a card interrupt was lost,
488 * re-sample it by the following steps.
489 */
490 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
491 data &= ~ESDHC_CTRL_D3CD;
492 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
493 data |= ESDHC_CTRL_D3CD;
494 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
495 }
496
497 if (val & SDHCI_INT_ADMA_ERROR) {
498 val &= ~SDHCI_INT_ADMA_ERROR;
499 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
500 }
501 }
502
503 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
504 && (reg == SDHCI_INT_STATUS)
505 && (val & SDHCI_INT_DATA_END))) {
506 u32 v;
507 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
508 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
509 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
510
511 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
512 {
513 /* send a manual CMD12 with RESPTYP=none */
514 data = MMC_STOP_TRANSMISSION << 24 |
515 SDHCI_CMD_ABORTCMD << 16;
516 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
517 imx_data->multiblock_status = WAIT_FOR_INT;
518 }
519 }
520
521 writel(val, host->ioaddr + reg);
522 }
523
esdhc_readw_le(struct sdhci_host * host,int reg)524 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
525 {
526 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
527 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
528 u16 ret = 0;
529 u32 val;
530
531 if (unlikely(reg == SDHCI_HOST_VERSION)) {
532 reg ^= 2;
533 if (esdhc_is_usdhc(imx_data)) {
534 /*
535 * The usdhc register returns a wrong host version.
536 * Correct it here.
537 */
538 return SDHCI_SPEC_300;
539 }
540 }
541
542 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
543 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
544 if (val & ESDHC_VENDOR_SPEC_VSELECT)
545 ret |= SDHCI_CTRL_VDD_180;
546
547 if (esdhc_is_usdhc(imx_data)) {
548 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
549 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
550 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
551 /* the std tuning bits is in ACMD12_ERR for imx6sl */
552 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
553 }
554
555 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
556 ret |= SDHCI_CTRL_EXEC_TUNING;
557 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
558 ret |= SDHCI_CTRL_TUNED_CLK;
559
560 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
561
562 return ret;
563 }
564
565 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
566 if (esdhc_is_usdhc(imx_data)) {
567 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
568 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
569 /* Swap AC23 bit */
570 if (m & ESDHC_MIX_CTRL_AC23EN) {
571 ret &= ~ESDHC_MIX_CTRL_AC23EN;
572 ret |= SDHCI_TRNS_AUTO_CMD23;
573 }
574 } else {
575 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
576 }
577
578 return ret;
579 }
580
581 return readw(host->ioaddr + reg);
582 }
583
esdhc_writew_le(struct sdhci_host * host,u16 val,int reg)584 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
585 {
586 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
587 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
588 u32 new_val = 0;
589
590 switch (reg) {
591 case SDHCI_CLOCK_CONTROL:
592 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
593 if (val & SDHCI_CLOCK_CARD_EN)
594 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
595 else
596 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
597 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
598 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
599 esdhc_wait_for_card_clock_gate_off(host);
600 return;
601 case SDHCI_HOST_CONTROL2:
602 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
603 if (val & SDHCI_CTRL_VDD_180)
604 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
605 else
606 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
607 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
608 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
609 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
610 if (val & SDHCI_CTRL_TUNED_CLK) {
611 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
612 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
613 } else {
614 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
615 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
616 }
617 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
618 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
619 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
620 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
621 if (val & SDHCI_CTRL_TUNED_CLK) {
622 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
623 } else {
624 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
625 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
626 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
627 }
628
629 if (val & SDHCI_CTRL_EXEC_TUNING) {
630 v |= ESDHC_MIX_CTRL_EXE_TUNE;
631 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
632 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
633 } else {
634 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
635 }
636
637 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
638 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
639 }
640 return;
641 case SDHCI_TRANSFER_MODE:
642 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
643 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
644 && (host->cmd->data->blocks > 1)
645 && (host->cmd->data->flags & MMC_DATA_READ)) {
646 u32 v;
647 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
648 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
649 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
650 }
651
652 if (esdhc_is_usdhc(imx_data)) {
653 u32 wml;
654 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
655 /* Swap AC23 bit */
656 if (val & SDHCI_TRNS_AUTO_CMD23) {
657 val &= ~SDHCI_TRNS_AUTO_CMD23;
658 val |= ESDHC_MIX_CTRL_AC23EN;
659 }
660 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
661 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
662
663 /* Set watermark levels for PIO access to maximum value
664 * (128 words) to accommodate full 512 bytes buffer.
665 * For DMA access restore the levels to default value.
666 */
667 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
668 if (val & SDHCI_TRNS_DMA) {
669 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
670 } else {
671 u8 ctrl;
672 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
673
674 /*
675 * Since already disable DMA mode, so also need
676 * to clear the DMASEL. Otherwise, for standard
677 * tuning, when send tuning command, usdhc will
678 * still prefetch the ADMA script from wrong
679 * DMA address, then we will see IOMMU report
680 * some error which show lack of TLB mapping.
681 */
682 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
683 ctrl &= ~SDHCI_CTRL_DMA_MASK;
684 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
685 }
686 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
687 ESDHC_WTMK_LVL_WR_WML_MASK);
688 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
689 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
690 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
691 } else {
692 /*
693 * Postpone this write, we must do it together with a
694 * command write that is down below.
695 */
696 imx_data->scratchpad = val;
697 }
698 return;
699 case SDHCI_COMMAND:
700 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
701 val |= SDHCI_CMD_ABORTCMD;
702
703 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
704 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
705 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
706
707 if (esdhc_is_usdhc(imx_data))
708 writel(val << 16,
709 host->ioaddr + SDHCI_TRANSFER_MODE);
710 else
711 writel(val << 16 | imx_data->scratchpad,
712 host->ioaddr + SDHCI_TRANSFER_MODE);
713 return;
714 case SDHCI_BLOCK_SIZE:
715 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
716 break;
717 }
718 esdhc_clrset_le(host, 0xffff, val, reg);
719 }
720
esdhc_readb_le(struct sdhci_host * host,int reg)721 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
722 {
723 u8 ret;
724 u32 val;
725
726 switch (reg) {
727 case SDHCI_HOST_CONTROL:
728 val = readl(host->ioaddr + reg);
729
730 ret = val & SDHCI_CTRL_LED;
731 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
732 ret |= (val & ESDHC_CTRL_4BITBUS);
733 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
734 return ret;
735 }
736
737 return readb(host->ioaddr + reg);
738 }
739
esdhc_writeb_le(struct sdhci_host * host,u8 val,int reg)740 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
741 {
742 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
743 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
744 u32 new_val = 0;
745 u32 mask;
746
747 switch (reg) {
748 case SDHCI_POWER_CONTROL:
749 /*
750 * FSL put some DMA bits here
751 * If your board has a regulator, code should be here
752 */
753 return;
754 case SDHCI_HOST_CONTROL:
755 /* FSL messed up here, so we need to manually compose it. */
756 new_val = val & SDHCI_CTRL_LED;
757 /* ensure the endianness */
758 new_val |= ESDHC_HOST_CONTROL_LE;
759 /* bits 8&9 are reserved on mx25 */
760 if (!is_imx25_esdhc(imx_data)) {
761 /* DMA mode bits are shifted */
762 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
763 }
764
765 /*
766 * Do not touch buswidth bits here. This is done in
767 * esdhc_pltfm_bus_width.
768 * Do not touch the D3CD bit either which is used for the
769 * SDIO interrupt erratum workaround.
770 */
771 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
772
773 esdhc_clrset_le(host, mask, new_val, reg);
774 return;
775 case SDHCI_SOFTWARE_RESET:
776 if (val & SDHCI_RESET_DATA)
777 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
778 break;
779 }
780 esdhc_clrset_le(host, 0xff, val, reg);
781
782 if (reg == SDHCI_SOFTWARE_RESET) {
783 if (val & SDHCI_RESET_ALL) {
784 /*
785 * The esdhc has a design violation to SDHC spec which
786 * tells that software reset should not affect card
787 * detection circuit. But esdhc clears its SYSCTL
788 * register bits [0..2] during the software reset. This
789 * will stop those clocks that card detection circuit
790 * relies on. To work around it, we turn the clocks on
791 * back to keep card detection circuit functional.
792 */
793 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
794 /*
795 * The reset on usdhc fails to clear MIX_CTRL register.
796 * Do it manually here.
797 */
798 if (esdhc_is_usdhc(imx_data)) {
799 /*
800 * the tuning bits should be kept during reset
801 */
802 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
803 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
804 host->ioaddr + ESDHC_MIX_CTRL);
805 imx_data->is_ddr = 0;
806 }
807 } else if (val & SDHCI_RESET_DATA) {
808 /*
809 * The eSDHC DAT line software reset clears at least the
810 * data transfer width on i.MX25, so make sure that the
811 * Host Control register is unaffected.
812 */
813 esdhc_clrset_le(host, 0xff, new_val,
814 SDHCI_HOST_CONTROL);
815 }
816 }
817 }
818
esdhc_pltfm_get_max_clock(struct sdhci_host * host)819 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
820 {
821 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
822
823 return pltfm_host->clock;
824 }
825
esdhc_pltfm_get_min_clock(struct sdhci_host * host)826 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
827 {
828 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
829
830 return pltfm_host->clock / 256 / 16;
831 }
832
esdhc_pltfm_set_clock(struct sdhci_host * host,unsigned int clock)833 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
834 unsigned int clock)
835 {
836 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
837 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
838 unsigned int host_clock = pltfm_host->clock;
839 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
840 int pre_div = 1;
841 int div = 1;
842 int ret;
843 u32 temp, val;
844
845 if (esdhc_is_usdhc(imx_data)) {
846 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
847 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
848 host->ioaddr + ESDHC_VENDOR_SPEC);
849 esdhc_wait_for_card_clock_gate_off(host);
850 }
851
852 if (clock == 0) {
853 host->mmc->actual_clock = 0;
854 return;
855 }
856
857 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
858 if (is_imx53_esdhc(imx_data)) {
859 /*
860 * According to the i.MX53 reference manual, if DLLCTRL[10] can
861 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
862 */
863 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
864 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
865 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
866 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
867 if (temp & BIT(10))
868 pre_div = 2;
869 }
870
871 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
872 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
873 | ESDHC_CLOCK_MASK);
874 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
875
876 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
877 unsigned int max_clock;
878
879 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
880
881 clock = min(clock, max_clock);
882 }
883
884 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
885 pre_div < 256)
886 pre_div *= 2;
887
888 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
889 div++;
890
891 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
892 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
893 clock, host->mmc->actual_clock);
894
895 pre_div >>= 1;
896 div--;
897
898 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
899 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
900 | (div << ESDHC_DIVIDER_SHIFT)
901 | (pre_div << ESDHC_PREDIV_SHIFT));
902 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
903
904 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
905 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
906 (temp & ESDHC_CLOCK_STABLE), 2, 100);
907 if (ret == -ETIMEDOUT)
908 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
909
910 if (esdhc_is_usdhc(imx_data)) {
911 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
912 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
913 host->ioaddr + ESDHC_VENDOR_SPEC);
914 }
915
916 }
917
esdhc_pltfm_get_ro(struct sdhci_host * host)918 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
919 {
920 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
921 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
922 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
923
924 switch (boarddata->wp_type) {
925 case ESDHC_WP_GPIO:
926 return mmc_gpio_get_ro(host->mmc);
927 case ESDHC_WP_CONTROLLER:
928 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
929 SDHCI_WRITE_PROTECT);
930 case ESDHC_WP_NONE:
931 break;
932 }
933
934 return -ENOSYS;
935 }
936
esdhc_pltfm_set_bus_width(struct sdhci_host * host,int width)937 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
938 {
939 u32 ctrl;
940
941 switch (width) {
942 case MMC_BUS_WIDTH_8:
943 ctrl = ESDHC_CTRL_8BITBUS;
944 break;
945 case MMC_BUS_WIDTH_4:
946 ctrl = ESDHC_CTRL_4BITBUS;
947 break;
948 default:
949 ctrl = 0;
950 break;
951 }
952
953 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
954 SDHCI_HOST_CONTROL);
955 }
956
usdhc_execute_tuning(struct mmc_host * mmc,u32 opcode)957 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
958 {
959 struct sdhci_host *host = mmc_priv(mmc);
960
961 /*
962 * i.MX uSDHC internally already uses a fixed optimized timing for
963 * DDR50, normally does not require tuning for DDR50 mode.
964 */
965 if (host->timing == MMC_TIMING_UHS_DDR50)
966 return 0;
967
968 return sdhci_execute_tuning(mmc, opcode);
969 }
970
esdhc_prepare_tuning(struct sdhci_host * host,u32 val)971 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
972 {
973 u32 reg;
974 u8 sw_rst;
975 int ret;
976
977 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
978 mdelay(1);
979
980 /* IC suggest to reset USDHC before every tuning command */
981 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
982 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
983 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
984 if (ret == -ETIMEDOUT)
985 dev_warn(mmc_dev(host->mmc),
986 "warning! RESET_ALL never complete before sending tuning command\n");
987
988 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
989 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
990 ESDHC_MIX_CTRL_FBCLK_SEL;
991 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
992 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
993 dev_dbg(mmc_dev(host->mmc),
994 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
995 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
996 }
997
esdhc_post_tuning(struct sdhci_host * host)998 static void esdhc_post_tuning(struct sdhci_host *host)
999 {
1000 u32 reg;
1001
1002 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1003 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1004 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1005 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1006 }
1007
esdhc_executing_tuning(struct sdhci_host * host,u32 opcode)1008 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1009 {
1010 int min, max, avg, ret;
1011
1012 /* find the mininum delay first which can pass tuning */
1013 min = ESDHC_TUNE_CTRL_MIN;
1014 while (min < ESDHC_TUNE_CTRL_MAX) {
1015 esdhc_prepare_tuning(host, min);
1016 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1017 break;
1018 min += ESDHC_TUNE_CTRL_STEP;
1019 }
1020
1021 /* find the maxinum delay which can not pass tuning */
1022 max = min + ESDHC_TUNE_CTRL_STEP;
1023 while (max < ESDHC_TUNE_CTRL_MAX) {
1024 esdhc_prepare_tuning(host, max);
1025 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1026 max -= ESDHC_TUNE_CTRL_STEP;
1027 break;
1028 }
1029 max += ESDHC_TUNE_CTRL_STEP;
1030 }
1031
1032 /* use average delay to get the best timing */
1033 avg = (min + max) / 2;
1034 esdhc_prepare_tuning(host, avg);
1035 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1036 esdhc_post_tuning(host);
1037
1038 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1039 ret ? "failed" : "passed", avg, ret);
1040
1041 return ret;
1042 }
1043
esdhc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)1044 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1045 {
1046 struct sdhci_host *host = mmc_priv(mmc);
1047 u32 m;
1048
1049 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1050 if (ios->enhanced_strobe)
1051 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1052 else
1053 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1054 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1055 }
1056
esdhc_change_pinstate(struct sdhci_host * host,unsigned int uhs)1057 static int esdhc_change_pinstate(struct sdhci_host *host,
1058 unsigned int uhs)
1059 {
1060 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1061 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1062 struct pinctrl_state *pinctrl;
1063
1064 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1065
1066 if (IS_ERR(imx_data->pinctrl) ||
1067 IS_ERR(imx_data->pins_100mhz) ||
1068 IS_ERR(imx_data->pins_200mhz))
1069 return -EINVAL;
1070
1071 switch (uhs) {
1072 case MMC_TIMING_UHS_SDR50:
1073 case MMC_TIMING_UHS_DDR50:
1074 pinctrl = imx_data->pins_100mhz;
1075 break;
1076 case MMC_TIMING_UHS_SDR104:
1077 case MMC_TIMING_MMC_HS200:
1078 case MMC_TIMING_MMC_HS400:
1079 pinctrl = imx_data->pins_200mhz;
1080 break;
1081 default:
1082 /* back to default state for other legacy timing */
1083 return pinctrl_select_default_state(mmc_dev(host->mmc));
1084 }
1085
1086 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1087 }
1088
1089 /*
1090 * For HS400 eMMC, there is a data_strobe line. This signal is generated
1091 * by the device and used for data output and CRC status response output
1092 * in HS400 mode. The frequency of this signal follows the frequency of
1093 * CLK generated by host. The host receives the data which is aligned to the
1094 * edge of data_strobe line. Due to the time delay between CLK line and
1095 * data_strobe line, if the delay time is larger than one clock cycle,
1096 * then CLK and data_strobe line will be misaligned, read error shows up.
1097 */
esdhc_set_strobe_dll(struct sdhci_host * host)1098 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1099 {
1100 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1101 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1102 u32 strobe_delay;
1103 u32 v;
1104 int ret;
1105
1106 /* disable clock before enabling strobe dll */
1107 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1108 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1109 host->ioaddr + ESDHC_VENDOR_SPEC);
1110 esdhc_wait_for_card_clock_gate_off(host);
1111
1112 /* force a reset on strobe dll */
1113 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1114 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1115 /* clear the reset bit on strobe dll before any setting */
1116 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1117
1118 /*
1119 * enable strobe dll ctrl and adjust the delay target
1120 * for the uSDHC loopback read clock
1121 */
1122 if (imx_data->boarddata.strobe_dll_delay_target)
1123 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1124 else
1125 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1126 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1127 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1128 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1129 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1130
1131 /* wait max 50us to get the REF/SLV lock */
1132 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1133 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1134 if (ret == -ETIMEDOUT)
1135 dev_warn(mmc_dev(host->mmc),
1136 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1137 }
1138
esdhc_reset_tuning(struct sdhci_host * host)1139 static void esdhc_reset_tuning(struct sdhci_host *host)
1140 {
1141 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1142 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1143 u32 ctrl;
1144 int ret;
1145
1146 /* Reset the tuning circuit */
1147 if (esdhc_is_usdhc(imx_data)) {
1148 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1149 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1150 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1151 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1152 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1153 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1154 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1155 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1156 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1157 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1158 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1159 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1160 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1161 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1162 if (ret == -ETIMEDOUT)
1163 dev_warn(mmc_dev(host->mmc),
1164 "Warning! clear execute tuning bit failed\n");
1165 /*
1166 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1167 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1168 * will finally make sure the normal data transfer logic correct.
1169 */
1170 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1171 ctrl |= SDHCI_INT_DATA_AVAIL;
1172 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1173 }
1174 }
1175 }
1176
esdhc_set_uhs_signaling(struct sdhci_host * host,unsigned timing)1177 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1178 {
1179 u32 m;
1180 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1181 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1182 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1183
1184 /* disable ddr mode and disable HS400 mode */
1185 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1186 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1187 imx_data->is_ddr = 0;
1188
1189 switch (timing) {
1190 case MMC_TIMING_UHS_SDR12:
1191 case MMC_TIMING_UHS_SDR25:
1192 case MMC_TIMING_UHS_SDR50:
1193 case MMC_TIMING_UHS_SDR104:
1194 case MMC_TIMING_MMC_HS:
1195 case MMC_TIMING_MMC_HS200:
1196 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1197 break;
1198 case MMC_TIMING_UHS_DDR50:
1199 case MMC_TIMING_MMC_DDR52:
1200 m |= ESDHC_MIX_CTRL_DDREN;
1201 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1202 imx_data->is_ddr = 1;
1203 if (boarddata->delay_line) {
1204 u32 v;
1205 v = boarddata->delay_line <<
1206 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1207 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1208 if (is_imx53_esdhc(imx_data))
1209 v <<= 1;
1210 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1211 }
1212 break;
1213 case MMC_TIMING_MMC_HS400:
1214 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1215 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1216 imx_data->is_ddr = 1;
1217 /* update clock after enable DDR for strobe DLL lock */
1218 host->ops->set_clock(host, host->clock);
1219 esdhc_set_strobe_dll(host);
1220 break;
1221 case MMC_TIMING_LEGACY:
1222 default:
1223 esdhc_reset_tuning(host);
1224 break;
1225 }
1226
1227 esdhc_change_pinstate(host, timing);
1228 }
1229
esdhc_reset(struct sdhci_host * host,u8 mask)1230 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1231 {
1232 sdhci_and_cqhci_reset(host, mask);
1233
1234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1236 }
1237
esdhc_get_max_timeout_count(struct sdhci_host * host)1238 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1239 {
1240 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1241 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1242
1243 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1244 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1245 }
1246
esdhc_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1247 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1248 {
1249 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1250 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1251
1252 /* use maximum timeout counter */
1253 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1254 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1255 SDHCI_TIMEOUT_CONTROL);
1256 }
1257
esdhc_cqhci_irq(struct sdhci_host * host,u32 intmask)1258 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1259 {
1260 int cmd_error = 0;
1261 int data_error = 0;
1262
1263 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1264 return intmask;
1265
1266 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1267
1268 return 0;
1269 }
1270
1271 static struct sdhci_ops sdhci_esdhc_ops = {
1272 .read_l = esdhc_readl_le,
1273 .read_w = esdhc_readw_le,
1274 .read_b = esdhc_readb_le,
1275 .write_l = esdhc_writel_le,
1276 .write_w = esdhc_writew_le,
1277 .write_b = esdhc_writeb_le,
1278 .set_clock = esdhc_pltfm_set_clock,
1279 .get_max_clock = esdhc_pltfm_get_max_clock,
1280 .get_min_clock = esdhc_pltfm_get_min_clock,
1281 .get_max_timeout_count = esdhc_get_max_timeout_count,
1282 .get_ro = esdhc_pltfm_get_ro,
1283 .set_timeout = esdhc_set_timeout,
1284 .set_bus_width = esdhc_pltfm_set_bus_width,
1285 .set_uhs_signaling = esdhc_set_uhs_signaling,
1286 .reset = esdhc_reset,
1287 .irq = esdhc_cqhci_irq,
1288 .dump_vendor_regs = esdhc_dump_debug_regs,
1289 };
1290
1291 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1292 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1293 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1294 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1295 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1296 .ops = &sdhci_esdhc_ops,
1297 };
1298
sdhci_esdhc_imx_hwinit(struct sdhci_host * host)1299 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1300 {
1301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1302 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1303 struct cqhci_host *cq_host = host->mmc->cqe_private;
1304 u32 tmp;
1305
1306 if (esdhc_is_usdhc(imx_data)) {
1307 /*
1308 * The imx6q ROM code will change the default watermark
1309 * level setting to something insane. Change it back here.
1310 */
1311 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1312
1313 /*
1314 * ROM code will change the bit burst_length_enable setting
1315 * to zero if this usdhc is chosen to boot system. Change
1316 * it back here, otherwise it will impact the performance a
1317 * lot. This bit is used to enable/disable the burst length
1318 * for the external AHB2AXI bridge. It's useful especially
1319 * for INCR transfer because without burst length indicator,
1320 * the AHB2AXI bridge does not know the burst length in
1321 * advance. And without burst length indicator, AHB INCR
1322 * transfer can only be converted to singles on the AXI side.
1323 */
1324 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1325 | ESDHC_BURST_LEN_EN_INCR,
1326 host->ioaddr + SDHCI_HOST_CONTROL);
1327
1328 /*
1329 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1330 * TO1.1, it's harmless for MX6SL
1331 */
1332 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1333 host->ioaddr + 0x6c);
1334
1335 /* disable DLL_CTRL delay line settings */
1336 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1337
1338 /*
1339 * For the case of command with busy, if set the bit
1340 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1341 * transfer complete interrupt when busy is deasserted.
1342 * When CQHCI use DCMD to send a CMD need R1b respons,
1343 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1344 * otherwise DCMD will always meet timeout waiting for
1345 * hardware interrupt issue.
1346 */
1347 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1348 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1349 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1350 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1351
1352 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1353 }
1354
1355 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1356 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1357 tmp |= ESDHC_STD_TUNING_EN;
1358
1359 /*
1360 * ROM code or bootloader may config the start tap
1361 * and step, unmask them first.
1362 */
1363 tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1364 if (imx_data->boarddata.tuning_start_tap)
1365 tmp |= imx_data->boarddata.tuning_start_tap;
1366 else
1367 tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1368
1369 if (imx_data->boarddata.tuning_step) {
1370 tmp |= imx_data->boarddata.tuning_step
1371 << ESDHC_TUNING_STEP_SHIFT;
1372 } else {
1373 tmp |= ESDHC_TUNING_STEP_DEFAULT
1374 << ESDHC_TUNING_STEP_SHIFT;
1375 }
1376
1377 /* Disable the CMD CRC check for tuning, if not, need to
1378 * add some delay after every tuning command, because
1379 * hardware standard tuning logic will directly go to next
1380 * step once it detect the CMD CRC error, will not wait for
1381 * the card side to finally send out the tuning data, trigger
1382 * the buffer read ready interrupt immediately. If usdhc send
1383 * the next tuning command some eMMC card will stuck, can't
1384 * response, block the tuning procedure or the first command
1385 * after the whole tuning procedure always can't get any response.
1386 */
1387 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1388 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1389 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1390 /*
1391 * ESDHC_STD_TUNING_EN may be configed in bootloader
1392 * or ROM code, so clear this bit here to make sure
1393 * the manual tuning can work.
1394 */
1395 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1396 tmp &= ~ESDHC_STD_TUNING_EN;
1397 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1398 }
1399
1400 /*
1401 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1402 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1403 * the 1st linux configure power/clock for the 2nd Linux.
1404 *
1405 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1406 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1407 * After we clear the pending interrupt and halt CQCTL, issue gone.
1408 */
1409 if (cq_host) {
1410 tmp = cqhci_readl(cq_host, CQHCI_IS);
1411 cqhci_writel(cq_host, tmp, CQHCI_IS);
1412 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1413 }
1414 }
1415 }
1416
esdhc_cqe_enable(struct mmc_host * mmc)1417 static void esdhc_cqe_enable(struct mmc_host *mmc)
1418 {
1419 struct sdhci_host *host = mmc_priv(mmc);
1420 struct cqhci_host *cq_host = mmc->cqe_private;
1421 u32 reg;
1422 u16 mode;
1423 int count = 10;
1424
1425 /*
1426 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1427 * the case after tuning, so ensure the buffer is drained.
1428 */
1429 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1430 while (reg & SDHCI_DATA_AVAILABLE) {
1431 sdhci_readl(host, SDHCI_BUFFER);
1432 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1433 if (count-- == 0) {
1434 dev_warn(mmc_dev(host->mmc),
1435 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1436 break;
1437 }
1438 mdelay(1);
1439 }
1440
1441 /*
1442 * Runtime resume will reset the entire host controller, which
1443 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1444 * Here set DMAEN and BCEN when enable CMDQ.
1445 */
1446 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1447 if (host->flags & SDHCI_REQ_USE_DMA)
1448 mode |= SDHCI_TRNS_DMA;
1449 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1450 mode |= SDHCI_TRNS_BLK_CNT_EN;
1451 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1452
1453 /*
1454 * Though Runtime resume reset the entire host controller,
1455 * but do not impact the CQHCI side, need to clear the
1456 * HALT bit, avoid CQHCI stuck in the first request when
1457 * system resume back.
1458 */
1459 cqhci_writel(cq_host, 0, CQHCI_CTL);
1460 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1461 dev_err(mmc_dev(host->mmc),
1462 "failed to exit halt state when enable CQE\n");
1463
1464
1465 sdhci_cqe_enable(mmc);
1466 }
1467
esdhc_sdhci_dumpregs(struct mmc_host * mmc)1468 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1469 {
1470 sdhci_dumpregs(mmc_priv(mmc));
1471 }
1472
1473 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1474 .enable = esdhc_cqe_enable,
1475 .disable = sdhci_cqe_disable,
1476 .dumpregs = esdhc_sdhci_dumpregs,
1477 };
1478
1479 #ifdef CONFIG_OF
1480 static int
sdhci_esdhc_imx_probe_dt(struct platform_device * pdev,struct sdhci_host * host,struct pltfm_imx_data * imx_data)1481 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1482 struct sdhci_host *host,
1483 struct pltfm_imx_data *imx_data)
1484 {
1485 struct device_node *np = pdev->dev.of_node;
1486 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1487 int ret;
1488
1489 if (of_get_property(np, "fsl,wp-controller", NULL))
1490 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1491
1492 /*
1493 * If we have this property, then activate WP check.
1494 * Retrieveing and requesting the actual WP GPIO will happen
1495 * in the call to mmc_of_parse().
1496 */
1497 if (of_property_read_bool(np, "wp-gpios"))
1498 boarddata->wp_type = ESDHC_WP_GPIO;
1499
1500 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1501 of_property_read_u32(np, "fsl,tuning-start-tap",
1502 &boarddata->tuning_start_tap);
1503
1504 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1505 &boarddata->strobe_dll_delay_target);
1506 if (of_find_property(np, "no-1-8-v", NULL))
1507 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1508
1509 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1510 boarddata->delay_line = 0;
1511
1512 mmc_of_parse_voltage(np, &host->ocr_mask);
1513
1514 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1515 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1516 ESDHC_PINCTRL_STATE_100MHZ);
1517 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1518 ESDHC_PINCTRL_STATE_200MHZ);
1519 }
1520
1521 /* call to generic mmc_of_parse to support additional capabilities */
1522 ret = mmc_of_parse(host->mmc);
1523 if (ret)
1524 return ret;
1525
1526 if (mmc_gpio_get_cd(host->mmc) >= 0)
1527 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1528
1529 return 0;
1530 }
1531 #else
1532 static inline int
sdhci_esdhc_imx_probe_dt(struct platform_device * pdev,struct sdhci_host * host,struct pltfm_imx_data * imx_data)1533 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1534 struct sdhci_host *host,
1535 struct pltfm_imx_data *imx_data)
1536 {
1537 return -ENODEV;
1538 }
1539 #endif
1540
sdhci_esdhc_imx_probe(struct platform_device * pdev)1541 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1542 {
1543 const struct of_device_id *of_id =
1544 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1545 struct sdhci_pltfm_host *pltfm_host;
1546 struct sdhci_host *host;
1547 struct cqhci_host *cq_host;
1548 int err;
1549 struct pltfm_imx_data *imx_data;
1550
1551 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1552 sizeof(*imx_data));
1553 if (IS_ERR(host))
1554 return PTR_ERR(host);
1555
1556 pltfm_host = sdhci_priv(host);
1557
1558 imx_data = sdhci_pltfm_priv(pltfm_host);
1559
1560 imx_data->socdata = of_id->data;
1561
1562 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1563 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1564
1565 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1566 if (IS_ERR(imx_data->clk_ipg)) {
1567 err = PTR_ERR(imx_data->clk_ipg);
1568 goto free_sdhci;
1569 }
1570
1571 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1572 if (IS_ERR(imx_data->clk_ahb)) {
1573 err = PTR_ERR(imx_data->clk_ahb);
1574 goto free_sdhci;
1575 }
1576
1577 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1578 if (IS_ERR(imx_data->clk_per)) {
1579 err = PTR_ERR(imx_data->clk_per);
1580 goto free_sdhci;
1581 }
1582
1583 pltfm_host->clk = imx_data->clk_per;
1584 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1585 err = clk_prepare_enable(imx_data->clk_per);
1586 if (err)
1587 goto free_sdhci;
1588 err = clk_prepare_enable(imx_data->clk_ipg);
1589 if (err)
1590 goto disable_per_clk;
1591 err = clk_prepare_enable(imx_data->clk_ahb);
1592 if (err)
1593 goto disable_ipg_clk;
1594
1595 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1596 if (IS_ERR(imx_data->pinctrl))
1597 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1598
1599 if (esdhc_is_usdhc(imx_data)) {
1600 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1601 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1602
1603 /* GPIO CD can be set as a wakeup source */
1604 host->mmc->caps |= MMC_CAP_CD_WAKE;
1605
1606 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1607 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1608
1609 /* clear tuning bits in case ROM has set it already */
1610 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1611 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1612 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1613
1614 /*
1615 * Link usdhc specific mmc_host_ops execute_tuning function,
1616 * to replace the standard one in sdhci_ops.
1617 */
1618 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1619 }
1620
1621 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1622 if (err)
1623 goto disable_ahb_clk;
1624
1625 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1626 sdhci_esdhc_ops.platform_execute_tuning =
1627 esdhc_executing_tuning;
1628
1629 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1630 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1631
1632 if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1633 imx_data->socdata->flags & ESDHC_FLAG_HS400)
1634 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1635
1636 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1637 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1638
1639 if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1640 imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1641 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1642 host->mmc_host_ops.hs400_enhanced_strobe =
1643 esdhc_hs400_enhanced_strobe;
1644 }
1645
1646 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1647 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1648 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1649 if (!cq_host) {
1650 err = -ENOMEM;
1651 goto disable_ahb_clk;
1652 }
1653
1654 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1655 cq_host->ops = &esdhc_cqhci_ops;
1656
1657 err = cqhci_init(cq_host, host->mmc, false);
1658 if (err)
1659 goto disable_ahb_clk;
1660 }
1661
1662 sdhci_esdhc_imx_hwinit(host);
1663
1664 err = sdhci_add_host(host);
1665 if (err)
1666 goto disable_ahb_clk;
1667
1668 pm_runtime_set_active(&pdev->dev);
1669 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1670 pm_runtime_use_autosuspend(&pdev->dev);
1671 pm_suspend_ignore_children(&pdev->dev, 1);
1672 pm_runtime_enable(&pdev->dev);
1673
1674 return 0;
1675
1676 disable_ahb_clk:
1677 clk_disable_unprepare(imx_data->clk_ahb);
1678 disable_ipg_clk:
1679 clk_disable_unprepare(imx_data->clk_ipg);
1680 disable_per_clk:
1681 clk_disable_unprepare(imx_data->clk_per);
1682 free_sdhci:
1683 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1684 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1685 sdhci_pltfm_free(pdev);
1686 return err;
1687 }
1688
sdhci_esdhc_imx_remove(struct platform_device * pdev)1689 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1690 {
1691 struct sdhci_host *host = platform_get_drvdata(pdev);
1692 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1693 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1694 int dead;
1695
1696 pm_runtime_get_sync(&pdev->dev);
1697 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1698 pm_runtime_disable(&pdev->dev);
1699 pm_runtime_put_noidle(&pdev->dev);
1700
1701 sdhci_remove_host(host, dead);
1702
1703 clk_disable_unprepare(imx_data->clk_per);
1704 clk_disable_unprepare(imx_data->clk_ipg);
1705 clk_disable_unprepare(imx_data->clk_ahb);
1706
1707 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1708 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1709
1710 sdhci_pltfm_free(pdev);
1711
1712 return 0;
1713 }
1714
1715 #ifdef CONFIG_PM_SLEEP
sdhci_esdhc_suspend(struct device * dev)1716 static int sdhci_esdhc_suspend(struct device *dev)
1717 {
1718 struct sdhci_host *host = dev_get_drvdata(dev);
1719 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1720 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1721 int ret;
1722
1723 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1724 ret = cqhci_suspend(host->mmc);
1725 if (ret)
1726 return ret;
1727 }
1728
1729 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1730 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1731 mmc_retune_timer_stop(host->mmc);
1732 mmc_retune_needed(host->mmc);
1733 }
1734
1735 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1736 mmc_retune_needed(host->mmc);
1737
1738 ret = sdhci_suspend_host(host);
1739 if (ret)
1740 return ret;
1741
1742 ret = pinctrl_pm_select_sleep_state(dev);
1743 if (ret)
1744 return ret;
1745
1746 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1747
1748 return ret;
1749 }
1750
sdhci_esdhc_resume(struct device * dev)1751 static int sdhci_esdhc_resume(struct device *dev)
1752 {
1753 struct sdhci_host *host = dev_get_drvdata(dev);
1754 int ret;
1755
1756 ret = pinctrl_pm_select_default_state(dev);
1757 if (ret)
1758 return ret;
1759
1760 /* re-initialize hw state in case it's lost in low power mode */
1761 sdhci_esdhc_imx_hwinit(host);
1762
1763 ret = sdhci_resume_host(host);
1764 if (ret)
1765 return ret;
1766
1767 if (host->mmc->caps2 & MMC_CAP2_CQE)
1768 ret = cqhci_resume(host->mmc);
1769
1770 if (!ret)
1771 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1772
1773 return ret;
1774 }
1775 #endif
1776
1777 #ifdef CONFIG_PM
sdhci_esdhc_runtime_suspend(struct device * dev)1778 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1779 {
1780 struct sdhci_host *host = dev_get_drvdata(dev);
1781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1782 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1783 int ret;
1784
1785 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1786 ret = cqhci_suspend(host->mmc);
1787 if (ret)
1788 return ret;
1789 }
1790
1791 ret = sdhci_runtime_suspend_host(host);
1792 if (ret)
1793 return ret;
1794
1795 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1796 mmc_retune_needed(host->mmc);
1797
1798 imx_data->actual_clock = host->mmc->actual_clock;
1799 esdhc_pltfm_set_clock(host, 0);
1800 clk_disable_unprepare(imx_data->clk_per);
1801 clk_disable_unprepare(imx_data->clk_ipg);
1802 clk_disable_unprepare(imx_data->clk_ahb);
1803
1804 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1805 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1806
1807 return ret;
1808 }
1809
sdhci_esdhc_runtime_resume(struct device * dev)1810 static int sdhci_esdhc_runtime_resume(struct device *dev)
1811 {
1812 struct sdhci_host *host = dev_get_drvdata(dev);
1813 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1814 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1815 int err;
1816
1817 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1818 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1819
1820 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1821 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1822
1823 err = clk_prepare_enable(imx_data->clk_ahb);
1824 if (err)
1825 goto remove_pm_qos_request;
1826
1827 err = clk_prepare_enable(imx_data->clk_per);
1828 if (err)
1829 goto disable_ahb_clk;
1830
1831 err = clk_prepare_enable(imx_data->clk_ipg);
1832 if (err)
1833 goto disable_per_clk;
1834
1835 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1836
1837 err = sdhci_runtime_resume_host(host, 0);
1838 if (err)
1839 goto disable_ipg_clk;
1840
1841 if (host->mmc->caps2 & MMC_CAP2_CQE)
1842 err = cqhci_resume(host->mmc);
1843
1844 return err;
1845
1846 disable_ipg_clk:
1847 clk_disable_unprepare(imx_data->clk_ipg);
1848 disable_per_clk:
1849 clk_disable_unprepare(imx_data->clk_per);
1850 disable_ahb_clk:
1851 clk_disable_unprepare(imx_data->clk_ahb);
1852 remove_pm_qos_request:
1853 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1854 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1855 return err;
1856 }
1857 #endif
1858
1859 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1860 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1861 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1862 sdhci_esdhc_runtime_resume, NULL)
1863 };
1864
1865 static struct platform_driver sdhci_esdhc_imx_driver = {
1866 .driver = {
1867 .name = "sdhci-esdhc-imx",
1868 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1869 .of_match_table = imx_esdhc_dt_ids,
1870 .pm = &sdhci_esdhc_pmops,
1871 },
1872 .probe = sdhci_esdhc_imx_probe,
1873 .remove = sdhci_esdhc_imx_remove,
1874 };
1875
1876 module_platform_driver(sdhci_esdhc_imx_driver);
1877
1878 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1879 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1880 MODULE_LICENSE("GPL v2");
1881