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Searched defs:ITNS (Results 1 – 9 of 9) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
Dcore_armv8mbl.h370 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_cm23.h370 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_armv8mml.h503 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_starmc1.h509 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_cm35p.h503 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_cm33.h503 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_armv81mml.h510 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_cm85.h530 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member
Dcore_cm55.h513 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist… member