1 /**************************************************************************//**
2 * @file core_armv8mml.h
3 * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
4 * @version V5.3.0
5 * @date 04. April 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32
33 #ifndef __CORE_ARMV8MML_H_GENERIC
34 #define __CORE_ARMV8MML_H_GENERIC
35
36 #include <stdint.h>
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /**
43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
44 CMSIS violates the following MISRA-C:2004 rules:
45
46 \li Required Rule 8.5, object/function definition in header file.<br>
47 Function definitions in header files are used to allow 'inlining'.
48
49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
50 Unions are used for effective representation of core registers.
51
52 \li Advisory Rule 19.7, Function-like macro defined.<br>
53 Function-like macros are used to allow more efficient code.
54 */
55
56
57 /*******************************************************************************
58 * CMSIS definitions
59 ******************************************************************************/
60 /**
61 \ingroup Cortex_ARMv8MML
62 @{
63 */
64
65 #include "cmsis_version.h"
66
67 /* CMSIS Armv8MML definitions */
68 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
69 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
70 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
71 __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
72
73 #define __CORTEX_M (80U) /*!< Cortex-M Core */
74
75 /** __FPU_USED indicates whether an FPU is used or not.
76 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
77 */
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81 #define __FPU_USED 1U
82 #else
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #define __FPU_USED 0U
85 #endif
86 #else
87 #define __FPU_USED 0U
88 #endif
89
90 #if defined(__ARM_FEATURE_DSP)
91 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
92 #define __DSP_USED 1U
93 #else
94 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
95 #define __DSP_USED 0U
96 #endif
97 #else
98 #define __DSP_USED 0U
99 #endif
100
101 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
102 #if defined __ARM_FP
103 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
104 #define __FPU_USED 1U
105 #else
106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #define __FPU_USED 0U
108 #endif
109 #else
110 #define __FPU_USED 0U
111 #endif
112
113 #if defined(__ARM_FEATURE_DSP)
114 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
115 #define __DSP_USED 1U
116 #else
117 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
118 #define __DSP_USED 0U
119 #endif
120 #else
121 #define __DSP_USED 0U
122 #endif
123
124 #elif defined (__ti__)
125 #if defined (__ARM_FP)
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
137 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
138 #define __DSP_USED 1U
139 #else
140 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
141 #define __DSP_USED 0U
142 #endif
143 #else
144 #define __DSP_USED 0U
145 #endif
146
147 #elif defined ( __GNUC__ )
148 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
149 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
150 #define __FPU_USED 1U
151 #else
152 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
153 #define __FPU_USED 0U
154 #endif
155 #else
156 #define __FPU_USED 0U
157 #endif
158
159 #if defined(__ARM_FEATURE_DSP)
160 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
161 #define __DSP_USED 1U
162 #else
163 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
164 #define __DSP_USED 0U
165 #endif
166 #else
167 #define __DSP_USED 0U
168 #endif
169
170 #elif defined ( __ICCARM__ )
171 #if defined __ARMVFP__
172 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
173 #define __FPU_USED 1U
174 #else
175 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
176 #define __FPU_USED 0U
177 #endif
178 #else
179 #define __FPU_USED 0U
180 #endif
181
182 #if defined(__ARM_FEATURE_DSP)
183 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
184 #define __DSP_USED 1U
185 #else
186 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
187 #define __DSP_USED 0U
188 #endif
189 #else
190 #define __DSP_USED 0U
191 #endif
192
193 #elif defined ( __TI_ARM__ )
194 #if defined __TI_VFP_SUPPORT__
195 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
196 #define __FPU_USED 1U
197 #else
198 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
199 #define __FPU_USED 0U
200 #endif
201 #else
202 #define __FPU_USED 0U
203 #endif
204
205 #elif defined ( __TASKING__ )
206 #if defined __FPU_VFP__
207 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
208 #define __FPU_USED 1U
209 #else
210 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
211 #define __FPU_USED 0U
212 #endif
213 #else
214 #define __FPU_USED 0U
215 #endif
216
217 #elif defined ( __CSMC__ )
218 #if ( __CSMC__ & 0x400U)
219 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
220 #define __FPU_USED 1U
221 #else
222 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
223 #define __FPU_USED 0U
224 #endif
225 #else
226 #define __FPU_USED 0U
227 #endif
228
229 #endif
230
231 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
232
233
234 #ifdef __cplusplus
235 }
236 #endif
237
238 #endif /* __CORE_ARMV8MML_H_GENERIC */
239
240 #ifndef __CMSIS_GENERIC
241
242 #ifndef __CORE_ARMV8MML_H_DEPENDANT
243 #define __CORE_ARMV8MML_H_DEPENDANT
244
245 #ifdef __cplusplus
246 extern "C" {
247 #endif
248
249 /* check device defines and use defaults */
250 #if defined __CHECK_DEVICE_DEFINES
251 #ifndef __ARMv8MML_REV
252 #define __ARMv8MML_REV 0x0000U
253 #warning "__ARMv8MML_REV not defined in device header file; using default!"
254 #endif
255
256 #ifndef __FPU_PRESENT
257 #define __FPU_PRESENT 0U
258 #warning "__FPU_PRESENT not defined in device header file; using default!"
259 #endif
260
261 #ifndef __MPU_PRESENT
262 #define __MPU_PRESENT 0U
263 #warning "__MPU_PRESENT not defined in device header file; using default!"
264 #endif
265
266 #ifndef __SAUREGION_PRESENT
267 #define __SAUREGION_PRESENT 0U
268 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
269 #endif
270
271 #ifndef __DSP_PRESENT
272 #define __DSP_PRESENT 0U
273 #warning "__DSP_PRESENT not defined in device header file; using default!"
274 #endif
275
276 #ifndef __VTOR_PRESENT
277 #define __VTOR_PRESENT 1U
278 #warning "__VTOR_PRESENT not defined in device header file; using default!"
279 #endif
280
281 #ifndef __NVIC_PRIO_BITS
282 #define __NVIC_PRIO_BITS 3U
283 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
284 #endif
285
286 #ifndef __Vendor_SysTickConfig
287 #define __Vendor_SysTickConfig 0U
288 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
289 #endif
290 #endif
291
292 /* IO definitions (access restrictions to peripheral registers) */
293 /**
294 \defgroup CMSIS_glob_defs CMSIS Global Defines
295
296 <strong>IO Type Qualifiers</strong> are used
297 \li to specify the access to peripheral variables.
298 \li for automatic generation of peripheral register debug information.
299 */
300 #ifdef __cplusplus
301 #define __I volatile /*!< Defines 'read only' permissions */
302 #else
303 #define __I volatile const /*!< Defines 'read only' permissions */
304 #endif
305 #define __O volatile /*!< Defines 'write only' permissions */
306 #define __IO volatile /*!< Defines 'read / write' permissions */
307
308 /* following defines should be used for structure members */
309 #define __IM volatile const /*! Defines 'read only' structure member permissions */
310 #define __OM volatile /*! Defines 'write only' structure member permissions */
311 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
312
313 /** @} end of group ARMv8MML */
314
315
316
317 /*******************************************************************************
318 * Register Abstraction
319 Core Register contain:
320 - Core Register
321 - Core NVIC Register
322 - Core SCB Register
323 - Core SysTick Register
324 - Core Debug Register
325 - Core MPU Register
326 - Core SAU Register
327 - Core FPU Register
328 ******************************************************************************/
329 /**
330 \defgroup CMSIS_core_register Defines and Type Definitions
331 \brief Type definitions and defines for Cortex-M processor based devices.
332 */
333
334 /**
335 \ingroup CMSIS_core_register
336 \defgroup CMSIS_CORE Status and Control Registers
337 \brief Core Register type definitions.
338 @{
339 */
340
341 /**
342 \brief Union type to access the Application Program Status Register (APSR).
343 */
344 typedef union
345 {
346 struct
347 {
348 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
349 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
350 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
356 } b; /*!< Structure used for bit access */
357 uint32_t w; /*!< Type used for word access */
358 } APSR_Type;
359
360 /* APSR Register Definitions */
361 #define APSR_N_Pos 31U /*!< APSR: N Position */
362 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
363
364 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
365 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
366
367 #define APSR_C_Pos 29U /*!< APSR: C Position */
368 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
369
370 #define APSR_V_Pos 28U /*!< APSR: V Position */
371 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
372
373 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
374 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
375
376 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
377 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
378
379
380 /**
381 \brief Union type to access the Interrupt Program Status Register (IPSR).
382 */
383 typedef union
384 {
385 struct
386 {
387 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
388 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
389 } b; /*!< Structure used for bit access */
390 uint32_t w; /*!< Type used for word access */
391 } IPSR_Type;
392
393 /* IPSR Register Definitions */
394 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
395 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
396
397
398 /**
399 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
400 */
401 typedef union
402 {
403 struct
404 {
405 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
406 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
407 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
408 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
409 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
410 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
411 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
412 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
413 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
414 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
415 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
416 } b; /*!< Structure used for bit access */
417 uint32_t w; /*!< Type used for word access */
418 } xPSR_Type;
419
420 /* xPSR Register Definitions */
421 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
422 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
423
424 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
425 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
426
427 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
428 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
429
430 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
431 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
432
433 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
434 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
435
436 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
437 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
438
439 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
440 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
441
442 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
443 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
444
445 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
446 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
447
448
449 /**
450 \brief Union type to access the Control Registers (CONTROL).
451 */
452 typedef union
453 {
454 struct
455 {
456 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
457 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
458 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
459 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
460 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
461 } b; /*!< Structure used for bit access */
462 uint32_t w; /*!< Type used for word access */
463 } CONTROL_Type;
464
465 /* CONTROL Register Definitions */
466 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
467 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
468
469 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
470 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
471
472 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
473 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
474
475 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
476 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
477
478 /** @} end of group CMSIS_CORE */
479
480
481 /**
482 \ingroup CMSIS_core_register
483 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
484 \brief Type definitions for the NVIC Registers
485 @{
486 */
487
488 /**
489 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
490 */
491 typedef struct
492 {
493 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
494 uint32_t RESERVED0[16U];
495 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
496 uint32_t RSERVED1[16U];
497 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
498 uint32_t RESERVED2[16U];
499 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
500 uint32_t RESERVED3[16U];
501 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
502 uint32_t RESERVED4[16U];
503 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
504 uint32_t RESERVED5[16U];
505 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
506 uint32_t RESERVED6[580U];
507 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
508 } NVIC_Type;
509
510 /* Software Triggered Interrupt Register Definitions */
511 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
512 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
513
514 /** @} end of group CMSIS_NVIC */
515
516
517 /**
518 \ingroup CMSIS_core_register
519 \defgroup CMSIS_SCB System Control Block (SCB)
520 \brief Type definitions for the System Control Block Registers
521 @{
522 */
523
524 /**
525 \brief Structure type to access the System Control Block (SCB).
526 */
527 typedef struct
528 {
529 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
530 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
531 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
532 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
533 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
534 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
535 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
536 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
537 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
538 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
539 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
540 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
541 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
542 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
543 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
544 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
545 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
546 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
547 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
548 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
549 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
550 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
551 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
552 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
553 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
554 uint32_t RESERVED7[21U];
555 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
556 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
557 uint32_t RESERVED3[69U];
558 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
559 uint32_t RESERVED4[15U];
560 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
561 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
562 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
563 uint32_t RESERVED5[1U];
564 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
565 uint32_t RESERVED6[1U];
566 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
567 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
568 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
569 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
570 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
571 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
572 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
573 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
574 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
575 } SCB_Type;
576
577 /* SCB CPUID Register Definitions */
578 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
579 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
580
581 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
582 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
583
584 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
585 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
586
587 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
588 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
589
590 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
591 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
592
593 /* SCB Interrupt Control State Register Definitions */
594 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
595 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
596
597 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
598 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
599
600 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
601 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
602
603 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
604 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
605
606 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
607 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
608
609 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
610 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
611
612 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
613 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
614
615 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
616 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
617
618 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
619 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
620
621 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
622 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
623
624 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
625 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
626
627 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
628 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
629
630 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
631 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
632
633 /* SCB Vector Table Offset Register Definitions */
634 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
635 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
636
637 /* SCB Application Interrupt and Reset Control Register Definitions */
638 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
639 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
640
641 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
642 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
643
644 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
645 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
646
647 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
648 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
649
650 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
651 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
652
653 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
654 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
655
656 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
657 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
658
659 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
660 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
661
662 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
663 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
664
665 /* SCB System Control Register Definitions */
666 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
667 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
668
669 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
670 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
671
672 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
673 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
674
675 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
676 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
677
678 /* SCB Configuration Control Register Definitions */
679 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
680 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
681
682 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
683 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
684
685 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
686 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
687
688 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
689 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
690
691 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
692 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
693
694 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
695 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
696
697 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
698 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
699
700 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
701 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
702
703 /* SCB System Handler Control and State Register Definitions */
704 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
705 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
706
707 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
708 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
709
710 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
711 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
712
713 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
714 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
715
716 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
717 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
718
719 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
720 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
721
722 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
723 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
724
725 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
726 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
727
728 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
729 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
730
731 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
732 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
733
734 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
735 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
736
737 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
738 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
739
740 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
741 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
742
743 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
744 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
745
746 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
747 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
748
749 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
750 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
751
752 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
753 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
754
755 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
756 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
757
758 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
759 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
760
761 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
762 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
763
764 /* SCB Configurable Fault Status Register Definitions */
765 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
766 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
767
768 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
769 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
770
771 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
772 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
773
774 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
775 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
776 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
777
778 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
779 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
780
781 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
782 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
783
784 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
785 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
786
787 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
788 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
789
790 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
791 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
792
793 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
794 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
795 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
796
797 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
798 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
799
800 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
801 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
802
803 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
804 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
805
806 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
807 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
808
809 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
810 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
811
812 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
813 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
814
815 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
816 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
817 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
818
819 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
820 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
821
822 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
823 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
824
825 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
826 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
827
828 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
829 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
830
831 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
832 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
833
834 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
835 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
836
837 /* SCB Hard Fault Status Register Definitions */
838 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
839 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
840
841 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
842 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
843
844 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
845 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
846
847 /* SCB Debug Fault Status Register Definitions */
848 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
849 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
850
851 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
852 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
853
854 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
855 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
856
857 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
858 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
859
860 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
861 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
862
863 /* SCB Non-Secure Access Control Register Definitions */
864 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
865 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
866
867 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
868 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
869
870 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
871 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
872
873 /* SCB Cache Level ID Register Definitions */
874 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
875 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
876
877 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
878 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
879
880 /* SCB Cache Type Register Definitions */
881 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
882 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
883
884 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
885 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
886
887 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
888 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
889
890 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
891 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
892
893 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
894 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
895
896 /* SCB Cache Size ID Register Definitions */
897 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
898 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
899
900 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
901 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
902
903 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
904 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
905
906 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
907 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
908
909 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
910 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
911
912 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
913 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
914
915 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
916 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
917
918 /* SCB Cache Size Selection Register Definitions */
919 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
920 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
921
922 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
923 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
924
925 /* SCB Software Triggered Interrupt Register Definitions */
926 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
927 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
928
929 /* SCB D-Cache Invalidate by Set-way Register Definitions */
930 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
931 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
932
933 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
934 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
935
936 /* SCB D-Cache Clean by Set-way Register Definitions */
937 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
938 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
939
940 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
941 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
942
943 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
944 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
945 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
946
947 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
948 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
949
950 /** @} end of group CMSIS_SCB */
951
952
953 /**
954 \ingroup CMSIS_core_register
955 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
956 \brief Type definitions for the System Control and ID Register not in the SCB
957 @{
958 */
959
960 /**
961 \brief Structure type to access the System Control and ID Register not in the SCB.
962 */
963 typedef struct
964 {
965 uint32_t RESERVED0[1U];
966 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
967 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
968 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
969 } SCnSCB_Type;
970
971 /* Interrupt Controller Type Register Definitions */
972 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
973 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
974
975 /** @} end of group CMSIS_SCnotSCB */
976
977
978 /**
979 \ingroup CMSIS_core_register
980 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
981 \brief Type definitions for the System Timer Registers.
982 @{
983 */
984
985 /**
986 \brief Structure type to access the System Timer (SysTick).
987 */
988 typedef struct
989 {
990 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
991 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
992 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
993 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
994 } SysTick_Type;
995
996 /* SysTick Control / Status Register Definitions */
997 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
998 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
999
1000 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1001 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1002
1003 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1004 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1005
1006 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1007 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1008
1009 /* SysTick Reload Register Definitions */
1010 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1011 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1012
1013 /* SysTick Current Register Definitions */
1014 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1015 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1016
1017 /* SysTick Calibration Register Definitions */
1018 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1019 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1020
1021 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1022 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1023
1024 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1025 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1026
1027 /** @} end of group CMSIS_SysTick */
1028
1029
1030 /**
1031 \ingroup CMSIS_core_register
1032 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1033 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1034 @{
1035 */
1036
1037 /**
1038 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1039 */
1040 typedef struct
1041 {
1042 __OM union
1043 {
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1047 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1048 uint32_t RESERVED0[864U];
1049 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1050 uint32_t RESERVED1[15U];
1051 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1052 uint32_t RESERVED2[15U];
1053 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1054 uint32_t RESERVED3[32U];
1055 uint32_t RESERVED4[43U];
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1057 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1058 uint32_t RESERVED5[1U];
1059 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1060 uint32_t RESERVED6[4U];
1061 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1062 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1063 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1064 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1065 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1066 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1067 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1068 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1069 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1070 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1071 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1072 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1073 } ITM_Type;
1074
1075 /* ITM Stimulus Port Register Definitions */
1076 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1077 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1078
1079 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1080 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1081
1082 /* ITM Trace Privilege Register Definitions */
1083 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1084 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1085
1086 /* ITM Trace Control Register Definitions */
1087 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1088 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1089
1090 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1091 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1092
1093 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1094 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1095
1096 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1097 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1098
1099 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1100 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1101
1102 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1103 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1104
1105 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1106 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1107
1108 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1109 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1110
1111 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1112 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1113
1114 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1115 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1116
1117 /* ITM Lock Status Register Definitions */
1118 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1119 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1120
1121 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1122 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1123
1124 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1125 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1126
1127 /** @}*/ /* end of group CMSIS_ITM */
1128
1129
1130 /**
1131 \ingroup CMSIS_core_register
1132 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1133 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1134 @{
1135 */
1136
1137 /**
1138 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1139 */
1140 typedef struct
1141 {
1142 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1143 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1144 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1145 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1146 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1147 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1148 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1149 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1150 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1151 uint32_t RESERVED1[1U];
1152 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1153 uint32_t RESERVED2[1U];
1154 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1155 uint32_t RESERVED3[1U];
1156 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1157 uint32_t RESERVED4[1U];
1158 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1159 uint32_t RESERVED5[1U];
1160 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1161 uint32_t RESERVED6[1U];
1162 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1163 uint32_t RESERVED7[1U];
1164 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1165 uint32_t RESERVED8[1U];
1166 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1167 uint32_t RESERVED9[1U];
1168 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1169 uint32_t RESERVED10[1U];
1170 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1171 uint32_t RESERVED11[1U];
1172 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1173 uint32_t RESERVED12[1U];
1174 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1175 uint32_t RESERVED13[1U];
1176 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1177 uint32_t RESERVED14[1U];
1178 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1179 uint32_t RESERVED15[1U];
1180 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1181 uint32_t RESERVED16[1U];
1182 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1183 uint32_t RESERVED17[1U];
1184 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1185 uint32_t RESERVED18[1U];
1186 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1187 uint32_t RESERVED19[1U];
1188 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1189 uint32_t RESERVED20[1U];
1190 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1191 uint32_t RESERVED21[1U];
1192 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1193 uint32_t RESERVED22[1U];
1194 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1195 uint32_t RESERVED23[1U];
1196 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1197 uint32_t RESERVED24[1U];
1198 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1199 uint32_t RESERVED25[1U];
1200 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1201 uint32_t RESERVED26[1U];
1202 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1203 uint32_t RESERVED27[1U];
1204 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1205 uint32_t RESERVED28[1U];
1206 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1207 uint32_t RESERVED29[1U];
1208 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1209 uint32_t RESERVED30[1U];
1210 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1211 uint32_t RESERVED31[1U];
1212 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1213 uint32_t RESERVED32[934U];
1214 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1215 uint32_t RESERVED33[1U];
1216 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1217 } DWT_Type;
1218
1219 /* DWT Control Register Definitions */
1220 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1221 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1222
1223 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1224 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1225
1226 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1227 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1228
1229 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1230 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1231
1232 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1233 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1234
1235 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1236 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1237
1238 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1239 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1240
1241 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1242 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1243
1244 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1245 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1246
1247 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1248 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1249
1250 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1251 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1252
1253 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1254 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1255
1256 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1257 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1258
1259 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1260 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1261
1262 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1263 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1264
1265 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1266 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1267
1268 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1269 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1270
1271 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1272 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1273
1274 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1275 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1276
1277 /* DWT CPI Count Register Definitions */
1278 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1279 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1280
1281 /* DWT Exception Overhead Count Register Definitions */
1282 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1283 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1284
1285 /* DWT Sleep Count Register Definitions */
1286 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1287 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1288
1289 /* DWT LSU Count Register Definitions */
1290 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1291 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1292
1293 /* DWT Folded-instruction Count Register Definitions */
1294 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1295 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1296
1297 /* DWT Comparator Function Register Definitions */
1298 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1299 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1300
1301 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1302 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1303
1304 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1305 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1306
1307 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1308 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1309
1310 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1311 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1312
1313 /** @}*/ /* end of group CMSIS_DWT */
1314
1315
1316 /**
1317 \ingroup CMSIS_core_register
1318 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1319 \brief Type definitions for the Trace Port Interface (TPI)
1320 @{
1321 */
1322
1323 /**
1324 \brief Structure type to access the Trace Port Interface Register (TPI).
1325 */
1326 typedef struct
1327 {
1328 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
1329 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
1330 uint32_t RESERVED0[2U];
1331 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1332 uint32_t RESERVED1[55U];
1333 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1334 uint32_t RESERVED2[131U];
1335 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1336 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1337 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1338 uint32_t RESERVED3[809U];
1339 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
1340 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
1341 uint32_t RESERVED4[4U];
1342 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
1343 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
1344 } TPI_Type;
1345
1346 /* TPI Asynchronous Clock Prescaler Register Definitions */
1347 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
1348 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
1349
1350 /* TPI Selected Pin Protocol Register Definitions */
1351 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1352 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1353
1354 /* TPI Formatter and Flush Status Register Definitions */
1355 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1356 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1357
1358 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1359 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1360
1361 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1362 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1363
1364 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1365 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1366
1367 /* TPI Formatter and Flush Control Register Definitions */
1368 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1369 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1370
1371 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
1372 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
1373
1374 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1375 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1376
1377 /* TPI Periodic Synchronization Control Register Definitions */
1378 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
1379 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
1380
1381 /* TPI Software Lock Status Register Definitions */
1382 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
1383 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
1384
1385 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
1386 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
1387
1388 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
1389 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
1390
1391 /* TPI DEVID Register Definitions */
1392 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1393 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1394
1395 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1396 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1397
1398 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1399 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1400
1401 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
1402 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
1403
1404 /* TPI DEVTYPE Register Definitions */
1405 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1406 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1407
1408 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1409 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1410
1411 /** @}*/ /* end of group CMSIS_TPI */
1412
1413
1414 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1415 /**
1416 \ingroup CMSIS_core_register
1417 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1418 \brief Type definitions for the Memory Protection Unit (MPU)
1419 @{
1420 */
1421
1422 /**
1423 \brief Structure type to access the Memory Protection Unit (MPU).
1424 */
1425 typedef struct
1426 {
1427 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1428 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1429 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1430 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1431 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1432 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1433 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1434 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1435 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1436 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1437 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1438 uint32_t RESERVED0[1];
1439 union {
1440 __IOM uint32_t MAIR[2];
1441 struct {
1442 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1443 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1444 };
1445 };
1446 } MPU_Type;
1447
1448 #define MPU_TYPE_RALIASES 4U
1449
1450 /* MPU Type Register Definitions */
1451 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1452 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1453
1454 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1455 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1456
1457 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1458 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1459
1460 /* MPU Control Register Definitions */
1461 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1462 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1463
1464 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1465 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1466
1467 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1468 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1469
1470 /* MPU Region Number Register Definitions */
1471 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1472 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1473
1474 /* MPU Region Base Address Register Definitions */
1475 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1476 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1477
1478 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1479 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1480
1481 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1482 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1483
1484 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1485 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1486
1487 /* MPU Region Limit Address Register Definitions */
1488 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1489 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1490
1491 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1492 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1493
1494 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1495 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1496
1497 /* MPU Memory Attribute Indirection Register 0 Definitions */
1498 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1499 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1500
1501 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1502 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1503
1504 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1505 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1506
1507 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1508 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1509
1510 /* MPU Memory Attribute Indirection Register 1 Definitions */
1511 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1512 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1513
1514 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1515 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1516
1517 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1518 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1519
1520 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1521 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1522
1523 /** @} end of group CMSIS_MPU */
1524 #endif
1525
1526
1527 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1528 /**
1529 \ingroup CMSIS_core_register
1530 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1531 \brief Type definitions for the Security Attribution Unit (SAU)
1532 @{
1533 */
1534
1535 /**
1536 \brief Structure type to access the Security Attribution Unit (SAU).
1537 */
1538 typedef struct
1539 {
1540 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1541 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1542 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1543 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1544 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1545 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1546 #else
1547 uint32_t RESERVED0[3];
1548 #endif
1549 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1550 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1551 } SAU_Type;
1552
1553 /* SAU Control Register Definitions */
1554 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1555 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1556
1557 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1558 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1559
1560 /* SAU Type Register Definitions */
1561 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1562 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1563
1564 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1565 /* SAU Region Number Register Definitions */
1566 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1567 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1568
1569 /* SAU Region Base Address Register Definitions */
1570 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1571 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1572
1573 /* SAU Region Limit Address Register Definitions */
1574 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1575 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1576
1577 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1578 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1579
1580 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1581 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1582
1583 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1584
1585 /* Secure Fault Status Register Definitions */
1586 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1587 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1588
1589 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1590 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1591
1592 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1593 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1594
1595 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1596 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1597
1598 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1599 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1600
1601 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1602 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1603
1604 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1605 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1606
1607 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1608 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1609
1610 /** @} end of group CMSIS_SAU */
1611 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1612
1613
1614 /**
1615 \ingroup CMSIS_core_register
1616 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1617 \brief Type definitions for the Floating Point Unit (FPU)
1618 @{
1619 */
1620
1621 /**
1622 \brief Structure type to access the Floating Point Unit (FPU).
1623 */
1624 typedef struct
1625 {
1626 uint32_t RESERVED0[1U];
1627 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1628 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1629 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1630 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1631 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1632 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1633 } FPU_Type;
1634
1635 /* Floating-Point Context Control Register Definitions */
1636 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1637 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1638
1639 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1640 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1641
1642 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1643 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1644
1645 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1646 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1647
1648 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1649 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1650
1651 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1652 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1653
1654 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1655 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1656
1657 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1658 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1659
1660 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1661 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1662
1663 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1664 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1665
1666 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1667 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1668
1669 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1670 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1671
1672 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1673 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1674
1675 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1676 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1677
1678 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1679 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1680
1681 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1682 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1683
1684 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1685 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1686
1687 /* Floating-Point Context Address Register Definitions */
1688 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1689 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1690
1691 /* Floating-Point Default Status Control Register Definitions */
1692 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1693 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1694
1695 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1696 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1697
1698 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1699 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1700
1701 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1702 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1703
1704 /* Media and VFP Feature Register 0 Definitions */
1705 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1706 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1707
1708 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1709 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1710
1711 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1712 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1713
1714 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1715 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1716
1717 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1718 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1719
1720 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1721 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1722
1723 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1724 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1725
1726 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1727 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1728
1729 /* Media and VFP Feature Register 1 Definitions */
1730 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1731 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1732
1733 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1734 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1735
1736 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1737 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1738
1739 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1740 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1741
1742 /* Media and VFP Feature Register 2 Definitions */
1743 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
1744 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
1745
1746 /** @} end of group CMSIS_FPU */
1747
1748 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1749 /**
1750 \ingroup CMSIS_core_register
1751 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1752 \brief Type definitions for the Core Debug Registers
1753 @{
1754 */
1755
1756 /**
1757 \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
1758 */
1759 typedef struct
1760 {
1761 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1762 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1763 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1764 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1765 uint32_t RESERVED0[1U];
1766 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1767 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1768 } CoreDebug_Type;
1769
1770 /* Debug Halting Control and Status Register Definitions */
1771 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
1772 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
1773
1774 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
1775 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
1776
1777 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
1778 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
1779
1780 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
1781 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
1782
1783 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
1784 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
1785
1786 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
1787 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
1788
1789 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
1790 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
1791
1792 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
1793 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
1794
1795 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
1796 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
1797
1798 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
1799 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
1800
1801 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
1802 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
1803
1804 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
1805 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
1806
1807 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
1808 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
1809
1810 /* Debug Core Register Selector Register Definitions */
1811 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
1812 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
1813
1814 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
1815 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
1816
1817 /* Debug Exception and Monitor Control Register Definitions */
1818 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
1819 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
1820
1821 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
1822 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
1823
1824 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
1825 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
1826
1827 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
1828 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
1829
1830 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
1831 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
1832
1833 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
1834 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
1835
1836 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
1837 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
1838
1839 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
1840 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
1841
1842 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
1843 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
1844
1845 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
1846 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
1847
1848 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
1849 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
1850
1851 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
1852 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
1853
1854 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
1855 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
1856
1857 /* Debug Authentication Control Register Definitions */
1858 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1859 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1860
1861 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1862 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1863
1864 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
1865 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1866
1867 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
1868 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1869
1870 /* Debug Security Control and Status Register Definitions */
1871 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
1872 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
1873
1874 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
1875 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
1876
1877 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
1878 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
1879
1880 /** @} end of group CMSIS_CoreDebug */
1881
1882
1883 /**
1884 \ingroup CMSIS_core_register
1885 \defgroup CMSIS_DCB Debug Control Block
1886 \brief Type definitions for the Debug Control Block Registers
1887 @{
1888 */
1889
1890 /**
1891 \brief Structure type to access the Debug Control Block Registers (DCB).
1892 */
1893 typedef struct
1894 {
1895 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1896 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1897 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1898 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1899 uint32_t RESERVED0[1U];
1900 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1901 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1902 } DCB_Type;
1903
1904 /* DHCSR, Debug Halting Control and Status Register Definitions */
1905 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1906 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1907
1908 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1909 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1910
1911 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1912 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1913
1914 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1915 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1916
1917 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1918 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1919
1920 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1921 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1922
1923 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1924 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1925
1926 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1927 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1928
1929 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1930 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1931
1932 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1933 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1934
1935 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1936 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1937
1938 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1939 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1940
1941 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1942 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1943
1944 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1945 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1946
1947 /* DCRSR, Debug Core Register Select Register Definitions */
1948 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1949 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1950
1951 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1952 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1953
1954 /* DCRDR, Debug Core Register Data Register Definitions */
1955 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1956 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1957
1958 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1959 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1960 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1961
1962 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
1963 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
1964
1965 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
1966 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
1967
1968 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
1969 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
1970
1971 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1972 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1973
1974 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1975 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1976
1977 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1978 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1979
1980 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1981 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1982
1983 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
1984 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
1985
1986 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1987 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1988
1989 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1990 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1991
1992 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1993 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1994
1995 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1996 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1997
1998 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1999 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
2000
2001 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
2002 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
2003
2004 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
2005 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
2006
2007 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
2008 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
2009
2010 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
2011 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
2012 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
2013
2014 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
2015 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
2016
2017 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
2018 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
2019
2020 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
2021 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
2022
2023 /* DSCSR, Debug Security Control and Status Register Definitions */
2024 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
2025 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
2026
2027 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
2028 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
2029
2030 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
2031 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
2032
2033 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
2034 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
2035
2036 /** @} end of group CMSIS_DCB */
2037
2038
2039
2040 /**
2041 \ingroup CMSIS_core_register
2042 \defgroup CMSIS_DIB Debug Identification Block
2043 \brief Type definitions for the Debug Identification Block Registers
2044 @{
2045 */
2046
2047 /**
2048 \brief Structure type to access the Debug Identification Block Registers (DIB).
2049 */
2050 typedef struct
2051 {
2052 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
2053 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
2054 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
2055 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
2056 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
2057 } DIB_Type;
2058
2059 /* DLAR, SCS Software Lock Access Register Definitions */
2060 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
2061 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
2062
2063 /* DLSR, SCS Software Lock Status Register Definitions */
2064 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
2065 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
2066
2067 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
2068 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
2069
2070 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
2071 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
2072
2073 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2074 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
2075 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
2076
2077 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
2078 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
2079
2080 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
2081 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
2082
2083 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
2084 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
2085
2086 /* DDEVARCH, SCS Device Architecture Register Definitions */
2087 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
2088 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
2089
2090 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
2091 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
2092
2093 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
2094 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
2095
2096 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
2097 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
2098
2099 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
2100 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
2101
2102 /* DDEVTYPE, SCS Device Type Register Definitions */
2103 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
2104 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
2105
2106 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
2107 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
2108
2109
2110 /** @} end of group CMSIS_DIB */
2111
2112
2113 /**
2114 \ingroup CMSIS_core_register
2115 \defgroup CMSIS_core_bitfield Core register bit field macros
2116 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2117 @{
2118 */
2119
2120 /**
2121 \brief Mask and shift a bit field value for use in a register bit range.
2122 \param[in] field Name of the register bit field.
2123 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2124 \return Masked and shifted value.
2125 */
2126 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2127
2128 /**
2129 \brief Mask and shift a register value to extract a bit filed value.
2130 \param[in] field Name of the register bit field.
2131 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2132 \return Masked and shifted bit field value.
2133 */
2134 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2135
2136 /** @} end of group CMSIS_core_bitfield */
2137
2138
2139 /**
2140 \ingroup CMSIS_core_register
2141 \defgroup CMSIS_core_base Core Definitions
2142 \brief Definitions for base addresses, unions, and structures.
2143 @{
2144 */
2145
2146 /* Memory mapping of Core Hardware */
2147 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2148 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2149 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2150 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
2151 #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
2152 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
2153 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
2154 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2155 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2156 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2157
2158 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2159 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2160 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2161 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2162 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2163 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2164 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
2165 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
2166 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
2167 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
2168
2169 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2170 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2171 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2172 #endif
2173
2174 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2175 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2176 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2177 #endif
2178
2179 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2180 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2181
2182 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2183 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2184 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
2185 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
2186 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
2187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2190
2191 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2192 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2193 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2194 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2195 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
2196 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
2197 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
2198
2199 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2200 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2201 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2202 #endif
2203
2204 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2205 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2206
2207 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2208 /** @} */
2209
2210
2211 /**
2212 \ingroup CMSIS_core_register
2213 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
2214 \brief Register alias definitions for backwards compatibility.
2215 @{
2216 */
2217 #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
2218 /*@} */
2219
2220
2221 /*******************************************************************************
2222 * Hardware Abstraction Layer
2223 Core Function Interface contains:
2224 - Core NVIC Functions
2225 - Core SysTick Functions
2226 - Core Debug Functions
2227 - Core Register Access Functions
2228 ******************************************************************************/
2229 /**
2230 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2231 */
2232
2233
2234
2235 /* ########################## NVIC functions #################################### */
2236 /**
2237 \ingroup CMSIS_Core_FunctionInterface
2238 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2239 \brief Functions that manage interrupts and exceptions via the NVIC.
2240 @{
2241 */
2242
2243 #ifdef CMSIS_NVIC_VIRTUAL
2244 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2245 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2246 #endif
2247 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2248 #else
2249 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2250 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2251 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2252 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2253 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2254 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2255 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2256 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2257 #define NVIC_GetActive __NVIC_GetActive
2258 #define NVIC_SetPriority __NVIC_SetPriority
2259 #define NVIC_GetPriority __NVIC_GetPriority
2260 #define NVIC_SystemReset __NVIC_SystemReset
2261 #endif /* CMSIS_NVIC_VIRTUAL */
2262
2263 #ifdef CMSIS_VECTAB_VIRTUAL
2264 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2265 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2266 #endif
2267 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2268 #else
2269 #define NVIC_SetVector __NVIC_SetVector
2270 #define NVIC_GetVector __NVIC_GetVector
2271 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2272
2273 #define NVIC_USER_IRQ_OFFSET 16
2274
2275
2276 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2277
2278 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2279 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2280
2281 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2282 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2283 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2284 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2285 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2286 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2287 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2288 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2289
2290 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2291 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2292 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2293 #else
2294 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2295 #endif
2296
2297
2298 /**
2299 \brief Set Priority Grouping
2300 \details Sets the priority grouping field using the required unlock sequence.
2301 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2302 Only values from 0..7 are used.
2303 In case of a conflict between priority grouping and available
2304 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2305 \param [in] PriorityGroup Priority grouping field.
2306 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2307 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2308 {
2309 uint32_t reg_value;
2310 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2311
2312 reg_value = SCB->AIRCR; /* read old register configuration */
2313 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2314 reg_value = (reg_value |
2315 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2316 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2317 SCB->AIRCR = reg_value;
2318 }
2319
2320
2321 /**
2322 \brief Get Priority Grouping
2323 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2324 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2325 */
__NVIC_GetPriorityGrouping(void)2326 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2327 {
2328 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2329 }
2330
2331
2332 /**
2333 \brief Enable Interrupt
2334 \details Enables a device specific interrupt in the NVIC interrupt controller.
2335 \param [in] IRQn Device specific interrupt number.
2336 \note IRQn must not be negative.
2337 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2338 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2339 {
2340 if ((int32_t)(IRQn) >= 0)
2341 {
2342 __COMPILER_BARRIER();
2343 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2344 __COMPILER_BARRIER();
2345 }
2346 }
2347
2348
2349 /**
2350 \brief Get Interrupt Enable status
2351 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2352 \param [in] IRQn Device specific interrupt number.
2353 \return 0 Interrupt is not enabled.
2354 \return 1 Interrupt is enabled.
2355 \note IRQn must not be negative.
2356 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2357 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2358 {
2359 if ((int32_t)(IRQn) >= 0)
2360 {
2361 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2362 }
2363 else
2364 {
2365 return(0U);
2366 }
2367 }
2368
2369
2370 /**
2371 \brief Disable Interrupt
2372 \details Disables a device specific interrupt in the NVIC interrupt controller.
2373 \param [in] IRQn Device specific interrupt number.
2374 \note IRQn must not be negative.
2375 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2376 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2377 {
2378 if ((int32_t)(IRQn) >= 0)
2379 {
2380 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2381 __DSB();
2382 __ISB();
2383 }
2384 }
2385
2386
2387 /**
2388 \brief Get Pending Interrupt
2389 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2390 \param [in] IRQn Device specific interrupt number.
2391 \return 0 Interrupt status is not pending.
2392 \return 1 Interrupt status is pending.
2393 \note IRQn must not be negative.
2394 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2395 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2396 {
2397 if ((int32_t)(IRQn) >= 0)
2398 {
2399 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2400 }
2401 else
2402 {
2403 return(0U);
2404 }
2405 }
2406
2407
2408 /**
2409 \brief Set Pending Interrupt
2410 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2411 \param [in] IRQn Device specific interrupt number.
2412 \note IRQn must not be negative.
2413 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2414 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2415 {
2416 if ((int32_t)(IRQn) >= 0)
2417 {
2418 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2419 }
2420 }
2421
2422
2423 /**
2424 \brief Clear Pending Interrupt
2425 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2426 \param [in] IRQn Device specific interrupt number.
2427 \note IRQn must not be negative.
2428 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2429 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2430 {
2431 if ((int32_t)(IRQn) >= 0)
2432 {
2433 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2434 }
2435 }
2436
2437
2438 /**
2439 \brief Get Active Interrupt
2440 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2441 \param [in] IRQn Device specific interrupt number.
2442 \return 0 Interrupt status is not active.
2443 \return 1 Interrupt status is active.
2444 \note IRQn must not be negative.
2445 */
__NVIC_GetActive(IRQn_Type IRQn)2446 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2447 {
2448 if ((int32_t)(IRQn) >= 0)
2449 {
2450 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2451 }
2452 else
2453 {
2454 return(0U);
2455 }
2456 }
2457
2458
2459 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2460 /**
2461 \brief Get Interrupt Target State
2462 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2463 \param [in] IRQn Device specific interrupt number.
2464 \return 0 if interrupt is assigned to Secure
2465 \return 1 if interrupt is assigned to Non Secure
2466 \note IRQn must not be negative.
2467 */
NVIC_GetTargetState(IRQn_Type IRQn)2468 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2469 {
2470 if ((int32_t)(IRQn) >= 0)
2471 {
2472 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2473 }
2474 else
2475 {
2476 return(0U);
2477 }
2478 }
2479
2480
2481 /**
2482 \brief Set Interrupt Target State
2483 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2484 \param [in] IRQn Device specific interrupt number.
2485 \return 0 if interrupt is assigned to Secure
2486 1 if interrupt is assigned to Non Secure
2487 \note IRQn must not be negative.
2488 */
NVIC_SetTargetState(IRQn_Type IRQn)2489 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2490 {
2491 if ((int32_t)(IRQn) >= 0)
2492 {
2493 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2494 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2495 }
2496 else
2497 {
2498 return(0U);
2499 }
2500 }
2501
2502
2503 /**
2504 \brief Clear Interrupt Target State
2505 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2506 \param [in] IRQn Device specific interrupt number.
2507 \return 0 if interrupt is assigned to Secure
2508 1 if interrupt is assigned to Non Secure
2509 \note IRQn must not be negative.
2510 */
NVIC_ClearTargetState(IRQn_Type IRQn)2511 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2512 {
2513 if ((int32_t)(IRQn) >= 0)
2514 {
2515 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2516 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2517 }
2518 else
2519 {
2520 return(0U);
2521 }
2522 }
2523 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2524
2525
2526 /**
2527 \brief Set Interrupt Priority
2528 \details Sets the priority of a device specific interrupt or a processor exception.
2529 The interrupt number can be positive to specify a device specific interrupt,
2530 or negative to specify a processor exception.
2531 \param [in] IRQn Interrupt number.
2532 \param [in] priority Priority to set.
2533 \note The priority cannot be set for every processor exception.
2534 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2535 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2536 {
2537 if ((int32_t)(IRQn) >= 0)
2538 {
2539 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2540 }
2541 else
2542 {
2543 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2544 }
2545 }
2546
2547
2548 /**
2549 \brief Get Interrupt Priority
2550 \details Reads the priority of a device specific interrupt or a processor exception.
2551 The interrupt number can be positive to specify a device specific interrupt,
2552 or negative to specify a processor exception.
2553 \param [in] IRQn Interrupt number.
2554 \return Interrupt Priority.
2555 Value is aligned automatically to the implemented priority bits of the microcontroller.
2556 */
__NVIC_GetPriority(IRQn_Type IRQn)2557 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2558 {
2559
2560 if ((int32_t)(IRQn) >= 0)
2561 {
2562 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2563 }
2564 else
2565 {
2566 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2567 }
2568 }
2569
2570
2571 /**
2572 \brief Encode Priority
2573 \details Encodes the priority for an interrupt with the given priority group,
2574 preemptive priority value, and subpriority value.
2575 In case of a conflict between priority grouping and available
2576 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2577 \param [in] PriorityGroup Used priority group.
2578 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2579 \param [in] SubPriority Subpriority value (starting from 0).
2580 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2581 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2582 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2583 {
2584 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2585 uint32_t PreemptPriorityBits;
2586 uint32_t SubPriorityBits;
2587
2588 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2589 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2590
2591 return (
2592 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2593 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2594 );
2595 }
2596
2597
2598 /**
2599 \brief Decode Priority
2600 \details Decodes an interrupt priority value with a given priority group to
2601 preemptive priority value and subpriority value.
2602 In case of a conflict between priority grouping and available
2603 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2604 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2605 \param [in] PriorityGroup Used priority group.
2606 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2607 \param [out] pSubPriority Subpriority value (starting from 0).
2608 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2609 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2610 {
2611 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2612 uint32_t PreemptPriorityBits;
2613 uint32_t SubPriorityBits;
2614
2615 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2616 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2617
2618 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2619 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2620 }
2621
2622
2623 /**
2624 \brief Set Interrupt Vector
2625 \details Sets an interrupt vector in SRAM based interrupt vector table.
2626 The interrupt number can be positive to specify a device specific interrupt,
2627 or negative to specify a processor exception.
2628 VTOR must been relocated to SRAM before.
2629 \param [in] IRQn Interrupt number
2630 \param [in] vector Address of interrupt handler function
2631 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2632 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2633 {
2634 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2635 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2636 __DSB();
2637 }
2638
2639
2640 /**
2641 \brief Get Interrupt Vector
2642 \details Reads an interrupt vector from interrupt vector table.
2643 The interrupt number can be positive to specify a device specific interrupt,
2644 or negative to specify a processor exception.
2645 \param [in] IRQn Interrupt number.
2646 \return Address of interrupt handler function
2647 */
__NVIC_GetVector(IRQn_Type IRQn)2648 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2649 {
2650 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2651 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2652 }
2653
2654
2655 /**
2656 \brief System Reset
2657 \details Initiates a system reset request to reset the MCU.
2658 */
__NVIC_SystemReset(void)2659 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2660 {
2661 __DSB(); /* Ensure all outstanding memory accesses included
2662 buffered write are completed before reset */
2663 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2664 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2665 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2666 __DSB(); /* Ensure completion of memory access */
2667
2668 for(;;) /* wait until reset */
2669 {
2670 __NOP();
2671 }
2672 }
2673
2674 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2675 /**
2676 \brief Set Priority Grouping (non-secure)
2677 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2678 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2679 Only values from 0..7 are used.
2680 In case of a conflict between priority grouping and available
2681 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2682 \param [in] PriorityGroup Priority grouping field.
2683 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2684 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2685 {
2686 uint32_t reg_value;
2687 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2688
2689 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2690 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2691 reg_value = (reg_value |
2692 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2693 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2694 SCB_NS->AIRCR = reg_value;
2695 }
2696
2697
2698 /**
2699 \brief Get Priority Grouping (non-secure)
2700 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2701 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2702 */
TZ_NVIC_GetPriorityGrouping_NS(void)2703 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2704 {
2705 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2706 }
2707
2708
2709 /**
2710 \brief Enable Interrupt (non-secure)
2711 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2712 \param [in] IRQn Device specific interrupt number.
2713 \note IRQn must not be negative.
2714 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2715 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2716 {
2717 if ((int32_t)(IRQn) >= 0)
2718 {
2719 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2720 }
2721 }
2722
2723
2724 /**
2725 \brief Get Interrupt Enable status (non-secure)
2726 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2727 \param [in] IRQn Device specific interrupt number.
2728 \return 0 Interrupt is not enabled.
2729 \return 1 Interrupt is enabled.
2730 \note IRQn must not be negative.
2731 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2732 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2733 {
2734 if ((int32_t)(IRQn) >= 0)
2735 {
2736 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2737 }
2738 else
2739 {
2740 return(0U);
2741 }
2742 }
2743
2744
2745 /**
2746 \brief Disable Interrupt (non-secure)
2747 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2748 \param [in] IRQn Device specific interrupt number.
2749 \note IRQn must not be negative.
2750 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2751 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2752 {
2753 if ((int32_t)(IRQn) >= 0)
2754 {
2755 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2756 }
2757 }
2758
2759
2760 /**
2761 \brief Get Pending Interrupt (non-secure)
2762 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2763 \param [in] IRQn Device specific interrupt number.
2764 \return 0 Interrupt status is not pending.
2765 \return 1 Interrupt status is pending.
2766 \note IRQn must not be negative.
2767 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2768 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2769 {
2770 if ((int32_t)(IRQn) >= 0)
2771 {
2772 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2773 }
2774 else
2775 {
2776 return(0U);
2777 }
2778 }
2779
2780
2781 /**
2782 \brief Set Pending Interrupt (non-secure)
2783 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2784 \param [in] IRQn Device specific interrupt number.
2785 \note IRQn must not be negative.
2786 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2787 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2788 {
2789 if ((int32_t)(IRQn) >= 0)
2790 {
2791 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2792 }
2793 }
2794
2795
2796 /**
2797 \brief Clear Pending Interrupt (non-secure)
2798 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2799 \param [in] IRQn Device specific interrupt number.
2800 \note IRQn must not be negative.
2801 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2802 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2803 {
2804 if ((int32_t)(IRQn) >= 0)
2805 {
2806 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2807 }
2808 }
2809
2810
2811 /**
2812 \brief Get Active Interrupt (non-secure)
2813 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2814 \param [in] IRQn Device specific interrupt number.
2815 \return 0 Interrupt status is not active.
2816 \return 1 Interrupt status is active.
2817 \note IRQn must not be negative.
2818 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2819 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2820 {
2821 if ((int32_t)(IRQn) >= 0)
2822 {
2823 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2824 }
2825 else
2826 {
2827 return(0U);
2828 }
2829 }
2830
2831
2832 /**
2833 \brief Set Interrupt Priority (non-secure)
2834 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2835 The interrupt number can be positive to specify a device specific interrupt,
2836 or negative to specify a processor exception.
2837 \param [in] IRQn Interrupt number.
2838 \param [in] priority Priority to set.
2839 \note The priority cannot be set for every non-secure processor exception.
2840 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2841 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2842 {
2843 if ((int32_t)(IRQn) >= 0)
2844 {
2845 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2846 }
2847 else
2848 {
2849 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2850 }
2851 }
2852
2853
2854 /**
2855 \brief Get Interrupt Priority (non-secure)
2856 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2857 The interrupt number can be positive to specify a device specific interrupt,
2858 or negative to specify a processor exception.
2859 \param [in] IRQn Interrupt number.
2860 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2861 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2862 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2863 {
2864
2865 if ((int32_t)(IRQn) >= 0)
2866 {
2867 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2868 }
2869 else
2870 {
2871 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2872 }
2873 }
2874 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2875
2876 /** @} end of CMSIS_Core_NVICFunctions */
2877
2878 /* ########################## MPU functions #################################### */
2879
2880 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2881
2882 #include "mpu_armv8.h"
2883
2884 #endif
2885
2886 /* ########################## FPU functions #################################### */
2887 /**
2888 \ingroup CMSIS_Core_FunctionInterface
2889 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2890 \brief Function that provides FPU type.
2891 @{
2892 */
2893
2894 /**
2895 \brief get FPU type
2896 \details returns the FPU type
2897 \returns
2898 - \b 0: No FPU
2899 - \b 1: Single precision FPU
2900 - \b 2: Double + Single precision FPU
2901 */
SCB_GetFPUType(void)2902 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2903 {
2904 uint32_t mvfr0;
2905
2906 mvfr0 = FPU->MVFR0;
2907 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2908 {
2909 return 2U; /* Double + Single precision FPU */
2910 }
2911 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2912 {
2913 return 1U; /* Single precision FPU */
2914 }
2915 else
2916 {
2917 return 0U; /* No FPU */
2918 }
2919 }
2920
2921
2922 /** @} end of CMSIS_Core_FpuFunctions */
2923
2924
2925 /* ########################## Cache functions #################################### */
2926
2927 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2928 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2929 #include "cachel1_armv7.h"
2930 #endif
2931
2932
2933 /* ########################## SAU functions #################################### */
2934 /**
2935 \ingroup CMSIS_Core_FunctionInterface
2936 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2937 \brief Functions that configure the SAU.
2938 @{
2939 */
2940
2941 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2942
2943 /**
2944 \brief Enable SAU
2945 \details Enables the Security Attribution Unit (SAU).
2946 */
TZ_SAU_Enable(void)2947 __STATIC_INLINE void TZ_SAU_Enable(void)
2948 {
2949 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2950 }
2951
2952
2953
2954 /**
2955 \brief Disable SAU
2956 \details Disables the Security Attribution Unit (SAU).
2957 */
TZ_SAU_Disable(void)2958 __STATIC_INLINE void TZ_SAU_Disable(void)
2959 {
2960 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2961 }
2962
2963 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2964
2965 /** @} end of CMSIS_Core_SAUFunctions */
2966
2967
2968
2969
2970 /* ################################## Debug Control function ############################################ */
2971 /**
2972 \ingroup CMSIS_Core_FunctionInterface
2973 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2974 \brief Functions that access the Debug Control Block.
2975 @{
2976 */
2977
2978
2979 /**
2980 \brief Set Debug Authentication Control Register
2981 \details writes to Debug Authentication Control register.
2982 \param [in] value value to be writen.
2983 */
DCB_SetAuthCtrl(uint32_t value)2984 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2985 {
2986 __DSB();
2987 __ISB();
2988 DCB->DAUTHCTRL = value;
2989 __DSB();
2990 __ISB();
2991 }
2992
2993
2994 /**
2995 \brief Get Debug Authentication Control Register
2996 \details Reads Debug Authentication Control register.
2997 \return Debug Authentication Control Register.
2998 */
DCB_GetAuthCtrl(void)2999 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3000 {
3001 return (DCB->DAUTHCTRL);
3002 }
3003
3004
3005 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3006 /**
3007 \brief Set Debug Authentication Control Register (non-secure)
3008 \details writes to non-secure Debug Authentication Control register when in secure state.
3009 \param [in] value value to be writen
3010 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)3011 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3012 {
3013 __DSB();
3014 __ISB();
3015 DCB_NS->DAUTHCTRL = value;
3016 __DSB();
3017 __ISB();
3018 }
3019
3020
3021 /**
3022 \brief Get Debug Authentication Control Register (non-secure)
3023 \details Reads non-secure Debug Authentication Control register when in secure state.
3024 \return Debug Authentication Control Register.
3025 */
TZ_DCB_GetAuthCtrl_NS(void)3026 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3027 {
3028 return (DCB_NS->DAUTHCTRL);
3029 }
3030 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3031
3032 /** @} end of CMSIS_Core_DCBFunctions */
3033
3034
3035
3036
3037 /* ################################## Debug Identification function ############################################ */
3038 /**
3039 \ingroup CMSIS_Core_FunctionInterface
3040 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
3041 \brief Functions that access the Debug Identification Block.
3042 @{
3043 */
3044
3045
3046 /**
3047 \brief Get Debug Authentication Status Register
3048 \details Reads Debug Authentication Status register.
3049 \return Debug Authentication Status Register.
3050 */
DIB_GetAuthStatus(void)3051 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3052 {
3053 return (DIB->DAUTHSTATUS);
3054 }
3055
3056
3057 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3058 /**
3059 \brief Get Debug Authentication Status Register (non-secure)
3060 \details Reads non-secure Debug Authentication Status register when in secure state.
3061 \return Debug Authentication Status Register.
3062 */
TZ_DIB_GetAuthStatus_NS(void)3063 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3064 {
3065 return (DIB_NS->DAUTHSTATUS);
3066 }
3067 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3068
3069 /** @} end of CMSIS_Core_DCBFunctions */
3070
3071
3072
3073
3074 /* ################################## SysTick function ############################################ */
3075 /**
3076 \ingroup CMSIS_Core_FunctionInterface
3077 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
3078 \brief Functions that configure the System.
3079 @{
3080 */
3081
3082 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3083
3084 /**
3085 \brief System Tick Configuration
3086 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
3087 Counter is in free running mode to generate periodic interrupts.
3088 \param [in] ticks Number of ticks between two interrupts.
3089 \return 0 Function succeeded.
3090 \return 1 Function failed.
3091 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3092 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
3093 must contain a vendor-specific implementation of this function.
3094 */
SysTick_Config(uint32_t ticks)3095 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3096 {
3097 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3098 {
3099 return (1UL); /* Reload value impossible */
3100 }
3101
3102 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3103 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3104 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3105 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3106 SysTick_CTRL_TICKINT_Msk |
3107 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3108 return (0UL); /* Function successful */
3109 }
3110
3111 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3112 /**
3113 \brief System Tick Configuration (non-secure)
3114 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
3115 Counter is in free running mode to generate periodic interrupts.
3116 \param [in] ticks Number of ticks between two interrupts.
3117 \return 0 Function succeeded.
3118 \return 1 Function failed.
3119 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3120 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
3121 must contain a vendor-specific implementation of this function.
3122
3123 */
TZ_SysTick_Config_NS(uint32_t ticks)3124 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3125 {
3126 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3127 {
3128 return (1UL); /* Reload value impossible */
3129 }
3130
3131 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3132 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3133 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3134 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3135 SysTick_CTRL_TICKINT_Msk |
3136 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3137 return (0UL); /* Function successful */
3138 }
3139 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3140
3141 #endif
3142
3143 /** @} end of CMSIS_Core_SysTickFunctions */
3144
3145
3146
3147 /* ##################################### Debug In/Output function ########################################### */
3148 /**
3149 \ingroup CMSIS_Core_FunctionInterface
3150 \defgroup CMSIS_core_DebugFunctions ITM Functions
3151 \brief Functions that access the ITM debug interface.
3152 @{
3153 */
3154
3155 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
3156 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
3157
3158
3159 /**
3160 \brief ITM Send Character
3161 \details Transmits a character via the ITM channel 0, and
3162 \li Just returns when no debugger is connected that has booked the output.
3163 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
3164 \param [in] ch Character to transmit.
3165 \returns Character to transmit.
3166 */
ITM_SendChar(uint32_t ch)3167 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3168 {
3169 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3170 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3171 {
3172 while (ITM->PORT[0U].u32 == 0UL)
3173 {
3174 __NOP();
3175 }
3176 ITM->PORT[0U].u8 = (uint8_t)ch;
3177 }
3178 return (ch);
3179 }
3180
3181
3182 /**
3183 \brief ITM Receive Character
3184 \details Inputs a character via the external variable \ref ITM_RxBuffer.
3185 \return Received character.
3186 \return -1 No character pending.
3187 */
ITM_ReceiveChar(void)3188 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3189 {
3190 int32_t ch = -1; /* no character available */
3191
3192 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3193 {
3194 ch = ITM_RxBuffer;
3195 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3196 }
3197
3198 return (ch);
3199 }
3200
3201
3202 /**
3203 \brief ITM Check Character
3204 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
3205 \return 0 No character available.
3206 \return 1 Character available.
3207 */
ITM_CheckChar(void)3208 __STATIC_INLINE int32_t ITM_CheckChar (void)
3209 {
3210
3211 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3212 {
3213 return (0); /* no character available */
3214 }
3215 else
3216 {
3217 return (1); /* character available */
3218 }
3219 }
3220
3221 /** @} end of CMSIS_core_DebugFunctions */
3222
3223
3224
3225
3226 #ifdef __cplusplus
3227 }
3228 #endif
3229
3230 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
3231
3232 #endif /* __CMSIS_GENERIC */
3233