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Searched refs:CCSIDR (Results 1 – 11 of 11) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
Dcachel1_armv7.h153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
225 locals.ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
259 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
294 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
329 ccsidr = SCB->CCSIDR; in SCB_CleanInvalidateDCache()
Dcore_starmc1.h557 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
3197 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
3238 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
3273 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
3308 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
3343 ccsidr = SCB->CCSIDR; in SCB_CleanInvalidateDCache()
Dcore_cm7.h496 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
Dcore_armv8mml.h550 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
Dcore_cm35p.h550 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
Dcore_cm33.h550 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
Dcore_armv81mml.h557 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
Dcore_cm85.h577 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
Dcore_cm55.h560 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64.td252 "Enable v8.3-A Extend of the CCSIDR number of sets">;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc219 …{ "ccidx", "Enable v8.3-A Extend of the CCSIDR number of sets", AArch64::FeatureCCIDX, { { { 0x0UL…