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Searched refs:IR3_REG_IMMED (Results 1 – 19 of 19) sorted by relevance

/third_party/mesa3d/src/freedreno/isa/
Dencode.c104 if (src->flags & IR3_REG_IMMED) { in __instruction_case()
151 assert(reg->flags & IR3_REG_IMMED); in extract_reg_iim()
158 assert(reg->flags & IR3_REG_IMMED); in extract_reg_uim()
227 if (ssbo->flags & IR3_REG_IMMED) { in extract_cat6_DESC_MODE()
266 if (reg->flags & IR3_REG_IMMED) { in __multisrc_case()
304 } else if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)) { in __cat3_src_case()
/third_party/mesa3d/src/freedreno/ir3/
Dir3_cp.c104 (cmp->srcs[1]->flags & IR3_REG_IMMED) && in is_foldable_double_cmp()
140 *dstflags |= srcflags & IR3_REG_IMMED; in combine_flags()
163 if (!(new_flags & IR3_REG_IMMED)) in lower_immed()
166 new_flags &= ~IR3_REG_IMMED; in lower_immed()
290 if (new_flags & IR3_REG_IMMED) { in try_swap_mad_two_srcs()
291 new_flags &= ~IR3_REG_IMMED; in try_swap_mad_two_srcs()
475 if (src_reg->flags & IR3_REG_IMMED) { in reg_cp()
592 if (instr->opc == OPC_MOV && (instr->srcs[0]->flags & IR3_REG_IMMED) && in instr_cp()
656 if ((samp->flags & IR3_REG_IMMED) && (tex->flags & IR3_REG_IMMED) && in instr_cp()
Dir3.c93 if (reg->flags & IR3_REG_IMMED) { in collect_reg_info()
854 flags &= (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS | in cp_flags()
902 if (flags & ~(IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_SHARED)) in ir3_valid_flags()
927 IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV | IR3_REG_SHARED; in ir3_valid_flags()
934 IR3_REG_RELATIV | IR3_REG_IMMED | IR3_REG_SHARED; in ir3_valid_flags()
941 n == 1 && flags == IR3_REG_IMMED) in ir3_valid_flags()
944 if (flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_SHARED)) { in ir3_valid_flags()
954 if ((flags & IR3_REG_IMMED) && reg->flags & (IR3_REG_IMMED)) in ir3_valid_flags()
969 valid_flags |= IR3_REG_IMMED; in ir3_valid_flags()
1002 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) in ir3_valid_flags()
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Dir3_parser.y1101 cat6_imm_offset: offset { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
1112 new_src(0, IR3_REG_IMMED)->uim_val = 0;
1113 new_src(0, IR3_REG_IMMED)->uim_val = $4;
1117 new_src(0, IR3_REG_IMMED)->uim_val = $5 - 2;
1118 new_src(0, IR3_REG_IMMED)->uim_val = $6;
1127 new_src(0, IR3_REG_IMMED)->iim_val = $8;
1211 | integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
1247 stc_dst: integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
1248 | T_A1 { new_src(0, IR3_REG_IMMED)->iim_val = 0; instr->flags |= IR3_INSTR_A1EN; }
1249 | T_A1 '+' integer { new_src(0, IR3_REG_IMMED)->iim_val = $3; instr->flags |= IR3_I…
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Dir3_lower_parallelcopy.c53 if (reg->flags & IR3_REG_IMMED) { in get_copy_src()
55 .flags = IR3_REG_IMMED, in get_copy_src()
245 ir3_src_create(shr, 0, IR3_REG_IMMED)->uim_val = 16; in do_copy()
263 if (entry->src.flags & IR3_REG_IMMED) in do_copy()
299 assert(!(entry->src.flags & (IR3_REG_IMMED | IR3_REG_CONST))); in split_32bit_copy()
379 !(entry->src.flags & (IR3_REG_IMMED | IR3_REG_CONST))) { in _handle_copies()
Dir3_cse.c51 } else if (src->flags & IR3_REG_IMMED) { in hash_instr()
98 } else if (i1_reg->flags & IR3_REG_IMMED) { in instrs_equal()
Dir3_delay.c274 if (src->flags & (IR3_REG_IMMED | IR3_REG_CONST)) in delay_calc()
332 if (!(src->flags & (IR3_REG_IMMED | IR3_REG_CONST))) in ir3_delay_calc()
Dir3_lower_spill.c59 ir3_src_create(mov, INVALID_REG, IR3_REG_IMMED)->uim_val = val; in set_base_reg()
78 ir3_src_create(mov, INVALID_REG, IR3_REG_IMMED)->uim_val = 0; in reset_base_reg()
Dir3_spill.c341 if (!(reg->instr->srcs[0]->flags & (IR3_REG_IMMED | IR3_REG_CONST))) in can_rematerialize()
692 if (val->flags & IR3_REG_IMMED) { in set_src_val()
693 src->flags = IR3_REG_IMMED | (val->flags & IR3_REG_HALF); in set_src_val()
733 if (val->flags & (IR3_REG_CONST | IR3_REG_IMMED)) { in spill()
747 unsigned src_flags = reg->flags & (IR3_REG_HALF | IR3_REG_IMMED | in spill()
751 ir3_src_create(spill, INVALID_REG, IR3_REG_IMMED)->uim_val = elems; in spill()
922 ir3_src_create(reload, INVALID_REG, IR3_REG_IMMED); in reload()
924 ir3_src_create(reload, INVALID_REG, IR3_REG_IMMED)->uim_val = elems; in reload()
1268 assert(src->flags & (IR3_REG_CONST | IR3_REG_IMMED)); in handle_pcopy()
1548 if ((pred_val->flags & (IR3_REG_IMMED | IR3_REG_CONST)) || in add_live_in_phi()
Dir3_legalize.c160 assert(inloc->flags & IR3_REG_IMMED); in legalize_block()
319 ir3_src_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0; in legalize_block()
349 ir3_src_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0; in legalize_block()
Dir3_postsched.c461 if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)) in calculate_deps()
714 (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_FNEG | in is_self_mov()
Dir3_lower_subgroups.c67 mov, INVALID_REG, (dst->flags & IR3_REG_HALF) | IR3_REG_IMMED); in mov_immed()
Dir3_validate.c75 if (reg->flags & IR3_REG_IMMED) in validate_src()
Dir3_ra_validate.c295 if (src->flags & (IR3_REG_IMMED | IR3_REG_CONST)) { in propagate_parallelcopy()
Dir3_print.c308 if (reg->flags & IR3_REG_IMMED) { in print_reg_name()
Dir3.h105 IR3_REG_IMMED = 0x002, enumerator
1259 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED)) in reg_gpr()
1938 ir3_src_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val; in create_immed_typed()
Dir3_sched.c250 if (src->flags & (IR3_REG_IMMED | IR3_REG_CONST)) in cycle_count()
Dir3_compiler_nir.c951 if (is_same_type_mov(src0) && (src0->srcs[0]->flags & IR3_REG_IMMED)) { in emit_intrinsic_load_ubo()
1028 if (is_same_type_mov(src0) && (src0->srcs[0]->flags & IR3_REG_IMMED)) { in emit_intrinsic_load_kernel_input()
4023 compile_assert(ctx, instr->srcs[0]->flags & IR3_REG_IMMED); in pack_inlocs()
/third_party/mesa3d/src/freedreno/ir3/tests/
Ddelay.c137 if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)) in fixup_wrmask()