1 /*
2 * Copyright (C) 2014 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #define XXH_INLINE_ALL
27 #include "xxhash.h"
28
29 /* This pass handles CSE'ing repeated expressions created in the process of
30 * translating from NIR. Currently this is just collect's. Also, currently
31 * this is intra-block only, to make it work over multiple block we'd need to
32 * bring forward dominance calculation.
33 */
34
35 #define HASH(hash, data) XXH32(&(data), sizeof(data), hash)
36
37 static uint32_t
hash_instr(const void * data)38 hash_instr(const void *data)
39 {
40 const struct ir3_instruction *instr = data;
41 uint32_t hash = 0;
42
43 hash = HASH(hash, instr->opc);
44 hash = HASH(hash, instr->dsts[0]->flags);
45 foreach_src (src, (struct ir3_instruction *)instr) {
46 if (src->flags & IR3_REG_CONST) {
47 if (src->flags & IR3_REG_RELATIV)
48 hash = HASH(hash, src->array.offset);
49 else
50 hash = HASH(hash, src->num);
51 } else if (src->flags & IR3_REG_IMMED) {
52 hash = HASH(hash, src->uim_val);
53 } else {
54 if (src->flags & IR3_REG_ARRAY)
55 hash = HASH(hash, src->array.offset);
56 hash = HASH(hash, src->def);
57 }
58 }
59
60 if (opc_cat(instr->opc) == 1) {
61 hash = HASH(hash, instr->cat1.dst_type);
62 hash = HASH(hash, instr->cat1.src_type);
63 hash = HASH(hash, instr->cat1.round);
64 }
65
66 return hash;
67 }
68
69 static bool
instrs_equal(const struct ir3_instruction * i1,const struct ir3_instruction * i2)70 instrs_equal(const struct ir3_instruction *i1, const struct ir3_instruction *i2)
71 {
72 if (i1->opc != i2->opc)
73 return false;
74
75 if (i1->dsts_count != i2->dsts_count)
76 return false;
77
78 if (i1->srcs_count != i2->srcs_count)
79 return false;
80
81 if (i1->dsts[0]->flags != i2->dsts[0]->flags)
82 return false;
83
84 for (unsigned i = 0; i < i1->srcs_count; i++) {
85 const struct ir3_register *i1_reg = i1->srcs[i], *i2_reg = i2->srcs[i];
86
87 if (i1_reg->flags != i2_reg->flags)
88 return false;
89
90 if (i1_reg->flags & IR3_REG_CONST) {
91 if (i1_reg->flags & IR3_REG_RELATIV) {
92 if (i1_reg->array.offset != i2_reg->array.offset)
93 return false;
94 } else {
95 if (i1_reg->num != i2_reg->num)
96 return false;
97 }
98 } else if (i1_reg->flags & IR3_REG_IMMED) {
99 if (i1_reg->uim_val != i2_reg->uim_val)
100 return false;
101 } else {
102 if (i1_reg->flags & IR3_REG_ARRAY) {
103 if (i1_reg->array.offset != i2_reg->array.offset)
104 return false;
105 }
106 if (i1_reg->def != i2_reg->def)
107 return false;
108 }
109 }
110
111 if (opc_cat(i1->opc) == 1) {
112 if (i1->cat1.dst_type != i2->cat1.dst_type ||
113 i1->cat1.src_type != i2->cat1.src_type ||
114 i1->cat1.round != i2->cat1.round)
115 return false;
116 }
117
118 return true;
119 }
120
121 static bool
instr_can_cse(const struct ir3_instruction * instr)122 instr_can_cse(const struct ir3_instruction *instr)
123 {
124 if (instr->opc != OPC_META_COLLECT && instr->opc != OPC_MOV)
125 return false;
126
127 if (!is_dest_gpr(instr->dsts[0]) || (instr->dsts[0]->flags & IR3_REG_ARRAY))
128 return false;
129
130 return true;
131 }
132
133 static bool
cmp_func(const void * data1,const void * data2)134 cmp_func(const void *data1, const void *data2)
135 {
136 return instrs_equal(data1, data2);
137 }
138
139 bool
ir3_cse(struct ir3 * ir)140 ir3_cse(struct ir3 *ir)
141 {
142 struct set *instr_set = _mesa_set_create(NULL, hash_instr, cmp_func);
143 foreach_block (block, &ir->block_list) {
144 _mesa_set_clear(instr_set, NULL);
145
146 foreach_instr (instr, &block->instr_list) {
147 instr->data = NULL;
148
149 if (!instr_can_cse(instr))
150 continue;
151
152 bool found;
153 struct set_entry *entry =
154 _mesa_set_search_or_add(instr_set, instr, &found);
155 if (found)
156 instr->data = (void *)entry->key;
157 }
158 }
159
160 bool progress = false;
161 foreach_block (block, &ir->block_list) {
162 foreach_instr (instr, &block->instr_list) {
163 foreach_src (src, instr) {
164 if ((src->flags & IR3_REG_SSA) && src->def &&
165 src->def->instr->data) {
166 progress = true;
167 struct ir3_instruction *instr = src->def->instr->data;
168 src->def = instr->dsts[0];
169 }
170 }
171 }
172 }
173
174 _mesa_set_destroy(instr_set, NULL);
175 return progress;
176 }
177