| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 63 MIMG = 11 variable in Format
119 elif self == Format.MIMG:
1414 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1416 opcode("image_msaa_load", -1, -1, 0x80, Format.MIMG, InstrClass.VMem) #GFX10.3+
1440 opcode(name, gfx7, gfx89, gfx7, Format.MIMG, InstrClass.VMem, is_atomic = True)
1486 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1501 opcode(name, -1, -1, code, Format.MIMG, InstrClass.VMem)
1534 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1536 opcode("image_bvh64_intersect_ray", -1, -1, 231, Format.MIMG, InstrClass.VMem)
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| D | aco_opt_value_numbering.cpp | 107 case Format::MIMG: return hash_murmur_32<MIMG_instruction>(instr); in operator ()()
267 case Format::MIMG: { in operator ()()
349 case Format::MIMG: in can_eliminate()
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| D | README-ISA.md | 88 ## MIMG opcodes on GFX8/GCN3
286 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
290 NSA MIMG instructions should be limited to 3 dwords before GFX10.3 to avoid
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| D | aco_insert_waitcnt.cpp | 686 case Format::MIMG: in gen()
696 if (ctx.gfx_level == GFX6 && instr->format != Format::MIMG && instr->operands.size() == 4) { in gen()
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| D | aco_register_allocation.cpp | 1555 unsigned first_operand = vec->format == Format::MIMG ? 3 : 0; in get_reg_vector()
1565 if (vec->format != Format::MIMG || is_mimg_vaddr_intact(ctx, reg_file, vec)) { in get_reg_vector()
1581 if (vec->format == Format::MIMG) in get_reg_vector()
2389 } else if (instr->format == Format::MIMG && instr->operands.size() > 4) { in get_affinities()
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| D | aco_ir.h | 84 MIMG = 11, enumerator
1159 constexpr bool isMIMG() const noexcept { return format == Format::MIMG; } in isMIMG()
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| D | aco_ir.cpp | 192 case Format::MIMG: return instr->mimg().sync; in get_sync_info()
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| D | aco_print_ir.cpp | 391 case Format::MIMG: { in print_instr_format_specific()
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| D | aco_assembler.cpp | 450 case Format::MIMG: { in emit_instruction()
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| D | aco_validate.cpp | 610 case Format::MIMG: { in validate_ir()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 1 //===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===//
9 // MIMG-specific encoding families to distinguish between semantically
125 let MIMG = 1;
138 class MIMG <dag outs, string dns = "">
152 let FilterClass = "MIMG";
182 // Base class of all pre-gfx10 MIMG instructions.
184 : MIMG<outs, dns>, MIMGe_gfx6789<op> {
193 // Base class of all non-NSA gfx10 MIMG instructions.
195 : MIMG<outs, dns>, MIMGe_gfx10<op> {
205 // Base class for all NSA MIMG instructions. Note that 1-dword addresses always
[all …]
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| D | SILoadStoreOptimizer.cpp | 101 MIMG, enumerator
336 return MIMG; in getInstClass()
496 if (InstClass == MIMG) { in setMI()
510 } else if (InstClass != MIMG) { in setMI()
662 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
724 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
915 CI.InstClass == MIMG in findMatchingInst()
1439 case MIMG: in getNewOpcode()
1452 if (CI.InstClass == MIMG) { in getSubRegIdxs()
2025 case MIMG: { in optimizeInstsWithSameBaseAddr()
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| D | SIInstrFormats.td | 41 field bit MIMG = 0;
153 let TSFlags{19} = MIMG;
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| D | SIDefines.h | 48 MIMG = 1 << 19, enumerator
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| D | SIInstrInfo.h | 482 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
486 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| D | AMDGPU.td | 202 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
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| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_insert_nops.cpp | 37 aco_opcode::image_sample, Format::MIMG, 3 + addrs, 1)}; in create_mimg()
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| D | test_hard_clause.cpp | 71 aco_opcode::image_sample, Format::MIMG, 5, 1)}; in create_mimg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 294 if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2946 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDataSize()
2978 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10()) in validateMIMGAddrSize()
3019 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGAtomicDMask()
3093 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGD16()
3109 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDim()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 373 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { in getInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 497 bit DA = 0; // DA bit in MIMG encoding
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.0.0.rst | 2790 - aco: move MIMG VDATA to its own operand
3070 - aco: fix inserting expcnt for MIMG on GFX6
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| D | 22.2.0.rst | 2275 - aco: Print r128/a16 MIMG bits separately.
2276 - aco: Remove r128_a16 MIMG builder option.
5245 - aco: avoid WAW hazard with BVH MIMG and other VMEM
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| D | 21.2.0.rst | 4834 - aco: fix emitting d16 for MIMG instructions on GFX9+
4835 - aco: fix emitting a16 for MIMG instructions on GFX10+
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