Searched refs:csio (Results 1 – 2 of 2) sorted by relevance
256 struct ccb_scsiio csio; member1089 …sc->data_ccb->csio.data_ptr = (uint8_t *)memalign(USB_CACHE_ALIGN_SIZE, SKB_DATA_ALIGN(SOFT_CACHE_… in umass_attach()1090 if (sc->data_ccb->csio.data_ptr == NULL) in umass_attach()1092 sc->data_ccb->csio.dxfer_len = SOFT_CACHE_SIZE; in umass_attach()1129 if (sc->data_ccb->csio.data_ptr != NULL) { in umass_detach()1130 free((void*)sc->data_ccb->csio.data_ptr); in umass_detach()1131 sc->data_ccb->csio.data_ptr = NULL; in umass_detach()2152 umass_ccb->csio.resid = residue; in umass_cam_cb()2153 umass_ccb->csio.status = status; in umass_cam_cb()2703 status = sc->data_ccb->csio.status; in umass_test_unit_ready()[all …]
906 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf) in gfx6_surface_settings() argument908 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign); in gfx6_surface_settings()909 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1; in gfx6_surface_settings()913 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_surface_settings()914 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()915 surf->u.legacy.bankh = csio->pTileInfo->bankHeight; in gfx6_surface_settings()916 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio; in gfx6_surface_settings()917 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes; in gfx6_surface_settings()918 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings()919 surf->u.legacy.macro_tile_index = csio->macroModeIndex; in gfx6_surface_settings()[all …]