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Searched refs:pm4 (Results 1 – 20 of 20) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c30 static void si_build_load_reg(struct si_screen *sscreen, struct si_pm4_state *pm4, in si_build_load_reg() argument
59 si_pm4_cmd_add(pm4, PKT3(packet, 1 + num_ranges * 2, 0)); in si_build_load_reg()
60 si_pm4_cmd_add(pm4, gpu_address); in si_build_load_reg()
61 si_pm4_cmd_add(pm4, gpu_address >> 32); in si_build_load_reg()
63 si_pm4_cmd_add(pm4, (ranges[i].offset - offset) / 4); in si_build_load_reg()
64 si_pm4_cmd_add(pm4, ranges[i].size / 4); in si_build_load_reg()
72 struct si_pm4_state pm4; in si_create_shadowing_ib_preamble() member
75 struct si_pm4_state *pm4 = (struct si_pm4_state *)CALLOC_STRUCT(si_shadow_preamble); in si_create_shadowing_ib_preamble() local
78 pm4->max_dw = sizeof(struct si_shadow_preamble) - offsetof(struct si_shadow_preamble, pm4.pm4); in si_create_shadowing_ib_preamble()
81 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
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Dsi_state.c444 struct si_pm4_state *pm4 = &blend->pm4; in si_create_blend_state_mode() local
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
482 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
523 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
533 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
599 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
636 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]); in si_create_blend_state_mode()
643 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); in si_create_blend_state_mode()
934 struct si_pm4_state *pm4 = &rs->pm4; in si_create_rs_state() local
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Dsi_pm4.c33 state->max_dw = ARRAY_SIZE(state->pm4); in si_pm4_cmd_begin()
43 state->max_dw = ARRAY_SIZE(state->pm4); in si_pm4_cmd_add()
45 state->pm4[state->ndw++] = dw; in si_pm4_cmd_add()
53 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate); in si_pm4_cmd_end()
62 state->max_dw = ARRAY_SIZE(state->pm4); in si_pm4_set_reg_custom()
68 state->pm4[state->ndw++] = reg | (idx << 28); in si_pm4_set_reg_custom()
73 state->pm4[state->ndw++] = val; in si_pm4_set_reg_custom()
147 radeon_emit_array(state->pm4, state->ndw); in si_pm4_emit()
Dsi_state_shaders.cpp611 si_pm4_clear_state(&shader->pm4); in si_get_shader_pm4_state()
612 shader->pm4.is_shader = true; in si_get_shader_pm4_state()
613 return &shader->pm4; in si_get_shader_pm4_state()
685 struct si_pm4_state *pm4; in si_shader_ls() local
690 pm4 = si_get_shader_pm4_state(shader); in si_shader_ls()
691 if (!pm4) in si_shader_ls()
695 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); in si_shader_ls()
708 struct si_pm4_state *pm4; in si_shader_hs() local
711 pm4 = si_get_shader_pm4_state(shader); in si_shader_hs()
712 if (!pm4) in si_shader_hs()
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Dsi_pm4.h59 uint32_t pm4[64]; member
Dsi_state.h54 struct si_pm4_state pm4; member
72 struct si_pm4_state pm4; member
123 struct si_pm4_state pm4; member
Dsi_shader.h840 struct si_pm4_state pm4; /* base class */ member
Dsi_state_draw.cpp248 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index]; in si_update_shaders() local
249 if (unlikely(!*pm4)) in si_update_shaders()
250 *pm4 = si_build_vgt_shader_config(sctx->screen, key); in si_update_shaders()
251 si_pm4_bind_state(sctx, vgt_shader_config, *pm4); in si_update_shaders()
Dsi_debug.c414 ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0, in si_log_chunk_type_cs_print()
Dsi_gfx_cs.c443 ctx->ws->cs_set_preamble(&ctx->gfx_cs, preamble->pm4, preamble->ndw, in si_begin_new_gfx_cs()
/third_party/libdrm/tests/amdgpu/
Dbasic_tests.c1038 uint32_t *pm4; in amdgpu_bo_eviction_test() local
1048 pm4 = calloc(pm4_dw, sizeof(*pm4)); in amdgpu_bo_eviction_test()
1049 CU_ASSERT_NOT_EQUAL(pm4, NULL); in amdgpu_bo_eviction_test()
1124 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, in amdgpu_bo_eviction_test()
1126 pm4[i++] = 0xffffffff & bo2_mc; in amdgpu_bo_eviction_test()
1127 pm4[i++] = 0xffffffff & bo1_mc; in amdgpu_bo_eviction_test()
1128 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; in amdgpu_bo_eviction_test()
1129 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; in amdgpu_bo_eviction_test()
1131 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); in amdgpu_bo_eviction_test()
1133 pm4[i++] = sdma_write_length - 1; in amdgpu_bo_eviction_test()
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Damdgpu_stress.c144 uint32_t *pm4; variable
201 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, in submit_ib()
203 pm4[i++] = 0xffffffff & dst; in submit_ib()
204 pm4[i++] = 0xffffffff & src; in submit_ib()
205 pm4[i++] = (0xffffffff00000000 & dst) >> 32; in submit_ib()
206 pm4[i++] = (0xffffffff00000000 & src) >> 32; in submit_ib()
208 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, in submit_ib()
212 pm4[i++] = bytes - 1; in submit_ib()
214 pm4[i++] = bytes; in submit_ib()
215 pm4[i++] = 0; in submit_ib()
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/third_party/ltp/testcases/kernel/mem/mem/
Dmem02.c77 char *pm1, *pm2, *pm3, *pm4; in main() local
159 pm4 = pm3 = malloc(10); in main()
161 *pm4++ = 'X'; in main()
164 pm4 = realloc(pm3, 5); in main()
165 pm3 = pm4; in main()
168 if (*pm4++ != 'X') { in main()
177 pm4 = realloc(pm3, 15); in main()
178 pm3 = pm4; in main()
188 free(pm4); in main()
/third_party/mesa3d/src/freedreno/registers/adreno/
Dmeson.build66 'adreno-pm4-pack.xml.h',
68 output: 'adreno-pm4-pack.xml.h',
/third_party/mesa3d/src/freedreno/vulkan/
Dmsm_kgsl.h398 unsigned int pm4; member
/third_party/mesa3d/docs/relnotes/
D21.3.0.rst2613 - radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers
2675 - radeonsi: unset SI_PREFETCH_* only when we unbind pm4 shader states
D22.0.0.rst2961 - radeonsi: decrease the size of si_pm4_state::pm4 except for cs_preamble_state
2994 - radeonsi: fix register shadowing after the pm4 state size was decreased
D22.1.0.rst2261 - radeonsi: fix register shadowing after the pm4 state size was decreased
D20.2.0.rst3447 - freedreno: android: add adreno-pm4-pack.xml.h generation to android build
D21.2.0.rst4559 - freedreno/tu+drm: Extract out pm4 pkt header helpers