1 /* 2 * HND Run Time Environment ioctl. 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: rte_ioctl.h 699094 2017-05-11 22:41:10Z $ 28 */ 29 30 #ifndef _rte_ioctl_h_ 31 #define _rte_ioctl_h_ 32 33 /* RTE IOCTL definitions for generic ether devices */ 34 #define RTEGHWADDR 0x8901 35 #define RTESHWADDR 0x8902 36 #define RTEGMTU 0x8903 37 #define RTEGSTATS 0x8904 38 #define RTEGALLMULTI 0x8905 39 #define RTESALLMULTI 0x8906 40 #define RTEGPROMISC 0x8907 41 #define RTESPROMISC 0x8908 42 #define RTESMULTILIST 0x8909 43 #define RTEGUP 0x890A 44 #define RTEGPERMADDR 0x890B 45 #define RTEDEVPWRSTCHG 0x890C /* Device pwr state change for PCIedev */ 46 #define RTEDEVPMETOGGLE 0x890D /* Toggle PME# to wake up the host */ 47 #define RTEDEVTIMESYNC 0x890E /* Device TimeSync */ 48 #define RTEDEVDSNOTIFY 0x890F /* Bus DS state notification */ 49 #define RTED11DMALPBK_INIT 0x8910 /* D11 DMA loopback init */ 50 #define RTED11DMALPBK_UNINIT 0x8911 /* D11 DMA loopback uninit */ 51 #define RTED11DMALPBK_RUN 0x8912 /* D11 DMA loopback run */ 52 #define RTEDEVTSBUFPOST 0x8913 /* Async interface for tsync buffer post */ 53 54 #define RTE_IOCTL_QUERY 0x00 55 #define RTE_IOCTL_SET 0x01 56 #define RTE_IOCTL_OVL_IDX_MASK 0x1e 57 #define RTE_IOCTL_OVL_RSV 0x20 58 #define RTE_IOCTL_OVL 0x40 59 #define RTE_IOCTL_OVL_IDX_SHIFT 1 60 61 enum hnd_ioctl_cmd { 62 HND_RTE_DNGL_IS_SS = 1, /* true if device connected at super speed */ 63 64 /* PCIEDEV specific wl <--> bus ioctls */ 65 BUS_GET_VAR = 2, 66 BUS_SET_VAR = 3, 67 BUS_FLUSH_RXREORDER_Q = 4, 68 BUS_SET_LTR_STATE = 5, 69 BUS_FLUSH_CHAINED_PKTS = 6, 70 BUS_SET_COPY_COUNT = 7, 71 BUS_UPDATE_FLOW_PKTS_MAX = 8, 72 BUS_UPDATE_EXTRA_TXLFRAGS = 9, 73 BUS_UPDATE_FRWD_RESRV_BUFCNT = 10, 74 BUS_PCIE_CONFIG_ACCESS = 11 75 }; 76 77 #define SDPCMDEV_SET_MAXTXPKTGLOM 1 78 #define RTE_MEMUSEINFO_VER 0x00 79 80 typedef struct memuse_info { 81 uint16 ver; /* version of this struct */ 82 uint16 len; /* length in bytes of this structure */ 83 uint32 tot; /* Total memory */ 84 uint32 text_len; /* Size of Text segment memory */ 85 uint32 data_len; /* Size of Data segment memory */ 86 uint32 bss_len; /* Size of BSS segment memory */ 87 88 uint32 arena_size; /* Total Heap size */ 89 uint32 arena_free; /* Heap memory available or free */ 90 uint32 inuse_size; /* Heap memory currently in use */ 91 uint32 inuse_hwm; /* High watermark of memory - reclaimed memory */ 92 uint32 inuse_overhead; /* tally of allocated mem_t blocks */ 93 uint32 inuse_total; /* Heap in-use + Heap overhead memory */ 94 uint32 free_lwm; /* Least free size since reclaim */ 95 uint32 mf_count; /* Malloc failure count */ 96 } memuse_info_t; 97 98 /* For D11 DMA loopback test */ 99 typedef struct d11_dmalpbk_args { 100 uint8 *buf; 101 int32 len; 102 } d11_dmalpbk_args_t; 103 #endif /* _rte_ioctl_h_ */ 104