1/** 2 ****************************************************************************** 3 * @file startup_stm32f407xx.s 4 * @author MCD Application Team 5 * @brief STM32F407xx Devices vector table for GCC based toolchains. 6 * This module performs: 7 * - Set the initial SP 8 * - Set the initial PC == Reset_Handler, 9 * - Set the vector table entries with the exceptions ISR address 10 * - Branches to main in the C library (which eventually 11 * calls main()). 12 * After Reset the Cortex-M4 processor is in Thread mode, 13 * priority is Privileged, and the Stack is set to Main. 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 .syntax unified 29 .cpu cortex-m4 30 .fpu softvfp 31 .thumb 32 33.extern HalExcNMI; 34.extern HalExcHardFault; 35.extern HalExcMemFault; 36.extern HalExcBusFault; 37.extern HalExcUsageFault; 38.extern HalExcSvcCall; 39.extern HalPendSV; 40.extern SysTick_Handler; 41 42.global g_pfnVectors 43.global Default_Handler 44 45/* start address for the initialization values of the .data section. 46defined in linker script */ 47.word _sidata 48/* start address for the .data section. defined in linker script */ 49.word _sdata 50/* end address for the .data section. defined in linker script */ 51.word _edata 52/* start address for the .bss section. defined in linker script */ 53.word _sbss 54/* end address for the .bss section. defined in linker script */ 55.word _ebss 56/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ 57 58/** 59 * @brief This is the code that gets called when the processor first 60 * starts execution following a reset event. Only the absolutely 61 * necessary set is performed, after which the application 62 * supplied main() routine is called. 63 * @param None 64 * @retval : None 65*/ 66 67 .section .text.Reset_Handler 68 .weak Reset_Handler 69 .type Reset_Handler, %function 70Reset_Handler: 71 ldr sp, =_estack /* set stack pointer */ 72 73/* Copy the data segment initializers from flash to SRAM */ 74 ldr r0, =_sdata 75 ldr r1, =_edata 76 ldr r2, =_sidata 77 movs r3, #0 78 b LoopCopyDataInit 79 80CopyDataInit: 81 ldr r4, [r2, r3] 82 str r4, [r0, r3] 83 adds r3, r3, #4 84 85LoopCopyDataInit: 86 adds r4, r0, r3 87 cmp r4, r1 88 bcc CopyDataInit 89 90/* Zero fill the bss segment. */ 91 ldr r2, =_sbss 92 ldr r4, =_ebss 93 movs r3, #0 94 b LoopFillZerobss 95 96FillZerobss: 97 str r3, [r2] 98 adds r2, r2, #4 99 100LoopFillZerobss: 101 cmp r2, r4 102 bcc FillZerobss 103 104/* Call the clock system intitialization function.*/ 105 bl SystemInit 106/* Call static constructors */ 107 bl __libc_init_array 108/* Call the application's entry point.*/ 109 bl main 110 bx lr 111.size Reset_Handler, .-Reset_Handler 112 113/** 114 * @brief This is the code that gets called when the processor receives an 115 * unexpected interrupt. This simply enters an infinite loop, preserving 116 * the system state for examination by a debugger. 117 * @param None 118 * @retval None 119*/ 120 .section .text.Default_Handler,"ax",%progbits 121Default_Handler: 122Infinite_Loop: 123 b Infinite_Loop 124 .size Default_Handler, .-Default_Handler 125/****************************************************************************** 126* 127* The minimal vector table for a Cortex M3. Note that the proper constructs 128* must be placed on this to ensure that it ends up at physical address 129* 0x0000.0000. 130* 131*******************************************************************************/ 132 .section .isr_vector,"a",%progbits 133 .type g_pfnVectors, %object 134 .size g_pfnVectors, .-g_pfnVectors 135 136 137g_pfnVectors: 138 .word _estack 139 .word Reset_Handler 140 .word HalExcNMI 141 .word HalExcHardFault 142 .word HalExcMemFault 143 .word HalExcBusFault 144 .word HalExcUsageFault 145 .word 0 146 .word 0 147 .word 0 148 .word 0 149 .word SVC_Handler 150 .word DebugMon_Handler 151 .word 0 152 .word HalPendSV 153 .word SysTick_Handler 154 155 /* External Interrupts */ 156 .word WWDG_IRQHandler /* Window WatchDog */ 157 .word PVD_IRQHandler /* PVD through EXTI Line detection */ 158 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ 159 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ 160 .word FLASH_IRQHandler /* FLASH */ 161 .word RCC_IRQHandler /* RCC */ 162 .word EXTI0_IRQHandler /* EXTI Line0 */ 163 .word EXTI1_IRQHandler /* EXTI Line1 */ 164 .word EXTI2_IRQHandler /* EXTI Line2 */ 165 .word EXTI3_IRQHandler /* EXTI Line3 */ 166 .word EXTI4_IRQHandler /* EXTI Line4 */ 167 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ 168 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ 169 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ 170 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ 171 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ 172 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ 173 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ 174 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ 175 .word CAN1_TX_IRQHandler /* CAN1 TX */ 176 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ 177 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 178 .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 179 .word EXTI9_5_IRQHandler /* External Line[9:5]s */ 180 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ 181 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ 182 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ 183 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 184 .word TIM2_IRQHandler /* TIM2 */ 185 .word TIM3_IRQHandler /* TIM3 */ 186 .word TIM4_IRQHandler /* TIM4 */ 187 .word I2C1_EV_IRQHandler /* I2C1 Event */ 188 .word I2C1_ER_IRQHandler /* I2C1 Error */ 189 .word I2C2_EV_IRQHandler /* I2C2 Event */ 190 .word I2C2_ER_IRQHandler /* I2C2 Error */ 191 .word SPI1_IRQHandler /* SPI1 */ 192 .word SPI2_IRQHandler /* SPI2 */ 193 .word USART1_IRQHandler /* USART1 */ 194 .word USART2_IRQHandler /* USART2 */ 195 .word USART3_IRQHandler /* USART3 */ 196 .word EXTI15_10_IRQHandler /* External Line[15:10]s */ 197 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ 198 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ 199 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ 200 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ 201 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ 202 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ 203 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ 204 .word FSMC_IRQHandler /* FSMC */ 205 .word SDIO_IRQHandler /* SDIO */ 206 .word TIM5_IRQHandler /* TIM5 */ 207 .word SPI3_IRQHandler /* SPI3 */ 208 .word UART4_IRQHandler /* UART4 */ 209 .word UART5_IRQHandler /* UART5 */ 210 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ 211 .word TIM7_IRQHandler /* TIM7 */ 212 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ 213 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ 214 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ 215 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ 216 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ 217 .word ETH_IRQHandler /* Ethernet */ 218 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ 219 .word CAN2_TX_IRQHandler /* CAN2 TX */ 220 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ 221 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ 222 .word CAN2_SCE_IRQHandler /* CAN2 SCE */ 223 .word OTG_FS_IRQHandler /* USB OTG FS */ 224 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ 225 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ 226 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ 227 .word USART6_IRQHandler /* USART6 */ 228 .word I2C3_EV_IRQHandler /* I2C3 event */ 229 .word I2C3_ER_IRQHandler /* I2C3 error */ 230 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ 231 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ 232 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ 233 .word OTG_HS_IRQHandler /* USB OTG HS */ 234 .word DCMI_IRQHandler /* DCMI */ 235 .word 0 /* CRYP crypto */ 236 .word HASH_RNG_IRQHandler /* Hash and Rng */ 237 .word FPU_IRQHandler /* FPU */ 238 239 240/******************************************************************************* 241* 242* Provide weak aliases for each Exception handler to the Default_Handler. 243* As they are weak aliases, any function with the same name will override 244* this definition. 245* 246*******************************************************************************/ 247 .weak HalExcNMI 248 .thumb_set HalExcNMI,Default_Handler 249 250 .weak HalExcHardFault 251 .thumb_set HalExcHardFault,Default_Handler 252 253 .weak HalExcMemFault 254 .thumb_set HalExcMemFault,Default_Handler 255 256 .weak HalExcBusFault 257 .thumb_set HalExcBusFault,Default_Handler 258 259 .weak HalExcUsageFault 260 .thumb_set HalExcUsageFault,Default_Handler 261 262 .weak SVC_Handler 263 .thumb_set SVC_Handler,Default_Handler 264 265 .weak DebugMon_Handler 266 .thumb_set DebugMon_Handler,Default_Handler 267 268 .weak HalPendSV 269 .thumb_set HalPendSV,Default_Handler 270 271 .weak SysTick_Handler 272 .thumb_set SysTick_Handler,Default_Handler 273 274 .weak WWDG_IRQHandler 275 .thumb_set WWDG_IRQHandler,Default_Handler 276 277 .weak PVD_IRQHandler 278 .thumb_set PVD_IRQHandler,Default_Handler 279 280 .weak TAMP_STAMP_IRQHandler 281 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 282 283 .weak RTC_WKUP_IRQHandler 284 .thumb_set RTC_WKUP_IRQHandler,Default_Handler 285 286 .weak FLASH_IRQHandler 287 .thumb_set FLASH_IRQHandler,Default_Handler 288 289 .weak RCC_IRQHandler 290 .thumb_set RCC_IRQHandler,Default_Handler 291 292 .weak EXTI0_IRQHandler 293 .thumb_set EXTI0_IRQHandler,Default_Handler 294 295 .weak EXTI1_IRQHandler 296 .thumb_set EXTI1_IRQHandler,Default_Handler 297 298 .weak EXTI2_IRQHandler 299 .thumb_set EXTI2_IRQHandler,Default_Handler 300 301 .weak EXTI3_IRQHandler 302 .thumb_set EXTI3_IRQHandler,Default_Handler 303 304 .weak EXTI4_IRQHandler 305 .thumb_set EXTI4_IRQHandler,Default_Handler 306 307 .weak DMA1_Stream0_IRQHandler 308 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler 309 310 .weak DMA1_Stream1_IRQHandler 311 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler 312 313 .weak DMA1_Stream2_IRQHandler 314 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler 315 316 .weak DMA1_Stream3_IRQHandler 317 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 318 319 .weak DMA1_Stream4_IRQHandler 320 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler 321 322 .weak DMA1_Stream5_IRQHandler 323 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler 324 325 .weak DMA1_Stream6_IRQHandler 326 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler 327 328 .weak ADC_IRQHandler 329 .thumb_set ADC_IRQHandler,Default_Handler 330 331 .weak CAN1_TX_IRQHandler 332 .thumb_set CAN1_TX_IRQHandler,Default_Handler 333 334 .weak CAN1_RX0_IRQHandler 335 .thumb_set CAN1_RX0_IRQHandler,Default_Handler 336 337 .weak CAN1_RX1_IRQHandler 338 .thumb_set CAN1_RX1_IRQHandler,Default_Handler 339 340 .weak CAN1_SCE_IRQHandler 341 .thumb_set CAN1_SCE_IRQHandler,Default_Handler 342 343 .weak EXTI9_5_IRQHandler 344 .thumb_set EXTI9_5_IRQHandler,Default_Handler 345 346 .weak TIM1_BRK_TIM9_IRQHandler 347 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler 348 349 .weak TIM1_UP_TIM10_IRQHandler 350 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler 351 352 .weak TIM1_TRG_COM_TIM11_IRQHandler 353 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler 354 355 .weak TIM1_CC_IRQHandler 356 .thumb_set TIM1_CC_IRQHandler,Default_Handler 357 358 .weak TIM2_IRQHandler 359 .thumb_set TIM2_IRQHandler,Default_Handler 360 361 .weak TIM3_IRQHandler 362 .thumb_set TIM3_IRQHandler,Default_Handler 363 364 .weak TIM4_IRQHandler 365 .thumb_set TIM4_IRQHandler,Default_Handler 366 367 .weak I2C1_EV_IRQHandler 368 .thumb_set I2C1_EV_IRQHandler,Default_Handler 369 370 .weak I2C1_ER_IRQHandler 371 .thumb_set I2C1_ER_IRQHandler,Default_Handler 372 373 .weak I2C2_EV_IRQHandler 374 .thumb_set I2C2_EV_IRQHandler,Default_Handler 375 376 .weak I2C2_ER_IRQHandler 377 .thumb_set I2C2_ER_IRQHandler,Default_Handler 378 379 .weak SPI1_IRQHandler 380 .thumb_set SPI1_IRQHandler,Default_Handler 381 382 .weak SPI2_IRQHandler 383 .thumb_set SPI2_IRQHandler,Default_Handler 384 385 .weak USART1_IRQHandler 386 .thumb_set USART1_IRQHandler,Default_Handler 387 388 .weak USART2_IRQHandler 389 .thumb_set USART2_IRQHandler,Default_Handler 390 391 .weak USART3_IRQHandler 392 .thumb_set USART3_IRQHandler,Default_Handler 393 394 .weak EXTI15_10_IRQHandler 395 .thumb_set EXTI15_10_IRQHandler,Default_Handler 396 397 .weak RTC_Alarm_IRQHandler 398 .thumb_set RTC_Alarm_IRQHandler,Default_Handler 399 400 .weak OTG_FS_WKUP_IRQHandler 401 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler 402 403 .weak TIM8_BRK_TIM12_IRQHandler 404 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler 405 406 .weak TIM8_UP_TIM13_IRQHandler 407 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler 408 409 .weak TIM8_TRG_COM_TIM14_IRQHandler 410 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler 411 412 .weak TIM8_CC_IRQHandler 413 .thumb_set TIM8_CC_IRQHandler,Default_Handler 414 415 .weak DMA1_Stream7_IRQHandler 416 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler 417 418 .weak FSMC_IRQHandler 419 .thumb_set FSMC_IRQHandler,Default_Handler 420 421 .weak SDIO_IRQHandler 422 .thumb_set SDIO_IRQHandler,Default_Handler 423 424 .weak TIM5_IRQHandler 425 .thumb_set TIM5_IRQHandler,Default_Handler 426 427 .weak SPI3_IRQHandler 428 .thumb_set SPI3_IRQHandler,Default_Handler 429 430 .weak UART4_IRQHandler 431 .thumb_set UART4_IRQHandler,Default_Handler 432 433 .weak UART5_IRQHandler 434 .thumb_set UART5_IRQHandler,Default_Handler 435 436 .weak TIM6_DAC_IRQHandler 437 .thumb_set TIM6_DAC_IRQHandler,Default_Handler 438 439 .weak TIM7_IRQHandler 440 .thumb_set TIM7_IRQHandler,Default_Handler 441 442 .weak DMA2_Stream0_IRQHandler 443 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler 444 445 .weak DMA2_Stream1_IRQHandler 446 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler 447 448 .weak DMA2_Stream2_IRQHandler 449 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler 450 451 .weak DMA2_Stream3_IRQHandler 452 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler 453 454 .weak DMA2_Stream4_IRQHandler 455 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler 456 457 .weak ETH_IRQHandler 458 .thumb_set ETH_IRQHandler,Default_Handler 459 460 .weak ETH_WKUP_IRQHandler 461 .thumb_set ETH_WKUP_IRQHandler,Default_Handler 462 463 .weak CAN2_TX_IRQHandler 464 .thumb_set CAN2_TX_IRQHandler,Default_Handler 465 466 .weak CAN2_RX0_IRQHandler 467 .thumb_set CAN2_RX0_IRQHandler,Default_Handler 468 469 .weak CAN2_RX1_IRQHandler 470 .thumb_set CAN2_RX1_IRQHandler,Default_Handler 471 472 .weak CAN2_SCE_IRQHandler 473 .thumb_set CAN2_SCE_IRQHandler,Default_Handler 474 475 .weak OTG_FS_IRQHandler 476 .thumb_set OTG_FS_IRQHandler,Default_Handler 477 478 .weak DMA2_Stream5_IRQHandler 479 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler 480 481 .weak DMA2_Stream6_IRQHandler 482 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler 483 484 .weak DMA2_Stream7_IRQHandler 485 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler 486 487 .weak USART6_IRQHandler 488 .thumb_set USART6_IRQHandler,Default_Handler 489 490 .weak I2C3_EV_IRQHandler 491 .thumb_set I2C3_EV_IRQHandler,Default_Handler 492 493 .weak I2C3_ER_IRQHandler 494 .thumb_set I2C3_ER_IRQHandler,Default_Handler 495 496 .weak OTG_HS_EP1_OUT_IRQHandler 497 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler 498 499 .weak OTG_HS_EP1_IN_IRQHandler 500 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler 501 502 .weak OTG_HS_WKUP_IRQHandler 503 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler 504 505 .weak OTG_HS_IRQHandler 506 .thumb_set OTG_HS_IRQHandler,Default_Handler 507 508 .weak DCMI_IRQHandler 509 .thumb_set DCMI_IRQHandler,Default_Handler 510 511 .weak HASH_RNG_IRQHandler 512 .thumb_set HASH_RNG_IRQHandler,Default_Handler 513 514 .weak FPU_IRQHandler 515 .thumb_set FPU_IRQHandler,Default_Handler 516 517/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 518