1 /* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AMBA_PL011_UART_H 33 #define _AMBA_PL011_UART_H 34 35 #include "los_typedef.h" 36 37 #ifdef __cplusplus 38 #if __cplusplus 39 extern "C" { 40 #endif /* __cplusplus */ 41 #endif /* __cplusplus */ 42 43 #define UART_DR 0x0 /* data register */ 44 #define UART_RSR 0x04 45 #define UART_FR 0x18 /* flag register */ 46 #define UART_CLR 0x44 /* interrupt clear register */ 47 #define UART_CR 0x30 /* control register */ 48 #define UART_IBRD 0x24 /* integer baudrate register */ 49 #define UART_FBRD 0x28 /* decimal baudrate register */ 50 #define UART_LCR_H 0x2C 51 #define UART_IFLS 0x34 /* fifo register */ 52 #define UART_IMSC 0x38 /* interrupt mask register */ 53 #define UART_RIS 0x3C /* base interrupt state register */ 54 #define UART_MIS 0x40 /* mask interrupt state register */ 55 #define UART_ICR 0x44 56 #define UART_DMACR 0x48 /* DMA control register */ 57 58 #define CMD_LENGTH 128 59 60 extern CHAR g_inputCmd[CMD_LENGTH]; 61 extern INT32 g_inputIdx; 62 63 #ifdef __cplusplus 64 #if __cplusplus 65 } 66 #endif /* __cplusplus */ 67 #endif /* __cplusplus */ 68 #endif 69