1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 /** 16 **************************************************************************************** 17 * 18 * @file ce_common.h 19 * 20 * @brief CE common header file 21 * 22 **************************************************************************************** 23 */ 24 25 #ifndef _CE_COMMON_H_ 26 #define _CE_COMMON_H_ 27 28 /* 29 * INCLUDE FILES 30 **************************************************************************************** 31 */ 32 #include "reg_dma.h" 33 #include "dma_api.h" 34 35 #define RSA2048_WORD_NUM 64 36 #define RSA1024_WORD_NUM 32 37 #define ECC160_WORD_NUM 5 38 #define ECC224_WORD_NUM 7 39 #define ECC256_WORD_NUM 8 40 #define ECC384_WORD_NUM 12 41 #define ECC512_WORD_NUM 16 42 43 #define CE_RESULT_UNREADY 0x00 44 #define CE_RESULT_WAIT_OUT 0x01 45 #define CE_RESULT_READY 0x02 46 47 typedef enum { 48 AES_MODE = 0x00, 49 HASH_MODE = 0x01, 50 RSA_MODE = 0x02, 51 ECC_MODE = 0x03, 52 UNSUPPORT_MODE = 0x04 53 } DMA_CYPT_MOD_T; 54 55 typedef enum { 56 AES_ECB_MODE = 0x00, 57 AES_CBC_MODE = 0x01, 58 AES_CTR_MODE = 0x02, 59 AES_GCM_MODE = 0x03 60 } DMA_CYPT_AES_MOD_T; 61 62 typedef enum { 63 AES_128_MODE = 0x04, 64 AES_192_MODE = 0x06, 65 AES_256_MODE = 0x08, 66 } DMA_CYPT_AES_KEYLEN_T; 67 68 typedef enum { 69 AES_ENCR = 0x00, 70 AES_DECR = 0x01 71 } DMA_CYPT_AES_ENCR_SEL_T; 72 73 typedef enum { 74 RSA_1024_MODE = 0x00, 75 RSA_2048_MODE = 0x01 76 } DMA_CYPT_RSA_MOD_T; 77 78 typedef enum { 79 ECC_160_MODE = 0x00, 80 ECC_224_MODE = 0x01, 81 ECC_256_MODE = 0x02, 82 ECC_384_MODE = 0x03, 83 ECC_512_MODE = 0x04 84 } DMA_CYPT_ECC_MOD_T; 85 86 typedef enum { 87 ECC_A_NOT_EQ_MINUS_3 = 0x00, 88 ECC_A_EQ_MINUS_3 = 0x01 89 } DMA_CYPT_A_EQ_P3_T; 90 91 typedef enum { 92 PKA_R2_MODP_UNREADY = 0x00, 93 PKA_R2_MODP_READY = 0x01 94 } DMA_R2_MODP_READY_T; 95 96 typedef enum { 97 AES_BIG_ENDIAN = 0x00, 98 AES_LITTLE_ENDIAN = 0x01 99 } DMA_AES_ENDIAN_T; 100 101 typedef enum { 102 HASH_BIG_ENDIAN = 0x00, 103 HASH_LITTLE_ENDIAN = 0x01 104 } DMA_HASH_ENDIAN_T; 105 106 typedef enum { 107 HASH_SHA224_MODE = 0x00, 108 HASH_SHA256_MODE = 0x01, 109 HASH_SHA1_MODE = 0x02 110 } DMA_CYPT_HASH_MOD_T; 111 112 typedef enum { 113 HASH_SW_PAD = 0x00, 114 HASH_HW_PAD = 0x01 115 } DMA_CYPT_HASH_PAD_T; 116 117 typedef struct { 118 uint32_t length_byte; 119 uint32_t *aes_data; 120 } aes_state_t; 121 122 typedef struct { 123 uint32_t cipher_dat_len_byte; 124 uint32_t auth_dat_len_byte; 125 uint32_t auth_dat_pad_len_byte; 126 uint32_t *auth_data; 127 uint32_t *aes_data; 128 } aes_gcm_state_t; 129 130 typedef struct { 131 uint32_t length_byte; 132 uint8_t *buf; 133 } hash_state_t; 134 135 typedef struct { 136 uint32_t aes_key[8]; 137 uint32_t aes_iv[4]; 138 DMA_CYPT_AES_KEYLEN_T aes_keylen; 139 uint64_t aes_plain_len; 140 uint64_t aes_a_len; 141 DMA_CYPT_MOD_T dma_cypt_mode; 142 uint8_t ce_chn; 143 DMA_CYPT_AES_ENCR_SEL_T aes_enc_decr_sel; //aes encrypt or descrypt mode select 144 uint8_t rsa_keylen; 145 uint32_t mod_mult_parameter; 146 DMA_CYPT_ECC_MOD_T ecc_mode; 147 DMA_CYPT_RSA_MOD_T rsa_mode; 148 DMA_CYPT_AES_MOD_T aes_mode; 149 DMA_CYPT_A_EQ_P3_T ecc_a_eq_p3; 150 DMA_R2_MODP_READY_T R2modP_sta; 151 DMA_AES_ENDIAN_T aes_endian_sel; 152 DMA_HASH_ENDIAN_T hash_endian_sel; 153 DMA_CYPT_HASH_MOD_T hash_mode; 154 DMA_CYPT_HASH_PAD_T hash_pad_sel; 155 } dma_cypt_t; 156 157 #endif // _CE_COMMON_H_ 158