1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef _DMA_COMMON_H_ 16 #define _DMA_COMMON_H_ 17 18 #include <stdbool.h> 19 20 #define DMA_PAUSE_OFFSET 0 21 #define DMA_PAUSE_STATUS_OFFSET 16 22 23 #define DMA_PAUSE_SET (0x01UL << DMA_PAUSE_OFFSET) 24 #define DMA_PAUSE_STATUS_SET (0x01UL << DMA_PAUSE_STATUS_OFFSET) 25 26 27 #define DMA_FRAG_WAIT_OFFSET 0 28 #define DMA_SR_AHB_FREQ_OFFSET 16 29 #define DMA_OUT_ENDIAN_OFFSET 28 30 31 32 /* CH_HLTR */ 33 #define DMA_CH_HALT_SET_OFFSET 0 34 #define DMA_CH_HALT_STAT_OFFSET 16 35 36 #define DMA_CH_HALT_SET_SET (0x01UL << DMA_CH_HALT_SET_OFFSET) 37 #define DMA_CH_HALT_STAT_SET (0x01UL << DMA_CH_HALT_STAT_OFFSET) 38 39 /* CH_RQR */ 40 #define DMA_CH_SRQ_OFFSET 0 41 #define DMA_CH_ERQM_OFFSET 1 42 43 #define DMA_CH_SRQ_SET (0x01UL << DMA_CH_SRQ_OFFSET) 44 45 /* CH_CTLR */ 46 #define DMA_CH_CHENA_OFFSET 0 47 #define ASDMA_CH_AUTO_CLOSE_EN_OFFSET 2//ASDMA Only 48 #define DMA_CH_LSTENA_OFFSET 4 49 #define ASDMA_CH_TBL0_CNT_SEL_OFFSET 5//ASDMA Only 50 #define DMA_CH_LSTCV_OFFSET 8 51 #define DMA_CH_RQPLVL_OFFSET 12 52 #define DMA_CH_BUSBU_OFFSET 16 53 54 #define DMA_CH_CHENA_SET (0x01UL << DMA_CH_CHENA_OFFSET) 55 #define ASDMA_CH_AUTO_CLOSE_EN_SET (0x01UL << ASDMA_CH_AUTO_CLOSE_EN_OFFSET)//ASDMA Only 56 #define DMA_CH_LSTENA_SET (0x01UL << DMA_CH_LSTENA_OFFSET) 57 #define DMA_CH_LSTCV_SET (0x01UL << DMA_CH_LSTCV_OFFSET) 58 59 /* CH_ICSR */ 60 #define DMA_CH_TBL0_IENA_OFFSET 0 61 #define DMA_CH_TBL1_IENA_OFFSET 1 62 #define DMA_CH_TBL2_IENA_OFFSET 2 63 #define DMA_CH_TLL_IENA_OFFSET 3 64 #define DMA_CH_CE_IENA_OFFSET 4 65 #define DMA_CH_TBL0_IRST_OFFSET 8 66 #define DMA_CH_TBL1_IRST_OFFSET 9 67 #define DMA_CH_TBL2_IRST_OFFSET 10 68 #define DMA_CH_TLL_IRST_OFFSET 11 69 #define DMA_CH_CE_IRST_OFFSET 12 70 #define DMA_CH_TBL0_IMST_OFFSET 16 71 #define DMA_CH_TBL1_IMST_OFFSET 17 72 #define DMA_CH_TBL2_IMST_OFFSET 18 73 #define DMA_CH_TLL_IMST_OFFSET 19 74 #define DMA_CH_CE_IMST_OFFSET 20 75 #define DMA_CH_TBL0_ICLR_OFFSET 24 76 #define DMA_CH_TBL1_ICLR_OFFSET 25 77 #define DMA_CH_TBL2_ICLR_OFFSET 26 78 #define DMA_CH_TLL_ICLR_OFFSET 27 79 #define DMA_CH_CE_ICLR_OFFSET 28 80 81 #define DMA_CH_TBL0_IENA_SET (0x01UL << DMA_CH_TBL0_IENA_OFFSET) 82 #define DMA_CH_TBL1_IENA_SET (0x01UL << DMA_CH_TBL1_IENA_OFFSET) 83 #define DMA_CH_TBL2_IENA_SET (0x01UL << DMA_CH_TBL2_IENA_OFFSET) 84 #define DMA_CH_TLL_IENA_SET (0x01UL << DMA_CH_TLL_IENA_OFFSET) 85 #define DMA_CH_CE_IENA_SET (0x01UL << DMA_CH_CE_IENA_OFFSET) 86 #define DMA_CH_ALL_IENA_SET (0x3FUL << DMA_CH_TBL0_IENA_OFFSET) 87 #define DMA_CH_TBL0_IRST_SET (0x01UL << DMA_CH_TBL0_IRST_OFFSET) 88 #define DMA_CH_TBL1_IRST_SET (0x01UL << DMA_CH_TBL1_IRST_OFFSET) 89 #define DMA_CH_TBL2_IRST_SET (0x01UL << DMA_CH_TBL2_IRST_OFFSET) 90 #define DMA_CH_TLL_IRST_SET (0x01UL << DMA_CH_TLL_IRST_OFFSET) 91 #define DMA_CH_CE_IRST_SET (0x01UL << DMA_CH_CE_IRST_OFFSET) 92 #define DMA_CH_ALL_IRST_SET (0x3FUL << DMA_CH_TBL0_IRST_OFFSET) 93 #define DMA_CH_TBL0_IMST_SET (0x01UL << DMA_CH_TBL0_IMST_OFFSET) 94 #define DMA_CH_TBL1_IMST_SET (0x01UL << DMA_CH_TBL1_IMST_OFFSET) 95 #define DMA_CH_TBL2_IMST_SET (0x01UL << DMA_CH_TBL2_IMST_OFFSET) 96 #define DMA_CH_TLL_IMST_SET (0x01UL << DMA_CH_TLL_IMST_OFFSET) 97 #define DMA_CH_CE_IMST_SET (0x01UL << DMA_CH_CE_IMST_OFFSET) 98 #define DMA_CH_ALL_IMST_SET (0x3FUL << DMA_CH_TBL0_IMST_OFFSET) 99 #define DMA_CH_TBL0_ICLR_SET (0x01UL << DMA_CH_TBL0_ICLR_OFFSET) 100 #define DMA_CH_TBL1_ICLR_SET (0x01UL << DMA_CH_TBL1_ICLR_OFFSET) 101 #define DMA_CH_TBL2_ICLR_SET (0x01UL << DMA_CH_TBL2_ICLR_OFFSET) 102 #define DMA_CH_TLL_ICLR_SET (0x01UL << DMA_CH_TLL_ICLR_OFFSET) 103 #define DMA_CH_CE_ICLR_SET (0x01UL << DMA_CH_CE_ICLR_OFFSET) 104 #define DMA_CH_ALL_ICLR_SET (0x3FUL << DMA_CH_TBL0_ICLR_OFFSET) 105 106 /* CH_TBL0CR */ 107 #define DMA_CH_TBL0_CNT_OFFSET 0 108 #define ASDMA_CH_LLI_DEDIC_INT_EN_OFFSET 16//ASDMA Only 109 #define ASDMA_CH_LLI_DEDIC_COUNT_EN_OFFSET 17//ASDMA Only 110 #define DMA_CH_TBL1_CNT_RH_OFFSET 17//DAM_CX Only 111 #define DMA_CH_LASTLLI_OFFSET 19 112 #define ASDMA_CH_CONSTADDR_OFFSET 20//ASDMA Only 113 #define DMA_CH_CONSTSA_OFFSET 20//DMA_CX Only 114 #define DMA_CH_CONSTDA_OFFSET 21//DMA_CX Only 115 #define DMA_CH_WRPADR_OFFSET 22//DAM_CX Only 116 #define DMA_CH_WRPDADR_OFFSET 23//DAM_CX Only 117 #define DMA_CH_RQTYP_OFFSET 24 118 #define DMA_CH_SWT_MODE_OFFSET 26 119 #define DMA_CH_DBUSU_OFFSET 28 120 #define DMA_CH_SBUSU_OFFSET 30 121 122 #define ASDMA_CH_LLI_DEDIC_INT_EN_SET (0x01UL << ASDMA_CH_LLI_DEDIC_INT_EN_OFFSET)//ASDMA Only 123 #define ASDMA_CH_LLI_DEDIC_COUNT_EN_SET (0x01UL << ASDMA_CH_LLI_DEDIC_COUNT_EN_OFFSET)//ASDMA Only 124 #define DMA_CH_LASTLLI_SET (0x01UL << DMA_CH_LASTLLI_OFFSET) 125 #define ASDMA_CH_CONSTADDR_SET (0x01UL << ASDMA_CH_CONSTADDR_OFFSET) 126 #define DMA_CH_CONSTSA_SET (0x01UL << DMA_CH_CONSTSA_OFFSET)//DMA_CX Only 127 #define DMA_CH_CONSTDA_SET (0x01UL << DMA_CH_CONSTDA_OFFSET)//DMA_CX Only 128 #define DMA_CH_WRPADR_SET (0x01UL << DMA_CH_WRPADR_OFFSET)//DAM_CX Only 129 #define DMA_CH_WRPDADR_SET (0x01UL << DMA_CH_WRPDADR_OFFSET)//DMA_CX Only 130 131 /* CH_TBL1CR */ 132 #define DMA_CH_TBL1_CNT_OFFSET 0 133 #define DMA_CH_TBL1_CNT_RL_OFFSET 17 134 135 /* CH_TBL2CR */ 136 #define DMA_CH_TBL2_CNT_OFFSET 0 137 #define DMA_CH_LLI_DEDIC_INT_EN_OFFSET 28//DMA_CX only 138 #define DMA_CH_LLI_DEDIC_COUNT_EN_OFFSET 29//DMA_CX Only 139 140 #define DMA_CH_LLI_DEDIC_INT_EN_SET (0x01UL << DMA_CH_LLI_DEDIC_INT_EN_OFFSET)//DMA_CX only 141 #define DMA_CH_LLI_DEDIC_COUNT_EN_SET (0x01UL << DMA_CH_LLI_DEDIC_COUNT_EN_OFFSET)//DMA_CX Only 142 143 /* CH_TSR */ 144 #define DMA_CH_STRANSZ_OFFSET 0 145 #define DMA_CH_DTRANSZ_OFFSET 16 146 147 /* CH_WMAR */ 148 #define DMA_CH_WRPMADR_OFFSET 0 149 #define DMA_CH_SAH4_OFFSET 28 150 151 /* CH_WJAR */ 152 #define DMA_CH_WRPJADR_OFFSET 0 153 #define DMA_CH_DAH4_OFFSET 28 154 155 /* CH_LNAR */ 156 #define DMA_CH_LLINADR_OFFSET 0 157 158 /* CH_TBL0SR */ 159 #define DMA_CH_STBL0SZ_OFFSET 0 160 #define DMA_CH_DTBL0SZ_OFFSET 16 161 162 /* CH_TBL1SSR */ 163 #define DMA_CH_TBL1_SSZ_OFFSET 0 164 #define DMA_CH_LLINADRH4_OFFSET 28 165 166 /* CH_TBL1DSR */ 167 #define DMA_CH_TBL1_DSZ_OFFSET 0 168 169 #define DMA_INVALID_ADDR 0xFFFFFFFFUL 170 171 typedef enum { 172 DMA_CH_0 = 0, 173 DMA_CH_1 = 1, 174 DMA_CH_2 = 2, 175 DMA_CH_3 = 3, 176 DMA_CH_4 = 4, 177 DMA_CH_5 = 5, 178 DMA_CH_6 = 6, 179 DMA_CH_7 = 7, 180 DMA_CH_8 = 8, 181 DMA_CH_9 = 9, 182 DMA_CH_10 = 10, 183 DMA_CH_11 = 11, 184 DMA_CH_12 = 12, 185 DMA_CH_13 = 13, 186 DMA_CX_CH_QTY = 14, 187 DMA_CH_14 = 14, 188 DMA_CH_15 = 15, 189 DMA_CH_16 = 16, 190 DMA_CH_17 = 17, 191 DMA_CH_18 = 18, 192 DMA_CH_19 = 19, 193 DMA_CH_20 = 20, 194 DMA_CH_21 = 21, 195 DMA_CH_22 = 22, 196 DMA_CH_23 = 23, 197 DMA_CH_24 = 24, 198 DMA_CH_25 = 25, 199 DMA_CH_26 = 26, 200 DMA_CH_27 = 27, 201 DMA_CH_28 = 28, 202 DMA_CH_29 = 29, 203 DMA_CH_30 = 30, 204 DMA_CH_31 = 31, 205 ASDMA_CH_QTY = 32, 206 DMA_CH_NONE = 0xFF, 207 } CS_DMA_CH_ENUM; 208 209 typedef enum { 210 REQ_CID_UART0_RX = 0, 211 REQ_CID_UART0_TX = 1, 212 REQ_CID_UART1_RX = 2, 213 REQ_CID_UART1_TX = 3, 214 REQ_CID_UART2_RX = 4, 215 REQ_CID_UART2_TX = 5, 216 REQ_CID_I2CM_RX = 6, 217 REQ_CID_I2CM_TX = 7, 218 REQ_CID_SPI_RX = 8, 219 REQ_CID_SPI_TX = 9, 220 REQ_CID_SDMMC_RX = 10, 221 REQ_CID_SDMMC_TX = 11, 222 REQ_CID_AUD_PROC_RX01 = 12, 223 REQ_CID_AUD_PROC_RX23 = 13, 224 REQ_CID_AUD_PROC_TX0 = 14, 225 REQ_CID_AUD_PROC_TX1 = 15, 226 REQ_CID_AUD_PROC_TX2 = 16, 227 REQ_CID_AUD_PROC_TX3 = 17, 228 REQ_CID_AUD_PROC_RXTX0 = 18, 229 REQ_CID_AUD_PROC_RXTX1 = 19, 230 REQ_CID_AUD_PROC_TXRX0 = 20, 231 REQ_CID_AUD_PROC_TXRX1 = 21, 232 REQ_CID_AUD_SRC_TX = 22, 233 REQ_CID_AUD_SRC_RX = 23, 234 REQ_CID_QTY = 24, 235 236 REQ_CID_MEMORY = 0xFE, 237 REQ_CID_NONE = 0xFF, 238 } DMA_REQ_CID_ENUM; 239 240 typedef enum { 241 DMA_LITTLE_ENDIAN = 0, 242 DMA_BIG_ENDIAN = 1, 243 } DMA_OUT_ENDIAN_ENUM; 244 245 typedef enum { 246 EXREQ_FALLING_EDGE = 0, 247 EXREQ_LOW_LEVEL = 1, 248 EXREQ_RISING_EDGE = 2, 249 EXREQ_HIGH_LEVEL = 3, 250 } DMA_EXREQ_TYPE_ENUM; 251 252 typedef enum { 253 DMA_PRIO_LOWEST = 0, 254 DMA_PRIO_LOW = 1, 255 DMA_PRIO_HIGH = 2, 256 DMA_PRIO_HIGHEST = 3, 257 } DMA_PRIORITY_ENUM; 258 259 typedef enum { 260 AHB_BURST_INCR8 = 0, 261 AHB_BURST_INCR4 = 1, 262 AHB_BURST_INCR16 = 2, 263 } DMA_AHB_BURST_SEL_ENUM; 264 265 typedef enum { 266 /* bit[0] fix on src enable 267 * bit[1] fix on dest enable 268 */ 269 FIX_ON_NONE = 0, 270 FIX_ON_SRC = 1, 271 FIX_ON_DEST = 2, 272 FIX_ON_BOTH = 3, 273 } DMA_ADDR_FIX_TYPE_ENUM; 274 275 typedef enum { 276 WRAP_ON_NONE = 0, 277 WRAP_ON_SRC = 1, 278 WRAP_ON_DEST = 3, 279 } DMA_ADDR_WRAP_TYPE_ENUM; 280 281 typedef enum { 282 REQ_FRAG = 0, 283 REQ_BLK = 1, 284 REQ_TRSC = 2, 285 REQ_LLIST = 3, 286 } DMA_REQ_MODE_ENUM; 287 288 typedef enum { 289 SWT_ABCD_ABCD = 0, 290 SWT_ABCD_DCBA = 1, 291 SWT_ABCD_BADC = 2, 292 SWT_ABCD_CDBA = 3, 293 } DMA_SWT_MODE_ENUM; 294 295 typedef enum { 296 AHB_BYTE = 0, 297 AHB_HWORD = 1, 298 AHB_WORD = 2, 299 AHB_DWORD = 3, 300 } DMA_AHB_SIZE_ENUM; 301 302 typedef enum { 303 DMA_CX = 0, 304 ASDMA = 1, 305 } DMA_TYPE_ENUM; 306 307 typedef enum { 308 DMA_UART0_RX = 0, 309 DMA_UART0_TX = 1, 310 DMA_UART1_RX = 2, 311 DMA_UART1_TX = 3, 312 DMA_UART2_RX = 4, 313 DMA_UART2_TX = 5, 314 DMA_I2CM_RX = 6, 315 DMA_I2CM_TX = 7, 316 DMA_SPI_RX = 8, 317 DMA_SPI_TX = 9, 318 DMA_SDMMC_RX = 10, 319 DMA_SDMCC_TX = 11, 320 DMA_AUD_PROC_RX01 = 12, 321 DMA_AUD_PROC_RX23 = 13, 322 DMA_AUD_PROC_TX0 = 14, 323 DMA_AUD_PROC_TX1 = 15, 324 DMA_AUD_PROC_TX2 = 16, 325 DMA_AUD_PROC_TX3 = 17, 326 DMA_AUD_PROC_RXTX0 = 18, 327 DMA_AUD_PROC_RXTX1 = 19, 328 DMA_AUD_PROC_TXRX0 = 20, 329 DMA_AUD_PROC_TXRX1 = 21, 330 DMA_AUD_SRC_TX = 22, 331 DMA_AUD_SRC_RX = 23, 332 DMA_CX_PERIPH_QTY = 24, 333 334 DMA_MEMORY = 0xFE, 335 DMA_PERIPH_NONE = 0xFF, 336 } DMA_CX_PERIPH_ENUM; 337 338 typedef enum { 339 DMA_TRANS_M2M = 0, 340 DMA_TRANS_M2P = 1, 341 DMA_TRANS_P2M = 2, 342 DMA_TRANS_P2P = 3, 343 } DMA_TRANS_TYPE_ENUM; 344 345 typedef enum { 346 ASDMA_ID_CS1000_UART0_RX = 0, 347 ASDMA_ID_CS1000_UART0_TX = 1, 348 ASDMA_ID_CS1000_UART1_RX = 2, 349 ASDMA_ID_CS1000_UART1_TX = 3, 350 ASDMA_ID_CS1000_UART2_RX = 4, 351 ASDMA_ID_CS1000_UART2_TX = 5, 352 ASDMA_ID_CS1000_SPI0_RX = 6, 353 ASDMA_ID_CS1000_SPI0_TX = 7, 354 ASDMA_ID_CS1000_SPI1_RX = 8, 355 ASDMA_ID_CS1000_SPI1_TX = 9, 356 ASDMA_ID_CS1000_SDMMC_RX = 10, 357 ASDMA_ID_CS1000_SDMCC_TX = 11, 358 ASDMA_ID_CS1000_I2CM0_RX = 12, 359 ASDMA_ID_CS1000_I2CM0_TX = 13, 360 ASDMA_ID_CS1000_I2CM1_RX = 14, 361 ASDMA_ID_CS1000_I2CM1_TX = 15, 362 ASDMA_ID_CS1000_CAMERA_RX = 16, 363 364 ASDMA_ID_AUDIO_RX = 28, 365 ASDMA_ID_AUDIO_TX = 29, 366 ASDMA_ID_GEN_SOFT_RX = 30, 367 ASDMA_ID_GEN_SOFT_TX = 31, 368 369 ASDMA_ID_MEMORY = 0xFE, 370 ASDMA_ID_NONE = 0xFF, 371 } ASDMA_PERIPH_ID_ENUM; 372 373 typedef void (*CS_DMA_IRQ_HANDLER_T)(uint8_t dma_type, uint8_t ch, uint32_t int_status); 374 375 typedef struct { 376 DMA_TYPE_ENUM dma_type; 377 uint8_t ch; 378 DMA_EXREQ_TYPE_ENUM exreq_type; 379 bool llist_en; 380 bool llist_cfg_valid; 381 bool llist_end; 382 DMA_PRIORITY_ENUM priority; 383 DMA_AHB_BURST_SEL_ENUM ahb_burst_sel; 384 uint32_t int_mask; 385 uint32_t src_addr;//must be configed as DMA_INVALID_ADDR in ASDMA RX mode 386 uint32_t dest_addr;//must be configed as DMA_INVALID_ADDR in ASDMA TX mode 387 uint32_t tbl0_cnt; 388 uint32_t tbl1_cnt_rh;//DMA_CX Only 389 uint32_t tbl1_cnt; 390 uint32_t tbl2_cnt;//DMA_CX Only 391 uint16_t src_tran_sz;//DMA_CX Only 392 uint16_t dest_tran_sz;//DMA_CX Only 393 uint32_t wrp_maddr;//DMA_CX Only 394 uint32_t wrp_jaddr;//DMA_CX Only 395 uint32_t nxt_addr; 396 uint16_t src_tbl0_sz;//DMA_CX Only 397 uint16_t dest_tbl0_sz;//DMA_CX Only 398 uint32_t src_tbl1_sz;//DMA_CX Only 399 uint32_t dest_tbl1_sz;//DMA_CX Only 400 uint8_t ext_req_cid;//DMA_CX Only 401 bool llist_dedicated_int_en; 402 DMA_ADDR_FIX_TYPE_ENUM addr_fix_type; 403 DMA_ADDR_WRAP_TYPE_ENUM addr_wrap_type;//DMA_CX Only 404 DMA_REQ_MODE_ENUM req_mode; 405 DMA_SWT_MODE_ENUM swt_mode; 406 DMA_AHB_SIZE_ENUM src_size; 407 DMA_AHB_SIZE_ENUM dest_size; 408 CS_DMA_IRQ_HANDLER_T handler; 409 DMA_CX_PERIPH_ENUM src_periph; 410 DMA_CX_PERIPH_ENUM dest_periph; 411 DMA_TRANS_TYPE_ENUM trans_type; 412 bool ch_en; 413 } DMA_CFG_T; 414 415 #endif 416