1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 /** 16 **************************************************************************************** 17 * 18 * @file dma_generic.h 19 * 20 * @brief DMA generic header file 21 * 22 **************************************************************************************** 23 */ 24 25 #ifndef _DMA_GENERIC_H_ 26 #define _DMA_GENERIC_H_ 27 28 /* 29 * INCLUDE FILES 30 **************************************************************************************** 31 */ 32 #include "reg_dma.h" 33 #include "dma_common.h" 34 35 /// DMA channel indexes 36 enum { 37 /// Channels for IPC 38 DMA_CHANNEL_IPC_DATA_AC0_TX = 0, 39 DMA_CHANNEL_IPC_DATA_AC1_TX = 1, 40 DMA_CHANNEL_IPC_DATA_AC2_TX = 2, 41 DMA_CHANNEL_IPC_DATA_AC3_TX = 3, 42 DMA_CHANNEL_IPC_DATA_BCN_TX = 4, 43 DMA_CHANNEL_IPC_DATA_RX0 = 5, 44 DMA_CHANNEL_IPC_MSG = 6, 45 DMA_CHANNEL_IPC_DBG = 7, 46 DMA_CHANNEL_IPC_CFM_TX = 8, 47 DMA_CHANNEL_IPC_GP_DL = 9, 48 DMA_CHANNEL_IPC_DBG_DUMP = 10, 49 DMA_CHANNEL_IPC_GP_UL = 11, 50 DMA_CHANNEL_IPC_MAX, 51 /// Channels for UART 52 DMA_CHANNEL_UART_RX = 8, 53 DMA_CHANNEL_UART_TX = 9, 54 /// Channels for SPI0 55 DMA_CHANNEL_SPI0_RX = 8, 56 DMA_CHANNEL_SPI0_TX = 9, 57 /// Channels for SDMMC 58 DMA_CHANNEL_SDMMC_RX = 10, 59 DMA_CHANNEL_SDMMC_TX = 11, 60 /// Channels for CRYPTO 61 DMA_CHANNEL_CYPT_IDX0 = 12, 62 DMA_CHANNEL_CYPT_IDX1 = 13, 63 64 DMA_CHANNEL_MAX = 20 65 }; 66 67 /// DMA descriptors 68 typedef struct { 69 uint32_t SAR; /* Src Addr */ 70 uint32_t DAR; /* Dest Addr */ 71 uint32_t TBL0CR; /* Trans Blk Lvl-0 Cnt */ 72 uint32_t TBL1CR; /* Trans Blk Lvl-1 Cnt */ 73 uint32_t TBL2CR; /* Trans Blk Lvl-2 Cnt */ 74 uint32_t TSR; /* Trans Sz */ 75 uint32_t RESERVED0[2]; 76 uint32_t LNAR; /* Lli Node Addr */ 77 uint32_t RESERVED1[3]; 78 }dma_desc_t; 79 80 #endif // _DMA_GENERIC_H_ 81