1 /*
2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "mipi_csi_hi35xx.h"
17 #include "hdf_log.h"
18 #include "mipi_rx_hi2121.h"
19 #include "securec.h"
20
21 #ifdef __cplusplus
22 #if __cplusplus
23 extern "C" {
24 #endif
25 #endif /* End of #ifdef __cplusplus */
26
27 #define HDF_LOG_TAG mipi_csi_hi35xx
28 /* macro definition */
29 #define MIPI_RX_DEV_NAME "mipi_csi_dev"
30 #define MIPI_RX_PROC_NAME "mipi_rx"
31
32 #define HIMEDIA_DYNAMIC_MINOR 255
33
34 #define COMBO_MAX_LANE_NUM 4
35
36 #define COMBO_MIN_WIDTH 32
37 #define COMBO_MIN_HEIGHT 32
38
39 #define MIPI_HEIGHT_ALIGN 2
40 #define MIPI_WIDTH_ALIGN 2
41
42 #define ENABLE_INT_MASK
43
44 #define SYNC_CODE_OFFSET8 (1 << 8) /* 8 --N+1 Frame sync */
45 #define SYNC_CODE_OFFSET10 (1 << 10) /* 10 --N+1 Frame sync */
46
47 /* function definition */
MipiIsHsModeCfged(struct MipiCsiCntlr * cntlr)48 static bool MipiIsHsModeCfged(struct MipiCsiCntlr *cntlr)
49 {
50 bool hsModeCfged;
51
52 OsalSpinLock(&cntlr->ctxLock);
53 hsModeCfged = cntlr->ctx.hsModeCfged;
54 OsalSpinUnlock(&cntlr->ctxLock);
55
56 return hsModeCfged;
57 }
58
MipiIsDevValid(struct MipiCsiCntlr * cntlr,uint8_t devno)59 static bool MipiIsDevValid(struct MipiCsiCntlr *cntlr, uint8_t devno)
60 {
61 bool devValid;
62
63 OsalSpinLock(&cntlr->ctxLock);
64 devValid = cntlr->ctx.devValid[devno];
65 OsalSpinUnlock(&cntlr->ctxLock);
66
67 return devValid;
68 }
69
MipiIsDevCfged(struct MipiCsiCntlr * cntlr,uint8_t devno)70 static bool MipiIsDevCfged(struct MipiCsiCntlr *cntlr, uint8_t devno)
71 {
72 bool devCfged;
73
74 OsalSpinLock(&cntlr->ctxLock);
75 devCfged = cntlr->ctx.devCfged[devno];
76 OsalSpinUnlock(&cntlr->ctxLock);
77
78 return devCfged;
79 }
80
CheckLane(uint8_t devno,int laneNum,LaneDivideMode curLaneDivideMode,int * laneSum,const short pLaneId[])81 static int CheckLane(uint8_t devno, int laneNum, LaneDivideMode curLaneDivideMode,
82 int *laneSum, const short pLaneId[])
83 {
84 int i;
85 int j;
86 int allLaneIdInvalidFlag = 1;
87 for (i = 0; i < laneNum; i++) {
88 int tempId = pLaneId[i];
89 int laneValid;
90
91 if (tempId < -1 || tempId >= COMBO_MAX_LANE_NUM) {
92 HDF_LOGE("%s: laneId[%d] is invalid value %d.", __func__, i, tempId);
93 return HDF_ERR_INVALID_PARAM;
94 }
95
96 if (tempId == -1) {
97 continue;
98 }
99 *laneSum = *laneSum + 1;
100 allLaneIdInvalidFlag = 0;
101
102 for (j = i + 1; j < laneNum; j++) {
103 if (tempId == pLaneId[j]) {
104 HDF_LOGE("%s: laneId[%d] can't be same value %d as laneId[%d]", __func__, i, tempId, j);
105 return HDF_ERR_INVALID_PARAM;
106 }
107 }
108
109 laneValid = MipiRxDrvIsLaneValid(devno, tempId, curLaneDivideMode);
110 if (laneValid == 0) {
111 HDF_LOGE("%s: laneId[%d] %d is invalid in hs_mode %d", __func__, i, tempId, curLaneDivideMode);
112 return HDF_ERR_INVALID_PARAM;
113 }
114 }
115 if (allLaneIdInvalidFlag != 0) {
116 HDF_LOGE("%s: all laneId is invalid!", __func__);
117 return HDF_ERR_INVALID_PARAM;
118 }
119 return HDF_SUCCESS;
120 }
121
CheckLaneId(struct MipiCsiCntlr * cntlr,uint8_t devno,InputMode inputMode,const short pLaneId[])122 static int CheckLaneId(struct MipiCsiCntlr *cntlr, uint8_t devno, InputMode inputMode, const short pLaneId[])
123 {
124 int laneNum;
125 int laneSum = 0;
126 int mode1LaneNum = 2;
127 LaneDivideMode curLaneDivideMode;
128
129 if (inputMode == INPUT_MODE_MIPI) {
130 laneNum = MIPI_LANE_NUM;
131 } else if (inputMode == INPUT_MODE_LVDS) {
132 laneNum = LVDS_LANE_NUM;
133 } else {
134 return HDF_SUCCESS;
135 }
136
137 OsalSpinLock(&cntlr->ctxLock);
138 curLaneDivideMode = cntlr->ctx.laneDivideMode;
139 OsalSpinUnlock(&cntlr->ctxLock);
140 if (CheckLane(devno, laneNum, curLaneDivideMode, &laneSum, pLaneId) != HDF_SUCCESS) {
141 HDF_LOGE("%s: laneId is invalid!", __func__);
142 return HDF_FAILURE;
143 }
144 if ((curLaneDivideMode == LANE_DIVIDE_MODE_1) && (laneSum > mode1LaneNum)) {
145 HDF_LOGE("%s: When divide mode is LANE_DIVIDE_MODE_1, valid lane number cannot be greater than 2", __func__);
146 return HDF_ERR_INVALID_PARAM;
147 }
148 return HDF_SUCCESS;
149 }
150
MipiGetLaneBitmap(InputMode inputMode,const short * pLaneId,unsigned int * pTotalLaneNum)151 static unsigned int MipiGetLaneBitmap(InputMode inputMode, const short *pLaneId, unsigned int *pTotalLaneNum)
152 {
153 unsigned int laneBitmap = 0;
154 int laneNum;
155 int totalLaneNum;
156 int i;
157
158 if (inputMode == INPUT_MODE_MIPI) {
159 laneNum = MIPI_LANE_NUM;
160 } else {
161 laneNum = LVDS_LANE_NUM;
162 }
163
164 totalLaneNum = 0;
165
166 for (i = 0; i < laneNum; i++) {
167 short tmpLaneId;
168 tmpLaneId = pLaneId[i];
169
170 if (tmpLaneId != -1) {
171 laneBitmap = laneBitmap | (1 << (unsigned short)(tmpLaneId));
172 totalLaneNum++;
173 }
174 }
175
176 *pTotalLaneNum = totalLaneNum;
177
178 return laneBitmap;
179 }
180
MipiCheckCombDevAttr(const ComboDevAttr * pAttr)181 static int MipiCheckCombDevAttr(const ComboDevAttr *pAttr)
182 {
183 if (pAttr->devno >= COMBO_DEV_MAX_NUM) {
184 HDF_LOGE("%s: invalid comboDev number(%u).", __func__, pAttr->devno);
185 return HDF_ERR_INVALID_PARAM;
186 }
187
188 if (pAttr->inputMode < INPUT_MODE_MIPI || pAttr->inputMode >= INPUT_MODE_BUTT) {
189 HDF_LOGE("%s: invalid inputMode(%d).", __func__, pAttr->inputMode);
190 return HDF_ERR_INVALID_PARAM;
191 }
192
193 if (pAttr->dataRate != MIPI_DATA_RATE_X1) {
194 HDF_LOGE("%s: invalid dataRate(%d).", __func__, pAttr->dataRate);
195 return HDF_ERR_INVALID_PARAM;
196 }
197
198 if (pAttr->imgRect.x < 0 || pAttr->imgRect.y < 0) {
199 HDF_LOGE("%s: crop x and y (%d, %d) must be great than 0", __func__, pAttr->imgRect.x, pAttr->imgRect.y);
200 return HDF_ERR_INVALID_PARAM;
201 }
202
203 if (pAttr->imgRect.width < COMBO_MIN_WIDTH || pAttr->imgRect.height < COMBO_MIN_HEIGHT) {
204 HDF_LOGE("%s: invalid imgSize(%u, %u), can't be smaller than (%d, %d)", __func__,
205 pAttr->imgRect.width, pAttr->imgRect.height, COMBO_MIN_WIDTH, COMBO_MIN_HEIGHT);
206 return HDF_ERR_INVALID_PARAM;
207 }
208
209 /* width and height align 2 */
210 if ((pAttr->imgRect.width & (MIPI_WIDTH_ALIGN - 1)) != 0) {
211 HDF_LOGE("%s: imgWidth should be %d bytes align which is %u!", __func__,
212 MIPI_WIDTH_ALIGN, pAttr->imgRect.width);
213 return HDF_ERR_INVALID_PARAM;
214 }
215
216 if ((pAttr->imgRect.height & (MIPI_HEIGHT_ALIGN - 1)) != 0) {
217 HDF_LOGE("%s: imgHeight should be %d bytes align which is %u!", __func__,
218 MIPI_WIDTH_ALIGN, pAttr->imgRect.height);
219 return HDF_ERR_INVALID_PARAM;
220 }
221
222 return HDF_SUCCESS;
223 }
224
CheckLvdsWdrMode(const LvdsDevAttr * pAttr)225 static int CheckLvdsWdrMode(const LvdsDevAttr *pAttr)
226 {
227 int ret = HDF_SUCCESS;
228
229 switch (pAttr->wdrMode) {
230 case HI_WDR_MODE_2F:
231 case HI_WDR_MODE_3F:
232 case HI_WDR_MODE_4F: {
233 if (pAttr->vsyncAttr.syncType != LVDS_VSYNC_NORMAL &&
234 pAttr->vsyncAttr.syncType != LVDS_VSYNC_SHARE) {
235 HDF_LOGE("%s: invalid syncType, must be LVDS_VSYNC_NORMAL or LVDS_VSYNC_SHARE", __func__);
236 ret = HDF_FAILURE;
237 }
238 break;
239 }
240
241 case HI_WDR_MODE_DOL_2F:
242 case HI_WDR_MODE_DOL_3F:
243 case HI_WDR_MODE_DOL_4F: {
244 if (pAttr->vsyncAttr.syncType == LVDS_VSYNC_NORMAL) {
245 if (pAttr->fidAttr.fidType != LVDS_FID_IN_SAV &&
246 pAttr->fidAttr.fidType != LVDS_FID_IN_DATA) {
247 HDF_LOGE("%s: invalid fidType, must be LVDS_FID_IN_SAV or LVDS_FID_IN_DATA", __func__);
248 ret = HDF_FAILURE;
249 }
250 } else if (pAttr->vsyncAttr.syncType == LVDS_VSYNC_HCONNECT) {
251 if (pAttr->fidAttr.fidType != LVDS_FID_NONE &&
252 pAttr->fidAttr.fidType != LVDS_FID_IN_DATA) {
253 HDF_LOGE("%s: invalid fidType, must be LVDS_FID_NONE or LVDS_FID_IN_DATA", __func__);
254 ret = HDF_FAILURE;
255 }
256 } else {
257 HDF_LOGE("%s: invalid syncType, must be LVDS_VSYNC_NORMAL or LVDS_VSYNC_HCONNECT", __func__);
258 ret = HDF_FAILURE;
259 }
260 break;
261 }
262
263 default:
264 break;
265 }
266
267 return ret;
268 }
269
CheckLvdsDevAttr(struct MipiCsiCntlr * cntlr,uint8_t devno,const LvdsDevAttr * pAttr)270 static int CheckLvdsDevAttr(struct MipiCsiCntlr *cntlr, uint8_t devno, const LvdsDevAttr *pAttr)
271 {
272 int ret;
273
274 if ((pAttr->inputDataType < DATA_TYPE_RAW_8BIT) ||
275 (pAttr->inputDataType > DATA_TYPE_RAW_16BIT)) {
276 HDF_LOGE("%s: invalid dataType, must be in [%d, %d]", __func__, DATA_TYPE_RAW_8BIT, DATA_TYPE_RAW_16BIT);
277 return HDF_ERR_INVALID_PARAM;
278 }
279
280 if ((pAttr->wdrMode < HI_WDR_MODE_NONE) || (pAttr->wdrMode >= HI_WDR_MODE_BUTT)) {
281 HDF_LOGE("%s: invalid wdrMode, must be in [%d, %d)", __func__, HI_WDR_MODE_NONE, HI_WDR_MODE_BUTT);
282 return HDF_ERR_INVALID_PARAM;
283 }
284
285 if ((pAttr->syncMode < LVDS_SYNC_MODE_SOF) || (pAttr->syncMode >= LVDS_SYNC_MODE_BUTT)) {
286 HDF_LOGE("%s: invalid syncMode, must be in [%d, %d)", __func__, LVDS_SYNC_MODE_SOF, LVDS_SYNC_MODE_BUTT);
287 return HDF_ERR_INVALID_PARAM;
288 }
289
290 if (pAttr->vsyncAttr.syncType < LVDS_VSYNC_NORMAL ||
291 pAttr->vsyncAttr.syncType >= LVDS_VSYNC_BUTT) {
292 HDF_LOGE("%s: invalid vsync_code, must be in [%d, %d)", __func__, LVDS_VSYNC_NORMAL, LVDS_VSYNC_BUTT);
293 return HDF_ERR_INVALID_PARAM;
294 }
295
296 if (pAttr->fidAttr.fidType < LVDS_FID_NONE || pAttr->fidAttr.fidType >= LVDS_FID_BUTT) {
297 HDF_LOGE("%s: invalid fidType, must be in [%d, %d)", __func__, LVDS_FID_NONE, LVDS_FID_BUTT);
298 return HDF_ERR_INVALID_PARAM;
299 }
300
301 if (pAttr->fidAttr.outputFil != TRUE && pAttr->fidAttr.outputFil != FALSE) {
302 HDF_LOGE("%s: invalid outputFil, must be HI_TURE or FALSE", __func__);
303 return HDF_ERR_INVALID_PARAM;
304 }
305
306 if ((pAttr->dataEndian < LVDS_ENDIAN_LITTLE) || (pAttr->dataEndian >= LVDS_ENDIAN_BUTT)) {
307 HDF_LOGE("%s: invalid lvds_bit_endian, must be in [%d, %d)", __func__, LVDS_ENDIAN_LITTLE, LVDS_ENDIAN_BUTT);
308 return HDF_ERR_INVALID_PARAM;
309 }
310
311 if ((pAttr->syncCodeEndian < LVDS_ENDIAN_LITTLE) ||
312 (pAttr->syncCodeEndian >= LVDS_ENDIAN_BUTT)) {
313 HDF_LOGE("%s: invalid lvds_bit_endian, must be in [%d, %d)", __func__, LVDS_ENDIAN_LITTLE, LVDS_ENDIAN_BUTT);
314 return HDF_ERR_INVALID_PARAM;
315 }
316
317 ret = CheckLvdsWdrMode(pAttr);
318 if (ret != HDF_SUCCESS) {
319 HDF_LOGE("%s: CheckLvdsWdrMode failed!", __func__);
320 return HDF_FAILURE;
321 }
322
323 ret = CheckLaneId(cntlr, devno, INPUT_MODE_LVDS, pAttr->laneId);
324 if (ret != HDF_SUCCESS) {
325 HDF_LOGE("%s: CheckLaneId failed!", __func__);
326 return HDF_FAILURE;
327 }
328
329 return HDF_SUCCESS;
330 }
331
GetSyncCodes(const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM],unsigned short offset,unsigned short dst[][WDR_VC_NUM][SYNC_CODE_NUM])332 static void GetSyncCodes(const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM], unsigned short offset,
333 unsigned short dst[][WDR_VC_NUM][SYNC_CODE_NUM])
334 {
335 int i;
336 int j;
337 int k;
338
339 /*
340 * SONY DOL N frame and N+1 Frame has the different syncCode
341 * N+1 Frame FSET is 1, FSET is the 10th bit
342 */
343 for (i = 0; i < LVDS_LANE_NUM; i++) {
344 for (j = 0; j < WDR_VC_NUM; j++) {
345 for (k = 0; k < SYNC_CODE_NUM; k++) {
346 dst[i][j][k] = syncCode[i][j][k] + offset;
347 }
348 }
349 }
350 }
351
MipiSetLvdsSyncCodes(uint8_t devno,const LvdsDevAttr * pAttr,unsigned int totalLaneNum,unsigned int laneBitmap)352 static void MipiSetLvdsSyncCodes(uint8_t devno, const LvdsDevAttr *pAttr,
353 unsigned int totalLaneNum, unsigned int laneBitmap)
354 {
355 int ret;
356 unsigned short offset;
357 /* Sony DOL Mode, vmalloc and OsalMemAlloc are used in different os. */
358 unsigned short pNxtSyncCode[LVDS_LANE_NUM][WDR_VC_NUM][SYNC_CODE_NUM] = { 0 };
359
360 if (pAttr->wdrMode >= HI_WDR_MODE_DOL_2F && pAttr->wdrMode <= HI_WDR_MODE_DOL_4F) {
361 /* DATA_TYPE_RAW_10BIT or DATA_TYPE_RAW_8BIT needs to be confirmed. */
362 offset = (pAttr->inputDataType == DATA_TYPE_RAW_10BIT) ? SYNC_CODE_OFFSET8 : SYNC_CODE_OFFSET10;
363 /*
364 * SONY DOL N frame and N+1 Frame has the different syncCode
365 * N+1 Frame FSET is 1, FSET is the 10th bit
366 */
367 GetSyncCodes(pAttr->syncCode, offset, pNxtSyncCode);
368
369 /* Set Dony DOL Line Information */
370 if (pAttr->fidAttr.fidType == LVDS_FID_IN_DATA) {
371 MipiRxDrvSetDolLineInformation(devno, pAttr->wdrMode);
372 }
373 } else {
374 ret = memcpy_s(pNxtSyncCode, sizeof(pNxtSyncCode), &pAttr->syncCode, sizeof(pNxtSyncCode));
375 if (ret != EOK) {
376 HDF_LOGE("%s: [memcpy_s] failed", __func__);
377 return;
378 }
379 }
380
381 /* LVDS_CTRL Sync code */
382 MipiRxDrvSetLvdsSyncCode(devno, totalLaneNum, pAttr->laneId, pAttr->syncCode);
383 MipiRxDrvSetLvdsNxtSyncCode(devno, totalLaneNum, pAttr->laneId, pNxtSyncCode);
384
385 /* PHY Sync code detect setting */
386 MipiRxDrvSetPhySyncConfig(pAttr, laneBitmap, pNxtSyncCode);
387 }
388
MipiSetLvdsIntMask(uint8_t devno)389 static void MipiSetLvdsIntMask(uint8_t devno)
390 {
391 (void)memset_s(MipiRxHalGetLvdsErrIntCnt(devno), sizeof(LvdsErrIntCnt), 0, sizeof(LvdsErrIntCnt));
392 (void)memset_s(MipiRxHalGetAlignErrIntCnt(devno), sizeof(AlignErrIntCnt), 0, sizeof(AlignErrIntCnt));
393
394 #ifdef ENABLE_INT_MASK
395 MipiRxDrvSetMipiIntMask(devno);
396 MipiRxDrvSetLvdsCtrlIntMask(devno, LVDS_CTRL_INT_MASK);
397 MipiRxDrvSetAlignIntMask(devno, ALIGN0_INT_MASK);
398 #endif
399 }
400
MipiSetLvdsPhySyncCfg(const struct MipiCsiCntlr * cntlr,uint8_t devno,const LvdsDevAttr * pLvdsAttr,unsigned int laneBitmap,unsigned int laneNum)401 static void MipiSetLvdsPhySyncCfg(const struct MipiCsiCntlr *cntlr, uint8_t devno,
402 const LvdsDevAttr *pLvdsAttr, unsigned int laneBitmap, unsigned int laneNum)
403 {
404 /* phy lane config */
405 MipiRxDrvSetLinkLaneId(devno, INPUT_MODE_LVDS, pLvdsAttr->laneId, laneBitmap, cntlr->ctx.laneDivideMode);
406 MipiRxDrvSetMemCken(devno, TRUE);
407 MipiRxDrvSetClrCken(devno, TRUE);
408
409 MipiRxDrvSetPhyConfig(INPUT_MODE_LVDS, laneBitmap);
410
411 /* sync codes */
412 MipiSetLvdsSyncCodes(devno, pLvdsAttr, laneNum, laneBitmap);
413
414 MipiRxSetPhyRgLp0ModeEn(devno, 0);
415 MipiRxSetPhyRgLp1ModeEn(devno, 0);
416 }
417
MipiSetLvdsDevAttr(struct MipiCsiCntlr * cntlr,const ComboDevAttr * pComboDevAttr)418 static int MipiSetLvdsDevAttr(struct MipiCsiCntlr *cntlr, const ComboDevAttr *pComboDevAttr)
419 {
420 uint8_t devno;
421 const LvdsDevAttr *pLvdsAttr = NULL;
422 int ret;
423 unsigned int laneBitmap;
424 unsigned int laneNum;
425
426 devno = pComboDevAttr->devno;
427 pLvdsAttr = &pComboDevAttr->lvdsAttr;
428
429 if (!MipiIsHsModeCfged(cntlr)) {
430 HDF_LOGE("%s: mipi must set hs mode before set lvds attr!", __func__);
431 return HDF_FAILURE;
432 }
433
434 if (!MipiIsDevValid(cntlr, devno)) {
435 HDF_LOGE("%s: invalid combo dev num after set hs mode!", __func__);
436 return HDF_FAILURE;
437 }
438
439 ret = CheckLvdsDevAttr(cntlr, devno, pLvdsAttr);
440 if (ret != HDF_SUCCESS) {
441 HDF_LOGE("%s: CheckLvdsDevAttr failed!", __func__);
442 return HDF_FAILURE;
443 }
444
445 laneBitmap = MipiGetLaneBitmap(INPUT_MODE_LVDS, pLvdsAttr->laneId, &laneNum);
446
447 /* work mode */
448 MipiRxDrvSetWorkMode(devno, INPUT_MODE_LVDS);
449
450 /* image crop */
451 MipiRxDrvSetLvdsImageRect(devno, &pComboDevAttr->imgRect, laneNum);
452 MipiRxDrvSetLvdsCropEn(devno, TRUE);
453
454 /* data type & mode */
455 ret = MipiRxDrvSetLvdsWdrMode(devno, pLvdsAttr->wdrMode, &pLvdsAttr->vsyncAttr, &pLvdsAttr->fidAttr);
456 if (ret != HDF_SUCCESS) {
457 HDF_LOGE("%s: set lvds wdr mode failed!", __func__);
458 return HDF_FAILURE;
459 }
460
461 MipiRxDrvSetLvdsCtrlMode(devno, pLvdsAttr->syncMode, pLvdsAttr->inputDataType,
462 pLvdsAttr->dataEndian, pLvdsAttr->syncCodeEndian);
463
464 /* data rate */
465 MipiRxDrvSetLvdsDataRate(devno, pComboDevAttr->dataRate);
466 MipiSetLvdsPhySyncCfg(cntlr, devno, pLvdsAttr, laneBitmap, laneNum);
467 MipiSetLvdsIntMask(devno);
468
469 return HDF_SUCCESS;
470 }
471
CheckMipiDevAttr(struct MipiCsiCntlr * cntlr,uint8_t devno,const MipiDevAttr * pAttr)472 static int CheckMipiDevAttr(struct MipiCsiCntlr *cntlr, uint8_t devno, const MipiDevAttr *pAttr)
473 {
474 int ret;
475 int i;
476
477 if ((pAttr->inputDataType < DATA_TYPE_RAW_8BIT) || (pAttr->inputDataType >= DATA_TYPE_BUTT)) {
478 HDF_LOGE("%s: invalid inputDataType, must be in [%d, %d)", __func__, DATA_TYPE_RAW_8BIT, DATA_TYPE_BUTT);
479 return HDF_ERR_INVALID_PARAM;
480 }
481
482 if ((pAttr->wdrMode < HI_MIPI_WDR_MODE_NONE) || (pAttr->wdrMode >= HI_MIPI_WDR_MODE_BUTT)) {
483 HDF_LOGE("%s: invalid wdrMode, must be in [%d, %d)", __func__, HI_MIPI_WDR_MODE_NONE, HI_MIPI_WDR_MODE_BUTT);
484 return HDF_ERR_INVALID_PARAM;
485 }
486
487 if ((pAttr->wdrMode != HI_MIPI_WDR_MODE_NONE) &&
488 (pAttr->inputDataType >= DATA_TYPE_YUV420_8BIT_NORMAL)) {
489 HDF_LOGE("%s: It do not support wdr mode when inputDataType is yuv format!", __func__);
490 return HDF_ERR_INVALID_PARAM;
491 }
492
493 if (pAttr->wdrMode == HI_MIPI_WDR_MODE_DT) {
494 for (i = 0; i < WDR_VC_NUM; i++) {
495 /* dataType must be the CSI-2 reserve Type [0x38, 0x3f] */
496 if (pAttr->dataType[i] < 0x38 || pAttr->dataType[i] > 0x3f) {
497 HDF_LOGE("%s: invalid dataType[%d]: %hd, must be in [0x38, 0x3f]", __func__, i, pAttr->dataType[i]);
498 return HDF_ERR_INVALID_PARAM;
499 }
500 }
501 }
502
503 ret = CheckLaneId(cntlr, devno, INPUT_MODE_MIPI, pAttr->laneId);
504 if (ret != HDF_SUCCESS) {
505 HDF_LOGE("%s: CheckLaneId failed!", __func__);
506 return HDF_FAILURE;
507 }
508
509 return HDF_SUCCESS;
510 }
511
MipiSetDtAndMode(uint8_t devno,const MipiDevAttr * pAttr)512 static void MipiSetDtAndMode(uint8_t devno, const MipiDevAttr *pAttr)
513 {
514 DataType inputDataType;
515
516 inputDataType = pAttr->inputDataType;
517
518 MipiRxDrvSetDiDt(devno, inputDataType);
519 MipiRxDrvSetMipiYuvDt(devno, inputDataType);
520
521 if (pAttr->wdrMode == HI_MIPI_WDR_MODE_DT) {
522 MipiRxDrvSetMipiWdrUserDt(devno, inputDataType, pAttr->dataType);
523 } else if (pAttr->wdrMode == HI_MIPI_WDR_MODE_DOL) {
524 MipiRxDrvSetMipiDolId(devno, inputDataType, NULL);
525 }
526
527 MipiRxDrvSetMipiWdrMode(devno, pAttr->wdrMode);
528 }
529
MipiSetIntMask(uint8_t devno)530 static void MipiSetIntMask(uint8_t devno)
531 {
532 /* interrupt mask */
533 (void)memset_s(MipiRxHalGetMipiErrInt(devno), sizeof(MipiErrIntCnt), 0, sizeof(MipiErrIntCnt));
534 (void)memset_s(MipiRxHalGetAlignErrIntCnt(devno), sizeof(AlignErrIntCnt), 0, sizeof(AlignErrIntCnt));
535
536 #ifdef ENABLE_INT_MASK
537 MipiRxDrvSetMipiIntMask(devno);
538 MipiRxDrvSetMipiCtrlIntMask(devno, MIPI_CTRL_INT_MASK); /* 0x12f8 */
539 MipiRxDrvSetMipiPkt1IntMask(devno, MIPI_PKT_INT1_MASK); /* 0x1064 */
540 MipiRxDrvSetMipiPkt2IntMask(devno, MIPI_PKT_INT2_MASK); /* 0x1074 */
541 MipiRxDrvSetMipiFrameIntMask(devno, MIPI_FRAME_INT_MASK); /* 0x1084 */
542 MipiRxDrvSetAlignIntMask(devno, ALIGN0_INT_MASK); /* 0x18f8 */
543 #endif
544 }
545
MipiSetPhyCfg(struct MipiCsiCntlr * cntlr,const ComboDevAttr * pComboDevAttr)546 static void MipiSetPhyCfg(struct MipiCsiCntlr *cntlr, const ComboDevAttr *pComboDevAttr)
547 {
548 uint8_t devno;
549 unsigned int laneBitmap;
550 unsigned int laneNum;
551 const MipiDevAttr *pMipiAttr = NULL;
552
553 devno = pComboDevAttr->devno;
554 pMipiAttr = &pComboDevAttr->mipiAttr;
555
556 laneBitmap = MipiGetLaneBitmap(INPUT_MODE_MIPI, pMipiAttr->laneId, &laneNum);
557 MipiRxDrvSetLinkLaneId(devno, INPUT_MODE_MIPI, pMipiAttr->laneId, laneBitmap, cntlr->ctx.laneDivideMode);
558
559 if (cntlr->ctx.laneDivideMode == 0) {
560 MipiRxDrvSetLaneNum(devno, laneNum);
561 } else {
562 MipiRxDrvSetLaneNum(devno, laneNum);
563
564 if (devno == 1) {
565 if (laneBitmap == 0x3) {
566 laneBitmap = 0xa;
567 } else if (laneBitmap == 0x1) {
568 laneBitmap = 0x2;
569 } else if (laneBitmap == 0x2) {
570 laneBitmap = 0x8;
571 } else {
572 laneBitmap = 0xa;
573 }
574 }
575 }
576
577 cntlr->ctx.laneBitmap[devno] = laneBitmap;
578 MipiRxDrvSetPhyConfig(INPUT_MODE_MIPI, laneBitmap);
579 }
580
MipiSetMipiDevAttr(struct MipiCsiCntlr * cntlr,const ComboDevAttr * pComboDevAttr)581 static int MipiSetMipiDevAttr(struct MipiCsiCntlr *cntlr, const ComboDevAttr *pComboDevAttr)
582 {
583 uint8_t devno;
584 const MipiDevAttr *pMipiAttr = NULL;
585 int ret;
586
587 devno = pComboDevAttr->devno;
588 pMipiAttr = &pComboDevAttr->mipiAttr;
589
590 if (!MipiIsHsModeCfged(cntlr)) {
591 HDF_LOGE("%s: mipi must set hs mode before set mipi attr!", __func__);
592 return HDF_FAILURE;
593 }
594
595 if (!MipiIsDevValid(cntlr, devno)) {
596 HDF_LOGE("%s: invalid combo dev num after set hs mode!", __func__);
597 return HDF_FAILURE;
598 }
599
600 ret = CheckMipiDevAttr(cntlr, devno, pMipiAttr);
601 if (ret != HDF_SUCCESS) {
602 HDF_LOGE("%s: CheckMipiDevAttr failed!", __func__);
603 return HDF_FAILURE;
604 }
605
606 /* work mode */
607 MipiRxDrvSetWorkMode(devno, INPUT_MODE_MIPI);
608
609 /* image crop */
610 MipiRxDrvSetMipiImageRect(devno, &pComboDevAttr->imgRect);
611 MipiRxDrvSetMipiCropEn(devno, TRUE);
612
613 /* data type & mode */
614 MipiSetDtAndMode(devno, pMipiAttr);
615
616 /* data rate */
617 MipiRxDrvSetDataRate(devno, pComboDevAttr->dataRate);
618
619 /* phy lane config */
620 MipiSetPhyCfg(cntlr, pComboDevAttr);
621
622 MipiRxDrvSetMemCken(devno, TRUE);
623
624 MipiSetIntMask(devno);
625
626 return HDF_SUCCESS;
627 }
628
MipiSetCmosDevAttr(const ComboDevAttr * pComboDevAttr)629 static int MipiSetCmosDevAttr(const ComboDevAttr *pComboDevAttr)
630 {
631 uint8_t devno;
632 unsigned int laneBitmap = 0xf;
633 unsigned int phyId = 0;
634
635 devno = pComboDevAttr->devno;
636
637 if ((devno > CMOS_MAX_DEV_NUM) || (devno == 0)) {
638 HDF_LOGE("%s: invalid cmos devno(%hhu)!", __func__, devno);
639 return HDF_ERR_INVALID_PARAM;
640 }
641
642 if (devno == 1) {
643 phyId = 0;
644 laneBitmap = 0xf;
645 }
646
647 if (pComboDevAttr->inputMode != INPUT_MODE_BT656) {
648 if (devno == 1) {
649 MipiRxDrvSetCmosEn(phyId, 1);
650 }
651 MipiRxDrvSetPhyEn(laneBitmap);
652 MipiRxDrvSetPhyCfgEn(laneBitmap, 1);
653 MipiRxDrvSetLaneEn(laneBitmap);
654 MipiRxDrvSetPhyCilEn(laneBitmap, 1);
655 MipiRxDrvSetPhyCfgMode(INPUT_MODE_CMOS, laneBitmap); /* BT1120 may not need 698~700 */
656
657 MipiRxSetPhyRgLp0ModeEn(phyId, 0);
658 MipiRxSetPhyRgLp1ModeEn(phyId, 0);
659 }
660
661 return HDF_SUCCESS;
662 }
663
MipiSetComboDevAttr(struct MipiCsiCntlr * cntlr,const ComboDevAttr * pAttr)664 static int32_t MipiSetComboDevAttr(struct MipiCsiCntlr *cntlr, const ComboDevAttr *pAttr)
665 {
666 int32_t ret;
667
668 ret = MipiCheckCombDevAttr(pAttr);
669 if (ret != HDF_SUCCESS) {
670 HDF_LOGE("%s: mipi check comboDev attr failed!", __func__);
671 return HDF_FAILURE;
672 }
673
674 switch (pAttr->inputMode) {
675 case INPUT_MODE_LVDS:
676 case INPUT_MODE_SUBLVDS:
677 case INPUT_MODE_HISPI: {
678 ret = MipiSetLvdsDevAttr(cntlr, pAttr);
679 if (ret < 0) {
680 HDF_LOGE("%s: mipi set lvds attr failed!", __func__);
681 ret = HDF_FAILURE;
682 }
683 break;
684 }
685
686 case INPUT_MODE_MIPI: {
687 ret = MipiSetMipiDevAttr(cntlr, pAttr);
688 if (ret != HDF_SUCCESS) {
689 HDF_LOGE("%s: mipi set mipi attr failed!", __func__);
690 ret = HDF_FAILURE;
691 }
692 break;
693 }
694
695 case INPUT_MODE_CMOS:
696 case INPUT_MODE_BT601:
697 case INPUT_MODE_BT656:
698 case INPUT_MODE_BT1120: {
699 ret = MipiSetCmosDevAttr(pAttr);
700 if (ret != HDF_SUCCESS) {
701 HDF_LOGE("%s: mipi set cmos attr failed!", __func__);
702 ret = HDF_FAILURE;
703 }
704 break;
705 }
706
707 default: {
708 HDF_LOGE("%s: invalid input mode", __func__);
709 ret = HDF_FAILURE;
710 break;
711 }
712 }
713
714 return ret;
715 }
716
SetComboDevAttr(struct MipiCsiCntlr * cntlr,const ComboDevAttr * argp)717 static int32_t SetComboDevAttr(struct MipiCsiCntlr *cntlr, const ComboDevAttr *argp)
718 {
719 int32_t ret;
720 errno_t err;
721 uint8_t devno;
722
723 if (argp == NULL) {
724 HDF_LOGE("%s: NULL pointer \r", __func__);
725 return HDF_ERR_INVALID_OBJECT;
726 }
727
728 devno = argp->devno;
729 OsalSpinLock(&cntlr->ctxLock);
730 cntlr->ctx.devCfged[devno] = true;
731 err = memcpy_s(&cntlr->ctx.comboDevAttr[devno], sizeof(ComboDevAttr), argp, sizeof(ComboDevAttr));
732 if (err != EOK) {
733 cntlr->ctx.devCfged[devno] = false;
734 HDF_LOGE("%s: [memcpy_s] failed.", __func__);
735 ret = HDF_FAILURE;
736 } else {
737 ret = HDF_SUCCESS;
738 }
739 OsalSpinUnlock(&cntlr->ctxLock);
740
741 return ret;
742 }
743
Hi35xxSetComboDevAttr(struct MipiCsiCntlr * cntlr,ComboDevAttr * pAttr)744 static int32_t Hi35xxSetComboDevAttr(struct MipiCsiCntlr *cntlr, ComboDevAttr *pAttr)
745 {
746 int32_t ret;
747
748 ret = MipiSetComboDevAttr(cntlr, pAttr);
749 if (ret == HDF_SUCCESS) {
750 ret = SetComboDevAttr(cntlr, pAttr);
751 } else {
752 HDF_LOGE("%s: [MipiSetComboDevAttr] failed.", __func__);
753 }
754
755 return ret;
756 }
757
Hi35xxSetExtDataType(struct MipiCsiCntlr * cntlr,ExtDataType * dataType)758 static int32_t Hi35xxSetExtDataType(struct MipiCsiCntlr *cntlr, ExtDataType *dataType)
759 {
760 unsigned int i;
761 uint8_t devno;
762 InputMode inputMode;
763 DataType inputDataType;
764
765 devno = dataType->devno;
766
767 if (devno >= COMBO_DEV_MAX_NUM) {
768 HDF_LOGE("%s: invalid mipi dev number(%hhu).", __func__, devno);
769 return HDF_ERR_INVALID_PARAM;
770 }
771
772 if (!MipiIsDevCfged(cntlr, devno)) {
773 HDF_LOGE("%s: MIPI device %hhu has not beed configured", __func__, devno);
774 return HDF_FAILURE;
775 }
776
777 OsalSpinLock(&cntlr->ctxLock);
778 inputMode = cntlr->ctx.comboDevAttr[devno].inputMode;
779 inputDataType = cntlr->ctx.comboDevAttr[devno].mipiAttr.inputDataType;
780 OsalSpinUnlock(&cntlr->ctxLock);
781
782 if (inputMode != INPUT_MODE_MIPI) {
783 HDF_LOGE("%s: devno: %hhu, input mode: %d, not support set data type", __func__, devno, inputMode);
784 return HDF_ERR_INVALID_PARAM;
785 }
786
787 if (dataType->num > MAX_EXT_DATA_TYPE_NUM) {
788 HDF_LOGE("%s: invalid ext data type num(%u)", __func__, dataType->num);
789 return HDF_ERR_INVALID_PARAM;
790 }
791
792 for (i = 0; i < dataType->num; i++) {
793 if (dataType->extDataBitWidth[i] < MIPI_RX_MIN_EXT_DATA_TYPE_BIT_WIDTH ||
794 dataType->extDataBitWidth[i] > MIPI_RX_MAX_EXT_DATA_TYPE_BIT_WIDTH) {
795 HDF_LOGE("%s: invalid ext data bit width(%u)", __func__, dataType->extDataBitWidth[i]);
796 return HDF_ERR_INVALID_PARAM;
797 }
798
799 if (dataType->extDataBitWidth[i] % 2 != 0) { /* 2:even check */
800 HDF_LOGE("%s: invalid ext data bit width(%u),must be even value", __func__, dataType->extDataBitWidth[i]);
801 return HDF_ERR_INVALID_PARAM;
802 }
803 }
804
805 MipiRxDrvSetExtDataType(dataType, inputDataType);
806
807 return HDF_SUCCESS;
808 }
809
Hi35xxSetPhyCmvmode(struct MipiCsiCntlr * cntlr,uint8_t devno,PhyCmvMode cmvMode)810 static int32_t Hi35xxSetPhyCmvmode(struct MipiCsiCntlr *cntlr, uint8_t devno, PhyCmvMode cmvMode)
811 {
812 InputMode inputMode;
813 unsigned int laneBitMap;
814
815 if (devno >= COMBO_DEV_MAX_NUM) {
816 HDF_LOGE("%s: invalid mipi dev number(%hhu).", __func__, devno);
817 return HDF_ERR_INVALID_PARAM;
818 }
819
820 if ((cmvMode < PHY_CMV_GE1200MV) || (cmvMode >= PHY_CMV_BUTT)) {
821 HDF_LOGE("%s: invalid common mode voltage mode: %d, must be int [%d, %d)", __func__,
822 cmvMode, PHY_CMV_GE1200MV, PHY_CMV_BUTT);
823 return HDF_ERR_INVALID_PARAM;
824 }
825
826 if (!MipiIsDevCfged(cntlr, devno)) {
827 HDF_LOGE("%s: MIPI device %hhu has not beed configured", __func__, devno);
828 return HDF_ERR_INVALID_PARAM;
829 }
830
831 OsalSpinLock(&cntlr->ctxLock);
832 inputMode = cntlr->ctx.comboDevAttr[devno].inputMode;
833 laneBitMap = cntlr->ctx.laneBitmap[devno];
834 OsalSpinUnlock(&cntlr->ctxLock);
835
836 if (inputMode != INPUT_MODE_MIPI &&
837 inputMode != INPUT_MODE_SUBLVDS &&
838 inputMode != INPUT_MODE_LVDS &&
839 inputMode != INPUT_MODE_HISPI) {
840 HDF_LOGE("%s: devno: %hhu, input mode: %d, not support set common voltage mode", __func__, devno, inputMode);
841 return HDF_ERR_INVALID_PARAM;
842 }
843
844 MipiRxDrvSetPhyCmvmode(inputMode, cmvMode, laneBitMap);
845
846 return HDF_SUCCESS;
847 }
848
Hi35xxResetSensor(struct MipiCsiCntlr * cntlr,uint8_t snsResetSource)849 static int32_t Hi35xxResetSensor(struct MipiCsiCntlr *cntlr, uint8_t snsResetSource)
850 {
851 (void)cntlr;
852 if (snsResetSource >= SNS_MAX_RST_SOURCE_NUM) {
853 HDF_LOGE("%s: invalid snsResetSource(%hhu).", __func__, snsResetSource);
854 return HDF_ERR_INVALID_PARAM;
855 }
856
857 SensorDrvReset(snsResetSource);
858
859 return HDF_SUCCESS;
860 }
861
Hi35xxUnresetSensor(struct MipiCsiCntlr * cntlr,uint8_t snsResetSource)862 static int32_t Hi35xxUnresetSensor(struct MipiCsiCntlr *cntlr, uint8_t snsResetSource)
863 {
864 (void)cntlr;
865 if (snsResetSource >= SNS_MAX_RST_SOURCE_NUM) {
866 HDF_LOGE("%s: invalid snsResetSource(%hhu).", __func__, snsResetSource);
867 return HDF_ERR_INVALID_PARAM;
868 }
869
870 SensorDrvUnreset(snsResetSource);
871
872 return HDF_SUCCESS;
873 }
874
Hi35xxResetRx(struct MipiCsiCntlr * cntlr,uint8_t comboDev)875 static int32_t Hi35xxResetRx(struct MipiCsiCntlr *cntlr, uint8_t comboDev)
876 {
877 (void)cntlr;
878 if (comboDev >= MIPI_RX_MAX_DEV_NUM) {
879 HDF_LOGE("%s: invalid comboDev num(%hhu).", __func__, comboDev);
880 return HDF_ERR_INVALID_PARAM;
881 }
882
883 MipiRxDrvCoreReset(comboDev);
884
885 return HDF_SUCCESS;
886 }
887
Hi35xxUnresetRx(struct MipiCsiCntlr * cntlr,uint8_t comboDev)888 static int32_t Hi35xxUnresetRx(struct MipiCsiCntlr *cntlr, uint8_t comboDev)
889 {
890 (void)cntlr;
891 if (comboDev >= MIPI_RX_MAX_DEV_NUM) {
892 HDF_LOGE("%s: invalid comboDev num(%hhu).", __func__, comboDev);
893 return HDF_ERR_INVALID_PARAM;
894 }
895
896 MipiRxDrvCoreUnreset(comboDev);
897
898 return HDF_SUCCESS;
899 }
900
MipiSetDevValid(struct MipiCsiCntlr * cntlr,LaneDivideMode mode)901 static void MipiSetDevValid(struct MipiCsiCntlr *cntlr, LaneDivideMode mode)
902 {
903 switch (mode) {
904 case LANE_DIVIDE_MODE_0:
905 cntlr->ctx.devValid[0] = true;
906 break;
907 case LANE_DIVIDE_MODE_1:
908 cntlr->ctx.devValid[0] = true;
909 cntlr->ctx.devValid[1] = true;
910 break;
911 default:
912 break;
913 }
914 }
915
Hi35xxSetHsMode(struct MipiCsiCntlr * cntlr,LaneDivideMode laneDivideMode)916 static int32_t Hi35xxSetHsMode(struct MipiCsiCntlr *cntlr, LaneDivideMode laneDivideMode)
917 {
918 if ((laneDivideMode < LANE_DIVIDE_MODE_0) ||
919 (laneDivideMode >= LANE_DIVIDE_MODE_BUTT)) {
920 HDF_LOGE("%s: invalid laneDivideMode(%d), must be in [%d, %d)", __func__,
921 laneDivideMode, LANE_DIVIDE_MODE_0, LANE_DIVIDE_MODE_BUTT);
922 return HDF_ERR_INVALID_PARAM;
923 }
924
925 MipiRxDrvSetHsMode(laneDivideMode);
926
927 OsalSpinLock(&cntlr->ctxLock);
928 cntlr->ctx.laneDivideMode = laneDivideMode;
929 cntlr->ctx.hsModeCfged = true;
930 (void)memset_s(cntlr->ctx.devValid, sizeof(cntlr->ctx.devValid), 0, sizeof(cntlr->ctx.devValid));
931 MipiSetDevValid(cntlr, laneDivideMode);
932 OsalSpinUnlock(&cntlr->ctxLock);
933
934 return HDF_SUCCESS;
935 }
936
Hi35xxEnableClock(struct MipiCsiCntlr * cntlr,uint8_t comboDev)937 static int32_t Hi35xxEnableClock(struct MipiCsiCntlr *cntlr, uint8_t comboDev)
938 {
939 (void)cntlr;
940 if (comboDev >= MIPI_RX_MAX_DEV_NUM) {
941 HDF_LOGE("%s: invalid comboDev num(%hhu).", __func__, comboDev);
942 return HDF_ERR_INVALID_PARAM;
943 }
944
945 MipiRxDrvEnableClock(comboDev);
946
947 return HDF_SUCCESS;
948 }
949
Hi35xxDisableClock(struct MipiCsiCntlr * cntlr,uint8_t comboDev)950 static int32_t Hi35xxDisableClock(struct MipiCsiCntlr *cntlr, uint8_t comboDev)
951 {
952 (void)cntlr;
953 if (comboDev >= MIPI_RX_MAX_DEV_NUM) {
954 HDF_LOGE("%s: invalid comboDev num(%hhu).", __func__, comboDev);
955 return HDF_ERR_INVALID_PARAM;
956 }
957
958 MipiRxDrvDisableClock(comboDev);
959
960 return HDF_SUCCESS;
961 }
962
Hi35xxEnableSensorClock(struct MipiCsiCntlr * cntlr,uint8_t snsClkSource)963 static int32_t Hi35xxEnableSensorClock(struct MipiCsiCntlr *cntlr, uint8_t snsClkSource)
964 {
965 (void)cntlr;
966 if (snsClkSource >= SNS_MAX_CLK_SOURCE_NUM) {
967 HDF_LOGE("%s: invalid snsClkSource(%hhu).", __func__, snsClkSource);
968 return HDF_ERR_INVALID_PARAM;
969 }
970
971 SensorDrvEnableClock(snsClkSource);
972
973 return HDF_SUCCESS;
974 }
975
Hi35xxDisableSensorClock(struct MipiCsiCntlr * cntlr,uint8_t snsClkSource)976 static int32_t Hi35xxDisableSensorClock(struct MipiCsiCntlr *cntlr, uint8_t snsClkSource)
977 {
978 (void)cntlr;
979 if (snsClkSource >= SNS_MAX_CLK_SOURCE_NUM) {
980 HDF_LOGE("%s: invalid snsClkSource(%hhu).", __func__, snsClkSource);
981 return HDF_ERR_INVALID_PARAM;
982 }
983
984 SensorDrvDisableClock(snsClkSource);
985
986 return HDF_SUCCESS;
987 }
988
989 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
Hi35xxGetMipiDevCtx(struct MipiCsiCntlr * cntlr,MipiDevCtx * ctx)990 static void Hi35xxGetMipiDevCtx(struct MipiCsiCntlr *cntlr, MipiDevCtx *ctx)
991 {
992 OsalSpinLock(&cntlr->ctxLock);
993 *ctx = cntlr->ctx;
994 OsalSpinUnlock(&cntlr->ctxLock);
995 }
996
Hi35xxGetPhyErrIntCnt(struct MipiCsiCntlr * cntlr,unsigned int phyId,PhyErrIntCnt * errInfo)997 static void Hi35xxGetPhyErrIntCnt(struct MipiCsiCntlr *cntlr, unsigned int phyId, PhyErrIntCnt *errInfo)
998 {
999 int32_t ret;
1000 PhyErrIntCnt *err = NULL;
1001
1002 (void)cntlr;
1003 err = MipiRxHalGetPhyErrIntCnt(phyId);
1004 if (err == NULL) {
1005 HDF_LOGE("%s: [MipiRxHalGetPhyErrIntCnt] failed.", __func__);
1006 return;
1007 }
1008 ret = memcpy_s(errInfo, sizeof(PhyErrIntCnt), err, sizeof(PhyErrIntCnt));
1009 if (ret != EOK) {
1010 HDF_LOGE("%s: [memcpy_s] failed.", __func__);
1011 } else {
1012 HDF_LOGI("%s: success.", __func__);
1013 }
1014 }
1015
Hi35xxGetMipiErrInt(struct MipiCsiCntlr * cntlr,unsigned int phyId,MipiErrIntCnt * errInfo)1016 static void Hi35xxGetMipiErrInt(struct MipiCsiCntlr *cntlr, unsigned int phyId, MipiErrIntCnt *errInfo)
1017 {
1018 int32_t ret;
1019 MipiErrIntCnt *err = NULL;
1020
1021 (void)cntlr;
1022 err = MipiRxHalGetMipiErrInt(phyId);
1023 if (err == NULL) {
1024 HDF_LOGE("%s: [MipiRxHalGetMipiErrInt] failed.", __func__);
1025 return;
1026 }
1027 ret = memcpy_s(errInfo, sizeof(MipiErrIntCnt), err, sizeof(MipiErrIntCnt));
1028 if (ret != EOK) {
1029 HDF_LOGE("%s: [memcpy_s] failed.", __func__);
1030 } else {
1031 HDF_LOGI("%s: success.", __func__);
1032 }
1033 }
1034
Hi35xxGetLvdsErrIntCnt(struct MipiCsiCntlr * cntlr,unsigned int phyId,LvdsErrIntCnt * errInfo)1035 static void Hi35xxGetLvdsErrIntCnt(struct MipiCsiCntlr *cntlr, unsigned int phyId, LvdsErrIntCnt *errInfo)
1036 {
1037 int32_t ret;
1038 LvdsErrIntCnt *err = NULL;
1039
1040 (void)cntlr;
1041 err = MipiRxHalGetLvdsErrIntCnt(phyId);
1042 if (err == NULL) {
1043 HDF_LOGE("%s: [MipiRxHalGetLvdsErrIntCnt] failed.", __func__);
1044 return;
1045 }
1046 ret = memcpy_s(errInfo, sizeof(LvdsErrIntCnt), err, sizeof(LvdsErrIntCnt));
1047 if (ret != EOK) {
1048 HDF_LOGE("%s: [memcpy_s] failed.", __func__);
1049 } else {
1050 HDF_LOGI("%s: success.", __func__);
1051 }
1052 }
1053
Hi35xxGetAlignErrIntCnt(struct MipiCsiCntlr * cntlr,unsigned int phyId,AlignErrIntCnt * errInfo)1054 static void Hi35xxGetAlignErrIntCnt(struct MipiCsiCntlr *cntlr, unsigned int phyId, AlignErrIntCnt *errInfo)
1055 {
1056 int32_t ret;
1057 AlignErrIntCnt *err = NULL;
1058
1059 (void)cntlr;
1060 err = MipiRxHalGetAlignErrIntCnt(phyId);
1061 if (err == NULL) {
1062 HDF_LOGE("%s: [MipiRxHalGetAlignErrIntCnt] failed.", __func__);
1063 return;
1064 }
1065 ret = memcpy_s(errInfo, sizeof(AlignErrIntCnt), err, sizeof(AlignErrIntCnt));
1066 if (ret != EOK) {
1067 HDF_LOGE("%s: [memcpy_s] failed.", __func__);
1068 } else {
1069 HDF_LOGI("%s: success.", __func__);
1070 }
1071 }
1072
Hi35xxGetPhyData(struct MipiCsiCntlr * cntlr,int phyId,int laneId,unsigned int * laneData)1073 static void Hi35xxGetPhyData(struct MipiCsiCntlr *cntlr, int phyId, int laneId, unsigned int *laneData)
1074 {
1075 (void)cntlr;
1076 *laneData = MipiRxDrvGetPhyData(phyId, laneId);
1077 }
1078
Hi35xxGetPhyMipiLinkData(struct MipiCsiCntlr * cntlr,int phyId,int laneId,unsigned int * laneData)1079 static void Hi35xxGetPhyMipiLinkData(struct MipiCsiCntlr *cntlr, int phyId, int laneId, unsigned int *laneData)
1080 {
1081 (void)cntlr;
1082 *laneData = MipiRxDrvGetPhyMipiLinkData(phyId, laneId);
1083 }
1084
Hi35xxGetPhyLvdsLinkData(struct MipiCsiCntlr * cntlr,int phyId,int laneId,unsigned int * laneData)1085 static void Hi35xxGetPhyLvdsLinkData(struct MipiCsiCntlr *cntlr, int phyId, int laneId, unsigned int *laneData)
1086 {
1087 (void)cntlr;
1088 *laneData = MipiRxDrvGetPhyLvdsLinkData(phyId, laneId);
1089 }
1090
Hi35xxGetMipiImgsizeStatis(struct MipiCsiCntlr * cntlr,uint8_t devno,short vc,ImgSize * pSize)1091 static void Hi35xxGetMipiImgsizeStatis(struct MipiCsiCntlr *cntlr, uint8_t devno, short vc, ImgSize *pSize)
1092 {
1093 (void)cntlr;
1094 MipiRxDrvGetMipiImgsizeStatis(devno, vc, pSize);
1095 }
1096
Hi35xxGetLvdsImgsizeStatis(struct MipiCsiCntlr * cntlr,uint8_t devno,short vc,ImgSize * pSize)1097 static void Hi35xxGetLvdsImgsizeStatis(struct MipiCsiCntlr *cntlr, uint8_t devno, short vc, ImgSize *pSize)
1098 {
1099 (void)cntlr;
1100 MipiRxDrvGetLvdsImgsizeStatis(devno, vc, pSize);
1101 }
1102
Hi35xxGetLvdsLaneImgsizeStatis(struct MipiCsiCntlr * cntlr,uint8_t devno,short lane,ImgSize * pSize)1103 static void Hi35xxGetLvdsLaneImgsizeStatis(struct MipiCsiCntlr *cntlr, uint8_t devno, short lane, ImgSize *pSize)
1104 {
1105 (void)cntlr;
1106 MipiRxDrvGetLvdsLaneImgsizeStatis(devno, lane, pSize);
1107 }
1108
1109 static struct MipiCsiCntlrDebugMethod g_debugMethod = {
1110 .getMipiDevCtx = Hi35xxGetMipiDevCtx,
1111 .getPhyErrIntCnt = Hi35xxGetPhyErrIntCnt,
1112 .getMipiErrInt = Hi35xxGetMipiErrInt,
1113 .getLvdsErrIntCnt = Hi35xxGetLvdsErrIntCnt,
1114 .getAlignErrIntCnt = Hi35xxGetAlignErrIntCnt,
1115 .getPhyData = Hi35xxGetPhyData,
1116 .getPhyMipiLinkData = Hi35xxGetPhyMipiLinkData,
1117 .getPhyLvdsLinkData = Hi35xxGetPhyLvdsLinkData,
1118 .getMipiImgsizeStatis = Hi35xxGetMipiImgsizeStatis,
1119 .getLvdsImgsizeStatis = Hi35xxGetLvdsImgsizeStatis,
1120 .getLvdsLaneImgsizeStatis = Hi35xxGetLvdsLaneImgsizeStatis
1121 };
1122 #endif
1123
1124 static struct MipiCsiCntlr g_mipiCsi = {
1125 .devNo = 0
1126 };
1127
1128 static struct MipiCsiCntlrMethod g_method = {
1129 .setComboDevAttr = Hi35xxSetComboDevAttr,
1130 .setPhyCmvmode = Hi35xxSetPhyCmvmode,
1131 .setExtDataType = Hi35xxSetExtDataType,
1132 .setHsMode = Hi35xxSetHsMode,
1133 .enableClock = Hi35xxEnableClock,
1134 .disableClock = Hi35xxDisableClock,
1135 .resetRx = Hi35xxResetRx,
1136 .unresetRx = Hi35xxUnresetRx,
1137 .enableSensorClock = Hi35xxEnableSensorClock,
1138 .disableSensorClock = Hi35xxDisableSensorClock,
1139 .resetSensor = Hi35xxResetSensor,
1140 .unresetSensor = Hi35xxUnresetSensor
1141 };
1142
Hi35xxMipiCsiInit(struct HdfDeviceObject * device)1143 static int32_t Hi35xxMipiCsiInit(struct HdfDeviceObject *device)
1144 {
1145 int32_t ret;
1146
1147 g_mipiCsi.priv = NULL;
1148 g_mipiCsi.ops = &g_method;
1149 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
1150 g_mipiCsi.debugs = &g_debugMethod;
1151 #endif
1152 ret = MipiCsiRegisterCntlr(&g_mipiCsi, device);
1153 if (ret != HDF_SUCCESS) {
1154 HDF_LOGE("%s: [MipiCsiRegisterCntlr] failed!", __func__);
1155 return ret;
1156 }
1157
1158 ret = MipiRxDrvInit();
1159 if (ret != HDF_SUCCESS) {
1160 HDF_LOGE("%s: [MipiRxDrvInit] failed.", __func__);
1161 return ret;
1162 }
1163 #ifdef MIPICSI_VFS_SUPPORT
1164 ret = MipiCsiDevModuleInit(g_mipiCsi.devNo);
1165 if (ret != HDF_SUCCESS) {
1166 HDF_LOGE("%s: [MipiCsiDevModuleInit] failed!", __func__);
1167 return ret;
1168 }
1169 #endif
1170
1171 OsalSpinInit(&g_mipiCsi.ctxLock);
1172 HDF_LOGI("%s: Mipi Csi init success.", __func__);
1173 return ret;
1174 }
1175
Hi35xxMipiCsiRelease(struct HdfDeviceObject * device)1176 static void Hi35xxMipiCsiRelease(struct HdfDeviceObject *device)
1177 {
1178 struct MipiCsiCntlr *cntlr = NULL;
1179
1180 HDF_LOGI("%s: enter!", __func__);
1181 if (device == NULL) {
1182 HDF_LOGE("%s: device is NULL.", __func__);
1183 return;
1184 }
1185 cntlr = MipiCsiCntlrFromDevice(device);
1186 if (cntlr == NULL) {
1187 HDF_LOGE("%s: cntlr is NULL.", __func__);
1188 return;
1189 }
1190
1191 OsalSpinDestroy(&cntlr->ctxLock);
1192 #ifdef MIPICSI_VFS_SUPPORT
1193 MipiCsiDevModuleExit(cntlr->devNo);
1194 #endif
1195 MipiRxDrvExit();
1196 MipiCsiUnregisterCntlr(&g_mipiCsi);
1197 g_mipiCsi.priv = NULL;
1198 }
1199
1200 struct HdfDriverEntry g_mipiCsiDriverEntry = {
1201 .moduleVersion = 1,
1202 .Init = Hi35xxMipiCsiInit,
1203 .Release = Hi35xxMipiCsiRelease,
1204 .moduleName = "HDF_MIPI_RX",
1205 };
1206 HDF_INIT(g_mipiCsiDriverEntry);
1207
1208 #ifdef __cplusplus
1209 #if __cplusplus
1210 }
1211
1212 #endif
1213 #endif /* End of #ifdef __cplusplus */
1214