1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #ifndef PWM_HI35XX_H
17 #define PWM_HI35XX_H
18 #include "hdf_base.h"
19
20 #define PWM_CLK_HZ 3000000 // 3MHz
21 #define PWM_CLK_PERIOD 333 // 333ns
22
23 #define PWM_MAX_HZ 1500000 // 1.5MHz
24 #define PWM_MIN_PERIOD 666 // 666ns
25
26 #define PWM_MIN_HZ 0.045 // 0.045Hz
27 #define PWM_MAX_PERIOD 22222222222 // 22222222222ns > 4294967295ns (UINT32_MAX)
28
29 #define PWM_ENABLE 1
30 #define PWM_DISABLE 0
31
32 #define PWM_INV_OFFSET 1
33 #define PWM_KEEP_OFFSET 2
34
35 #define PWM_DEFAULT_PERIOD 0x3E7 // 999
36 #define PWM_DEFAULT_POLARITY 0
37 #define PWM_DEFAULT_DUTY_CYCLE 0x14D // 333
38
39 #define PWM_DUMPER_NAME_PREFIX "pwm_dumper_"
40 #define PWM_DUMPER_NAME_LEN 64
41
42 #define PWM_CFG1_SHIFT 0x4 // Offset Address 0x4
43 #define PWM_CFG2_SHIFT 0x8 // Offset Address 0x8
44 #define PWM_CTRL_SHIFT 0xC // Offset Address 0xC
45 #define PWM_STATE0_SHIFT 0x10 // Offset Address 0x10
46 #define PWM_STATE1_SHIFT 0x14 // Offset Address 0x14
47 #define PWM_STATE2_SHIFT 0x18 // Offset Address 0x18
48
49 struct HiPwmRegs {
50 volatile uint32_t cfg0;
51 volatile uint32_t cfg1;
52 volatile uint32_t cfg2;
53 volatile uint32_t ctrl;
54 volatile uint32_t state0;
55 volatile uint32_t state1;
56 volatile uint32_t state2;
57 };
58
HiPwmDisable(struct HiPwmRegs * reg)59 static inline void HiPwmDisable(struct HiPwmRegs *reg)
60 {
61 reg->ctrl &= ~1;
62 }
63
HiPwmAlwaysOutput(struct HiPwmRegs * reg)64 static inline void HiPwmAlwaysOutput(struct HiPwmRegs *reg)
65 {
66 /* keep the pwm always output */
67 reg->ctrl |= ((1 << PWM_KEEP_OFFSET) | PWM_ENABLE);
68 }
69
HiPwmOutputNumberSquareWaves(struct HiPwmRegs * reg,uint32_t number)70 static inline void HiPwmOutputNumberSquareWaves(struct HiPwmRegs *reg, uint32_t number)
71 {
72 uint32_t mask;
73
74 /* pwm output number square waves */
75 reg->cfg2 = number;
76 mask = ~(1 << PWM_KEEP_OFFSET);
77 reg->ctrl &= mask;
78 reg->ctrl |= PWM_ENABLE;
79 }
80
HiPwmSetPolarity(struct HiPwmRegs * reg,uint8_t polarity)81 static inline void HiPwmSetPolarity(struct HiPwmRegs *reg, uint8_t polarity)
82 {
83 uint32_t mask;
84
85 mask = ~(1 << PWM_INV_OFFSET);
86 reg->ctrl &= mask;
87 reg->ctrl |= (polarity << PWM_INV_OFFSET);
88 }
89
HiPwmSetPeriod(struct HiPwmRegs * reg,uint32_t period)90 static inline void HiPwmSetPeriod(struct HiPwmRegs *reg, uint32_t period)
91 {
92 reg->cfg0 = period / PWM_CLK_PERIOD;
93 }
94
HiPwmSetDuty(struct HiPwmRegs * reg,uint32_t duty)95 static inline void HiPwmSetDuty(struct HiPwmRegs *reg, uint32_t duty)
96 {
97 reg->cfg1 = duty / PWM_CLK_PERIOD;
98 }
99
100 #endif /* PWM_HI35XX_H */
101