1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __ACODEC_H__ 17 #define __ACODEC_H__ 18 19 #define IOC_TYPE_ACODEC 'A' 20 21 typedef enum hiACODEC_FS_E { 22 ACODEC_FS_8000 = 0x1, 23 ACODEC_FS_11025 = 0x2, 24 ACODEC_FS_12000 = 0x3, 25 ACODEC_FS_16000 = 0x4, 26 ACODEC_FS_22050 = 0x5, 27 ACODEC_FS_24000 = 0x6, 28 ACODEC_FS_32000 = 0x7, 29 ACODEC_FS_44100 = 0x8, 30 ACODEC_FS_48000 = 0x9, 31 ACODEC_FS_64000 = 0xa, 32 ACODEC_FS_96000 = 0xb, 33 34 ACODEC_FS_BUTT = 0x1c, 35 } ACODEC_FS_E; 36 37 typedef struct { 38 /* volume control, 0x00~0x7e, 0x7F:mute */ 39 unsigned int vol_ctrl; 40 /* adc/dac mute control, 1:mute, 0:unmute */ 41 unsigned int vol_ctrl_mute; 42 } ACODEC_VOL_CTRL; 43 44 typedef enum hiACODEC_IOCTL_E { 45 IOC_NR_SOFT_RESET_CTRL = 0x0, 46 47 IOC_NR_SET_INPUT_VOL, 48 IOC_NR_SET_OUTPUT_VOL, 49 IOC_NR_GET_INPUT_VOL, 50 IOC_NR_GET_OUTPUT_VOL, 51 52 IOC_NR_SET_I2S1_FS, 53 IOC_NR_SET_MIXER_MIC, 54 IOC_NR_SEL_DAC_CLK, 55 IOC_NR_SEL_ADC_CLK, 56 IOC_NR_SEL_ANA_MCLK, 57 IOC_NR_SET_GAIN_MICL, 58 IOC_NR_SET_GAIN_MICR, 59 IOC_NR_SET_DACL_VOL, 60 IOC_NR_SET_DACR_VOL, 61 IOC_NR_SET_ADCL_VOL, 62 IOC_NR_SET_ADCR_VOL, 63 IOC_NR_SET_MICL_MUTE, 64 IOC_NR_SET_MICR_MUTE, 65 IOC_NR_SET_DACL_MUTE, 66 IOC_NR_SET_DACR_MUTE, 67 IOC_NR_BOOSTL_ENABLE, 68 IOC_NR_BOOSTR_ENABLE, 69 70 IOC_NR_GET_GAIN_MICL, 71 IOC_NR_GET_GAIN_MICR, 72 IOC_NR_GET_DACL_VOL, 73 IOC_NR_GET_DACR_VOL, 74 IOC_NR_GET_ADCL_VOL, 75 IOC_NR_GET_ADCR_VOL, 76 77 IOC_NR_SET_PD_DACL, 78 IOC_NR_SET_PD_DACR, 79 IOC_NR_SET_PD_ADCL, 80 IOC_NR_SET_PD_ADCR, 81 IOC_NR_SET_PD_LINEINL, 82 IOC_NR_SET_PD_LINEINR, 83 84 IOC_NR_SET_DAC_DE_EMPHASIS, 85 IOC_NR_SET_ADC_HP_FILTER, 86 87 IOC_NR_SET_I2S1_DATAWIDTH, 88 89 IOC_NR_DACL_SEL_TRACK, 90 IOC_NR_DACR_SEL_TRACK, 91 IOC_NR_ADCL_SEL_TRACK, 92 IOC_NR_ADCR_SEL_TRACK, 93 } ACODEC_IOCTL_E; 94 95 typedef enum hiACODEC_MIXER_E { 96 ACODEC_MIXER_IN0 = 0x0, /* HI3516CV500/HI3516DV300 Unsupport IN0. */ 97 ACODEC_MIXER_IN1 = 0x1, 98 ACODEC_MIXER_IN_D = 0x2, 99 100 ACODEC_MIXER_BUTT, 101 } ACODEC_MIXER_E; 102 103 /* reset the audio code to the default config */ 104 #define ACODEC_SOFT_RESET_CTRL \ 105 _IO(IOC_TYPE_ACODEC, IOC_NR_SOFT_RESET_CTRL) 106 /* ACODEC_FS_E */ 107 #define ACODEC_SET_I2S1_FS \ 108 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_I2S1_FS, unsigned int) 109 110 /* select the micpga's input, micin linein, or differential input(ACODEC_MIXER_E) */ 111 #define ACODEC_SET_MIXER_MIC \ 112 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_MIXER_MIC, unsigned int) 113 /* Input volume control(left channel) ACODEC_VOL_CTRL */ 114 #define ACODEC_SET_ADCL_VOL \ 115 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_ADCL_VOL, ACODEC_VOL_CTRL) 116 /* Input volume control(right channel) ACODEC_VOL_CTRL */ 117 #define ACODEC_SET_ADCR_VOL \ 118 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_ADCR_VOL, ACODEC_VOL_CTRL) 119 /* Output volume control(left channel) ACODEC_VOL_CTRL */ 120 #define ACODEC_SET_DACL_VOL \ 121 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_DACL_VOL, ACODEC_VOL_CTRL) 122 /* Output volume control(right channel) ACODEC_VOL_CTRL */ 123 #define ACODEC_SET_DACR_VOL \ 124 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_DACR_VOL, ACODEC_VOL_CTRL) 125 /* analog part input volume control(left channel 0~0x1f) */ 126 #define ACODEC_SET_GAIN_MICL \ 127 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_GAIN_MICL, unsigned int) 128 /* analog part input volume control(right channel 0~0x1f) */ 129 #define ACODEC_SET_GAIN_MICR \ 130 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_GAIN_MICR, unsigned int) 131 /* Input mute control(left channel), 1:mute, 0:unmute */ 132 #define ACODEC_SET_MICL_MUTE \ 133 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_MICL_MUTE, unsigned int) 134 /* Input mute control(right channel), 1:mute, 0:unmute */ 135 #define ACODEC_SET_MICR_MUTE \ 136 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_MICR_MUTE, unsigned int) 137 /* Output mute control(left channel), 1:mute, 0:unmute */ 138 #define ACODEC_SET_DACL_MUTE \ 139 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_DACL_MUTE, unsigned int) 140 /* Output mute control(right channel), 1:mute, 0:unmute */ 141 #define ACODEC_SET_DACR_MUTE \ 142 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_DACR_MUTE, unsigned int) 143 /* Audio AD BOOST Control, 1:on, 0:off */ 144 #define ACODEC_ENABLE_BOOSTL \ 145 _IOWR(IOC_TYPE_ACODEC, IOC_NR_BOOSTL_ENABLE, unsigned int) 146 #define ACODEC_ENABLE_BOOSTR \ 147 _IOWR(IOC_TYPE_ACODEC, IOC_NR_BOOSTR_ENABLE, unsigned int) 148 149 #define ACODEC_GET_DACL_VOL \ 150 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_DACL_VOL, ACODEC_VOL_CTRL) 151 #define ACODEC_GET_DACR_VOL \ 152 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_DACR_VOL, ACODEC_VOL_CTRL) 153 #define ACODEC_GET_ADCL_VOL \ 154 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_ADCL_VOL, ACODEC_VOL_CTRL) 155 #define ACODEC_GET_ADCR_VOL \ 156 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_ADCR_VOL, ACODEC_VOL_CTRL) 157 #define ACODEC_GET_GAIN_MICL \ 158 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_GAIN_MICL, unsigned int) 159 #define ACODEC_GET_GAIN_MICR \ 160 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_GAIN_MICR, unsigned int) 161 162 /* set adcl power, 0: power up, 1: power down */ 163 #define ACODEC_SET_PD_LINEINL \ 164 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_PD_LINEINL, unsigned int) 165 /* set adcr power, 0: power up, 1: power down */ 166 #define ACODEC_SET_PD_LINEINR \ 167 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_PD_LINEINR, unsigned int) 168 /* set adcl power, 0: power up, 1: power down */ 169 #define ACODEC_SET_PD_DACL \ 170 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_PD_DACL, unsigned int) 171 /* set adcr power, 0: power up, 1: power down */ 172 #define ACODEC_SET_PD_DACR \ 173 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_PD_DACR, unsigned int) 174 /* set adcl power, 0: power up, 1: power down */ 175 #define ACODEC_SET_PD_ADCL \ 176 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_PD_ADCL, unsigned int) 177 /* set adcr power, 0: power up, 1: power down */ 178 #define ACODEC_SET_PD_ADCR \ 179 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_PD_ADCR, unsigned int) 180 181 /* Don't need to set, the driver will set a default value */ 182 /* clock of dac and adc is reverse or obverse */ 183 #define ACODEC_SEL_DAC_CLK \ 184 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SEL_DAC_CLK, unsigned int) 185 #define ACODEC_SEL_ADC_CLK \ 186 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SEL_ADC_CLK, unsigned int) 187 /* clock of analog part and digital part is reverse or obverse */ 188 #define ACODEC_SEL_ANA_MCLK \ 189 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SEL_ANA_MCLK, unsigned int) 190 #define ACODEC_SET_DAC_DE_EMPHASIS \ 191 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_DAC_DE_EMPHASIS, unsigned int) 192 #define ACODEC_SET_ADC_HP_FILTER \ 193 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_ADC_HP_FILTER, unsigned int) 194 195 #define ACODEC_GET_INPUT_VOL \ 196 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_INPUT_VOL, unsigned int) 197 #define ACODEC_GET_OUTPUT_VOL \ 198 _IOWR(IOC_TYPE_ACODEC, IOC_NR_GET_OUTPUT_VOL, unsigned int) 199 #define ACODEC_SET_INPUT_VOL \ 200 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_INPUT_VOL, unsigned int) 201 #define ACODEC_SET_OUTPUT_VOL \ 202 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_OUTPUT_VOL, unsigned int) 203 204 #define ACODEC_ADCL_SEL_TRACK \ 205 _IOWR(IOC_TYPE_ACODEC, IOC_NR_ADCL_SEL_TRACK, unsigned int) 206 #define ACODEC_ADCR_SEL_TRACK \ 207 _IOWR(IOC_TYPE_ACODEC, IOC_NR_ADCR_SEL_TRACK, unsigned int) 208 #define ACODEC_DACL_SEL_TRACK \ 209 _IOWR(IOC_TYPE_ACODEC, IOC_NR_DACL_SEL_TRACK, unsigned int) 210 #define ACODEC_DACR_SEL_TRACK \ 211 _IOWR(IOC_TYPE_ACODEC, IOC_NR_DACR_SEL_TRACK, unsigned int) 212 213 /* Reserved ioctl cmd */ 214 #define ACODEC_SET_I2S1_DATAWIDTH \ 215 _IOWR(IOC_TYPE_ACODEC, IOC_NR_SET_I2S1_DATAWIDTH, unsigned int) 216 217 #endif /* End of #ifndef __ACODEC_H__ */ 218