1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __HI_MIPI_H__ 17 #define __HI_MIPI_H__ 18 19 typedef unsigned int combo_dev_t; 20 typedef unsigned int sns_rst_source_t; 21 typedef unsigned int sns_clk_source_t; 22 23 #define MIPI_LANE_NUM 4 24 #define LVDS_LANE_NUM 4 25 26 #define WDR_VC_NUM 4 27 #define SYNC_CODE_NUM 4 28 29 #define MIPI_RX_MAX_DEV_NUM 2 30 #define CMOS_MAX_DEV_NUM 1 31 32 #define SNS_MAX_CLK_SOURCE_NUM 2 33 #define SNS_MAX_RST_SOURCE_NUM 2 34 #define MAX_EXT_DATA_TYPE_NUM 3 35 36 #define hi_mipi_rx_unused(x) ((void)(x)) 37 38 #define HI_ERR(x...) \ 39 do { \ 40 osal_printk("%s(%d): ", __FUNCTION__, __LINE__); \ 41 osal_printk(x); \ 42 } while (0) 43 44 typedef enum { 45 LANE_DIVIDE_MODE_0 = 0, 46 LANE_DIVIDE_MODE_1 = 1, 47 LANE_DIVIDE_MODE_BUTT 48 } lane_divide_mode_t; 49 50 typedef enum { 51 WORK_MODE_LVDS = 0x0, 52 WORK_MODE_MIPI = 0x1, 53 WORK_MODE_CMOS = 0x2, 54 WORK_MODE_BT1120 = 0x3, 55 WORK_MODE_SLVS = 0x4, 56 WORK_MODE_BUTT 57 } work_mode_t; 58 59 typedef enum { 60 INPUT_MODE_MIPI = 0x0, /* mipi */ 61 INPUT_MODE_SUBLVDS = 0x1, /* SUB_LVDS */ 62 INPUT_MODE_LVDS = 0x2, /* LVDS */ 63 INPUT_MODE_HISPI = 0x3, /* HISPI */ 64 INPUT_MODE_CMOS = 0x4, /* CMOS */ 65 INPUT_MODE_BT601 = 0x5, /* BT601 */ 66 INPUT_MODE_BT656 = 0x6, /* BT656 */ 67 INPUT_MODE_BT1120 = 0x7, /* BT1120 */ 68 INPUT_MODE_BYPASS = 0x8, /* MIPI Bypass */ 69 70 INPUT_MODE_BUTT 71 } input_mode_t; 72 73 typedef enum { 74 MIPI_DATA_RATE_X1 = 0, /* output 1 pixel per clock */ 75 MIPI_DATA_RATE_X2 = 1, /* output 2 pixel per clock */ 76 77 MIPI_DATA_RATE_BUTT 78 } mipi_data_rate_t; 79 80 typedef struct { 81 int x; 82 int y; 83 unsigned int width; 84 unsigned int height; 85 } img_rect_t; 86 87 typedef struct { 88 unsigned int width; 89 unsigned int height; 90 } img_size_t; 91 92 typedef enum { 93 DATA_TYPE_RAW_8BIT = 0, 94 DATA_TYPE_RAW_10BIT, 95 DATA_TYPE_RAW_12BIT, 96 DATA_TYPE_RAW_14BIT, 97 DATA_TYPE_RAW_16BIT, 98 DATA_TYPE_YUV420_8BIT_NORMAL, 99 DATA_TYPE_YUV420_8BIT_LEGACY, 100 DATA_TYPE_YUV422_8BIT, 101 DATA_TYPE_YUV422_PACKED, /* yuv422 8bit transform user define 16bit raw */ 102 DATA_TYPE_BUTT 103 } data_type_t; 104 105 typedef struct { 106 combo_dev_t devno; 107 unsigned int num; 108 unsigned int ext_data_bit_width[MAX_EXT_DATA_TYPE_NUM]; 109 unsigned int ext_data_type[MAX_EXT_DATA_TYPE_NUM]; 110 } ext_data_type_t; 111 112 /* MIPI D_PHY WDR MODE defines */ 113 typedef enum { 114 HI_MIPI_WDR_MODE_NONE = 0x0, 115 HI_MIPI_WDR_MODE_VC = 0x1, /* Virtual Channel */ 116 HI_MIPI_WDR_MODE_DT = 0x2, /* Data Type */ 117 HI_MIPI_WDR_MODE_DOL = 0x3, /* DOL Mode */ 118 HI_MIPI_WDR_MODE_BUTT 119 } mipi_wdr_mode_t; 120 121 typedef struct { 122 data_type_t input_data_type; /* data type: 8/10/12/14/16 bit */ 123 mipi_wdr_mode_t wdr_mode; /* MIPI WDR mode */ 124 short lane_id[MIPI_LANE_NUM]; /* lane_id: -1 - disable */ 125 126 union { 127 short data_type[WDR_VC_NUM]; /* used by the HI_MIPI_WDR_MODE_DT */ 128 }; 129 } mipi_dev_attr_t; 130 131 typedef enum { 132 HI_WDR_MODE_NONE = 0x0, 133 HI_WDR_MODE_2F = 0x1, 134 HI_WDR_MODE_3F = 0x2, 135 HI_WDR_MODE_4F = 0x3, 136 HI_WDR_MODE_DOL_2F = 0x4, 137 HI_WDR_MODE_DOL_3F = 0x5, 138 HI_WDR_MODE_DOL_4F = 0x6, 139 HI_WDR_MODE_BUTT 140 } wdr_mode_t; 141 142 typedef enum { 143 LVDS_SYNC_MODE_SOF = 0, /* sensor SOL, EOL, SOF, EOF */ 144 LVDS_SYNC_MODE_SAV, /* SAV, EAV */ 145 LVDS_SYNC_MODE_BUTT 146 } lvds_sync_mode_t; 147 148 typedef enum { 149 LVDS_VSYNC_NORMAL = 0x00, 150 LVDS_VSYNC_SHARE = 0x01, 151 LVDS_VSYNC_HCONNECT = 0x02, 152 LVDS_VSYNC_BUTT 153 } lvds_vsync_type_t; 154 155 typedef struct { 156 lvds_vsync_type_t sync_type; 157 158 /* hconnect vsync blanking len, valid when the sync_type is LVDS_VSYNC_HCONNECT */ 159 unsigned short hblank1; 160 unsigned short hblank2; 161 } lvds_vsync_attr_t; 162 163 typedef enum { 164 LVDS_FID_NONE = 0x00, 165 LVDS_FID_IN_SAV = 0x01, /* frame identification id in SAV 4th */ 166 LVDS_FID_IN_DATA = 0x02, /* frame identification id in first data */ 167 LVDS_FID_BUTT 168 } lvds_fid_type_t; 169 170 typedef struct { 171 lvds_fid_type_t fid_type; 172 173 /* 174 * Sony DOL has the Frame Information Line, in DOL H-Connection mode, 175 * should configure this flag as false to disable output the Frame Information Line 176 */ 177 unsigned char output_fil; 178 } lvds_fid_attr_t; 179 180 typedef enum { 181 LVDS_ENDIAN_LITTLE = 0x0, 182 LVDS_ENDIAN_BIG = 0x1, 183 LVDS_ENDIAN_BUTT 184 } lvds_bit_endian_t; 185 186 typedef struct { 187 data_type_t input_data_type; /* data type: 8/10/12/14 bit */ 188 wdr_mode_t wdr_mode; /* WDR mode */ 189 190 lvds_sync_mode_t sync_mode; /* sync mode: SOF, SAV */ 191 lvds_vsync_attr_t vsync_attr; /* normal, share, hconnect */ 192 lvds_fid_attr_t fid_attr; /* frame identification code */ 193 194 lvds_bit_endian_t data_endian; /* data endian: little/big */ 195 lvds_bit_endian_t sync_code_endian; /* sync code endian: little/big */ 196 short lane_id[LVDS_LANE_NUM]; /* lane_id: -1 - disable */ 197 198 /* 199 * each vc has 4 params, sync_code[i]: 200 * sync_mode is SYNC_MODE_SOF: SOF, EOF, SOL, EOL 201 * sync_mode is SYNC_MODE_SAV: invalid sav, invalid eav, valid sav, valid eav 202 */ 203 unsigned short sync_code[LVDS_LANE_NUM][WDR_VC_NUM][SYNC_CODE_NUM]; 204 } lvds_dev_attr_t; 205 206 typedef struct { 207 combo_dev_t devno; /* device number */ 208 input_mode_t input_mode; /* input mode: MIPI/LVDS/SUBLVDS/HISPI/DC */ 209 mipi_data_rate_t data_rate; 210 img_rect_t img_rect; /* MIPI Rx device crop area (corresponding to the oringnal sensor input image size) */ 211 212 union { 213 mipi_dev_attr_t mipi_attr; 214 lvds_dev_attr_t lvds_attr; 215 }; 216 } combo_dev_attr_t; 217 218 typedef enum { 219 PHY_CMV_GE1200MV = 0x00, 220 PHY_CMV_LT1200MV = 0x01, 221 PHY_CMV_BUTT 222 } phy_cmv_mode_t; 223 224 typedef struct { 225 combo_dev_t devno; 226 phy_cmv_mode_t cmv_mode; 227 } phy_cmv_t; 228 229 #define HI_MIPI_IOC_MAGIC 'm' 230 231 /* init data lane, input mode, data type */ 232 #define HI_MIPI_SET_DEV_ATTR _IOW(HI_MIPI_IOC_MAGIC, 0x01, combo_dev_attr_t) 233 234 /* set phy common mode voltage mode */ 235 #define HI_MIPI_SET_PHY_CMVMODE _IOW(HI_MIPI_IOC_MAGIC, 0x04, phy_cmv_t) 236 237 /* reset sensor */ 238 #define HI_MIPI_RESET_SENSOR _IOW(HI_MIPI_IOC_MAGIC, 0x05, sns_rst_source_t) 239 240 /* unreset sensor */ 241 #define HI_MIPI_UNRESET_SENSOR _IOW(HI_MIPI_IOC_MAGIC, 0x06, sns_rst_source_t) 242 243 /* reset mipi */ 244 #define HI_MIPI_RESET_MIPI _IOW(HI_MIPI_IOC_MAGIC, 0x07, combo_dev_t) 245 246 /* unreset mipi */ 247 #define HI_MIPI_UNRESET_MIPI _IOW(HI_MIPI_IOC_MAGIC, 0x08, combo_dev_t) 248 249 /* reset slvs */ 250 #define HI_MIPI_RESET_SLVS _IOW(HI_MIPI_IOC_MAGIC, 0x09, combo_dev_t) 251 252 /* unreset slvs */ 253 #define HI_MIPI_UNRESET_SLVS _IOW(HI_MIPI_IOC_MAGIC, 0x0a, combo_dev_t) 254 255 /* set mipi hs_mode */ 256 #define HI_MIPI_SET_HS_MODE _IOW(HI_MIPI_IOC_MAGIC, 0x0b, lane_divide_mode_t) 257 258 /* enable mipi clock */ 259 #define HI_MIPI_ENABLE_MIPI_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0c, combo_dev_t) 260 261 /* disable mipi clock */ 262 #define HI_MIPI_DISABLE_MIPI_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0d, combo_dev_t) 263 264 /* enable slvs clock */ 265 #define HI_MIPI_ENABLE_SLVS_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0e, combo_dev_t) 266 267 /* disable slvs clock */ 268 #define HI_MIPI_DISABLE_SLVS_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0f, combo_dev_t) 269 270 /* enable sensor clock */ 271 #define HI_MIPI_ENABLE_SENSOR_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x10, sns_clk_source_t) 272 273 /* disable sensor clock */ 274 #define HI_MIPI_DISABLE_SENSOR_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x11, sns_clk_source_t) 275 276 #define HI_MIPI_SET_EXT_DATA_TYPE _IOW(HI_MIPI_IOC_MAGIC, 0x12, ext_data_type_t) 277 278 #endif /* __HI_MIPI_RX_H__ */ 279