1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __HI_MIPI_TX_H__ 17 #define __HI_MIPI_TX_H__ 18 19 #define CMD_MAX_NUM 4 20 #define LANE_MAX_NUM 4 21 #define MIPI_TX_DISABLE_LANE_ID (-1) 22 #define MIPI_TX_SET_DATA_SIZE 800 23 #define MIPI_TX_GET_DATA_SIZE 160 24 25 typedef enum { 26 OUTPUT_MODE_CSI = 0x0, /* csi mode */ 27 OUTPUT_MODE_DSI_VIDEO = 0x1, /* dsi video mode */ 28 OUTPUT_MODE_DSI_CMD = 0x2, /* dsi command mode */ 29 30 OUTPUT_MODE_BUTT 31 } output_mode_t; 32 33 typedef enum { 34 BURST_MODE = 0x0, 35 NON_BURST_MODE_SYNC_PULSES = 0x1, 36 NON_BURST_MODE_SYNC_EVENTS = 0x2, 37 38 VIDEO_DATA_MODE_BUTT 39 } video_mode_t; 40 41 typedef enum { 42 OUT_FORMAT_RGB_16_BIT = 0x0, 43 OUT_FORMAT_RGB_18_BIT = 0x1, 44 OUT_FORMAT_RGB_24_BIT = 0x2, 45 OUT_FORMAT_YUV420_8_BIT_NORMAL = 0x3, 46 OUT_FORMAT_YUV420_8_BIT_LEGACY = 0x4, 47 OUT_FORMAT_YUV422_8_BIT = 0x5, 48 49 OUT_FORMAT_BUTT 50 } output_format_t; 51 52 typedef struct { 53 unsigned short vid_pkt_size; 54 unsigned short vid_hsa_pixels; 55 unsigned short vid_hbp_pixels; 56 unsigned short vid_hline_pixels; 57 unsigned short vid_vsa_lines; 58 unsigned short vid_vbp_lines; 59 unsigned short vid_vfp_lines; 60 unsigned short vid_active_lines; 61 unsigned short edpi_cmd_size; 62 } sync_info_t; 63 64 typedef struct { 65 unsigned int devno; /* device number */ 66 short lane_id[LANE_MAX_NUM]; /* lane_id: -1 - disable */ 67 output_mode_t output_mode; /* output mode: CSI/DSI_VIDEO/DSI_CMD */ 68 video_mode_t video_mode; 69 output_format_t output_format; 70 sync_info_t sync_info; 71 unsigned int phy_data_rate; /* mbps */ 72 unsigned int pixel_clk; /* KHz */ 73 } combo_dev_cfg_t; 74 75 typedef struct { 76 unsigned int devno; /* device number */ 77 unsigned short data_type; 78 unsigned short cmd_size; 79 unsigned char *cmd; 80 } cmd_info_t; 81 82 typedef struct { 83 unsigned int devno; /* device number */ 84 unsigned short data_type; /* DSI data type */ 85 unsigned short data_param; /* data param,low 8 bit:first param.high 8 bit:second param, set 0 if not use */ 86 unsigned short get_data_size; /* read data size */ 87 unsigned char *get_data; /* read data memory address, should malloc by user */ 88 } get_cmd_info_t; 89 90 #define HI_MIPI_TX_IOC_MAGIC 't' 91 92 #define HI_MIPI_TX_SET_DEV_CFG _IOW(HI_MIPI_TX_IOC_MAGIC, 0x01, combo_dev_cfg_t) 93 #define HI_MIPI_TX_SET_CMD _IOW(HI_MIPI_TX_IOC_MAGIC, 0x02, cmd_info_t) 94 #define HI_MIPI_TX_ENABLE _IO(HI_MIPI_TX_IOC_MAGIC, 0x03) 95 #define HI_MIPI_TX_GET_CMD _IOWR(HI_MIPI_TX_IOC_MAGIC, 0x04, get_cmd_info_t) 96 #define HI_MIPI_TX_DISABLE _IO(HI_MIPI_TX_IOC_MAGIC, 0x05) 97 98 #endif 99