1root { 2 platform { 3 timer_config { 4 match_attr = "hisilicon_hi35xx_timer"; 5 template timer_controller { 6 number = 1; 7 reg_base = 0x113B0000; 8 bus_clock = 30; /* bus clock ,HZ */ 9 mode = 1; /* once time or period */ 10 init_count_val = 0; /* timer count value */ 11 irq = 33; /* timer interrupt number */ 12 } 13 device_timer_0 :: timer_controller { 14 number = 0; 15 reg_base = 0x12000000; 16 bus_clock = 30; 17 irq = 33; 18 } 19 device_timer_1 :: timer_controller { 20 number = 1; 21 reg_base = 0x12000020; 22 bus_clock = 30; 23 irq = 33; 24 } 25 device_timer_2 :: timer_controller { 26 number = 2; 27 reg_base = 0x12001000; 28 bus_clock = 30; 29 irq = 34; 30 } 31 device_timer_3 :: timer_controller { 32 number = 3; 33 reg_base = 0x12001020; 34 bus_clock = 30; 35 irq = 34; 36 } 37 device_timer_4 :: timer_controller { 38 number = 4; 39 reg_base = 0x12002000; 40 bus_clock = 30; 41 irq = 35; 42 } 43 device_timer_5 :: timer_controller { 44 number = 5; 45 reg_base = 0x12002020; 46 bus_clock = 30; 47 irq = 35; 48 } 49 device_timer_6 :: timer_controller { 50 number = 6; 51 reg_base = 0x12003000; 52 bus_clock = 30; 53 irq = 36; 54 } 55 device_timer_7 :: timer_controller { 56 number = 7; 57 reg_base = 0x12003020; 58 bus_clock = 30; 59 irq = 36; 60 } 61 } 62 } 63} 64