1root { 2 platform { 3 spi_config { 4 template spi_controller { 5 match_attr = ""; 6 transferMode = 0; 7 busNum = 0; 8 clkRate = 100000000; 9 bitsPerWord = 8; 10 mode = 19; 11 maxSpeedHz = 0; 12 minSpeedHz = 0; 13 speed = 2000000; 14 fifoSize = 256; 15 numCs = 1; 16 regBase = 0x12070000; 17 irqNum = 46; 18 REG_CRG_SPI = 0x120101bc; /* CRG_REG_BASE(0x12010000) + 0x01bc */ 19 CRG_SPI_CKEN = 0; 20 CRG_SPI_RST = 0; 21 REG_MISC_CTRL_SPI = 0x12028000; /* MISC_REG_BASE(0x12028000) + 0 */ 22 MISC_CTRL_SPI_CS = 0; 23 MISC_CTRL_SPI_CS_SHIFT = 0; 24 } 25 26 spi_controller_0x12070000 :: spi_controller { 27 busNum = 0; 28 CRG_SPI_CKEN = 0x1000; /* (0x1 << 12) 0:close clk, 1:open clk */ 29 CRG_SPI_RST = 0x8000; /* (0x1 << 15) 0:cancel reset, 1:reset */ 30 match_attr = "hisilicon_hi35xx_spi_0"; 31 } 32 33 spi_controller_0x12071000 :: spi_controller { 34 busNum = 1; 35 numCs = 2; 36 CRG_SPI_CKEN = 0x2000; /* (0x1 << 13) 0:close clk, 1:open clk */ 37 CRG_SPI_RST = 0x10000; /* (0x1 << 16) 0:cancel reset, 1:reset */ 38 MISC_CTRL_SPI_CS = 0x4; /* (0x1 << MISC_CTRL_SPI_CS_SHIFT) 00:cs0, 01:cs1 */ 39 MISC_CTRL_SPI_CS_SHIFT = 2; /* 2 */ 40 match_attr = "hisilicon_hi35xx_spi_1"; 41 regBase = 0x12071000; 42 irqNum = 47; 43 } 44 } 45 } 46} 47