1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __FLASH_PRV_H__ 17 #define __FLASH_PRV_H__ 18 #include <hi_flash_base.h> 19 #include <hi_types_base.h> 20 #include <hi3861_platform_base.h> 21 #define flash_info_print(fmt, ...) 22 23 #define HI_FLASH_OPTION_READ_WAIT_READY 0x1 24 #define HI_FLASH_OPTION_WRITE_WAIT_READY 0x2 25 #define HI_FLASH_OPTION_ERASE_WAIT_READY 0x4 26 #define HI_FLASH_OPTION_WRITE_ENABLE_WAIT_READY 0x8 27 28 /*****************************************************************************/ 29 #define SPI_QE_EN 0x02 /* QE Bit Enable */ 30 #define SPI_CMD_WREN 0x06 /* Write Enable */ 31 #define SPI_CMD_VSR_WREN 0x50 /* write volatile SR reg enable */ 32 /*****************************************************************************/ 33 #define SPI_CMD_SE_4K 0x20 /* 4KB sector Erase */ 34 #define SPI_CMD_SE_32K 0x52 /* 32KB sector Erase */ 35 #define SPI_CMD_SE 0xD8 /* 64KB Sector Erase */ 36 #define SPI_CMD_CE1 0xC7 /* chip erase */ 37 #define SPI_CMD_CE2 0x60 /* chip erase */ 38 /*****************************************************************************/ 39 #define SPI_CMD_WRSR1 0x01 /* Write Status Register */ 40 #define SPI_CMD_WRSR2 0x31 /* Write Status Register-2 */ 41 #define SPI_CMD_RDSR2 0x35 /* Read Status Register-2 */ 42 #define SPI_CMD_WRSR3 0x11 /* Write Status Register-3 */ 43 #define SPI_CMD_RDSR3 0x15 /* Read Status Register-3 */ 44 #define SPI_CMD_RDID 0x9F /* Read Identification */ 45 46 /* read status register. */ 47 #define SPI_CMD_RDSR 0x05 48 49 /* write status/configuration register. */ 50 #define SPI_CMD_WRSRCR 0x01 51 52 /* read configuration register. */ 53 #define SPI_CMD_RDCR 0x15 54 55 /*****************************************************************************/ 56 #define SPI_CMD_PP 0x02 /* Page Programming */ 57 #define SPI_CMD_WRITE_DUAL 0xA2 /* fast program dual input */ 58 #define SPI_CMD_WRITE_QUAD 0x32 /* fast program quad input */ 59 #define SPI_CMD_WRITE_DUAL_ADDR 0xD2 /* Dual I/O High Performance Write */ 60 #define SPI_CMD_WRITE_QUAD_ADDR 0x12 /* Quad I/O High Performance Write */ 61 /*****************************************************************************/ 62 #define SPI_CMD_READ 0x03 /* Read Data bytes */ 63 #define SPI_CMD_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */ 64 #define SPI_CMD_READ_DUAL 0x3B /* fast read dual output */ 65 #define SPI_CMD_READ_QUAD 0x6B /* fast read quad output */ 66 #define SPI_CMD_QUAD_IO 0xEB /* fast quad-IO */ 67 68 #define SPI_CMD_READ_DUAL_ADDR 0xBB /* Dual I/O High Performance Read */ 69 #define SPI_CMD_READ_QUAD_ADDR 0xEB /* Quad I/O High Performance Read */ 70 /*****************************************************************************/ 71 #define SPI_CMD_SR_WIPN 0 /* Write in Progress */ 72 #define SPI_CMD_SR_WIP 1 /* Write in Progress */ 73 #define SPI_CMD_SR_WEL 2 /* Write Enable Latch */ 74 /*****************************************************************************/ 75 #define SPI_CMD_EN4B 0xB7 /* enter to 4 bytes mode and set 4 byte bit as '1' */ 76 #define SPI_CMD_EX4B 0xE9 /* exit 4 bytes mode and clear 4 byte bit as '0' */ 77 78 #define SPI_CMD_RESET_ENABLE 0x66 /* RESET Enable */ 79 #define SPI_CMD_RESET 0x99 /* RESET */ 80 81 #define SPI_SR_BIT_WIP (1<<0) /* Write in Progress */ 82 #define SPI_SR_BIT_WEL (1<<1) /* Write Enable Latch */ 83 84 #define _1K 0x400 85 #define _2K 0x800 86 #define _4K 0x1000 87 #define _8K 0x2000 88 #define _16K 0x4000 89 #define _32K 0x8000 90 #define _64K 0x10000 91 #define _128K 0x20000 92 #define _256K 0x40000 93 #define _512K 0x80000 94 #define _1M 0x100000 95 #define _2M 0x200000 96 #define _4M 0x400000 97 #define _8M 0x800000 98 #define _16M 0x1000000 99 #define _32M 0x2000000 100 101 #define _CHIP_SIZE 0x3ffff 102 #define HI_FLASH_DEFAULT_TYPE_NUM 8 103 104 #define HI_FLASH_SUPPORT_REF_VBAT /* VBAT can be used as ref valtage */ 105 /* if support flash_update:#define HI_FLASH_SUPPORT_UPDATE_SFC_FREQ */ 106 #define HI_FLASH_VOLTAGE_TH0 280 107 #define HI_FLASH_VOLTAGE_TH1 310 108 #define PLL2DBB_192M_MASK 0x3 109 #define CMU_CLK_SEL_96M 96 110 #define CMU_CLK_SEL_80M 80 111 #define CMU_CLK_SEL_48M 48 112 113 typedef struct { 114 hi_u32 cmd : 8; 115 hi_u32 iftype : 3; 116 hi_u32 dummy : 3; 117 hi_u32 size : 18; 118 } spi_flash_operation; 119 120 typedef enum { 121 HI_FLASH_SUPPORT_4K_ERASE = 0x1, 122 HI_FLASH_SUPPORT_32K_ERASE = 0x2, 123 HI_FLASH_SUPPORT_64K_ERASE = 0x4, 124 HI_FLASH_SUPPORT_CHIP_ERASE = 0x8, 125 HI_FLASH_SUPPORT_AREA_LOCK_NV = 0x10, 126 HI_FLASH_SUPPORT_AREA_LOCK_VOLATILE = 0x20, 127 HI_FLASH_SUPPORT_INDIVIDUAL_LOCK = 0x40, 128 HI_FLASH_SUPPORT_SUSPEND_RESUME = 0x80, 129 HI_FLASH_VLT_INFLUENCE_FREQ = 0x100, 130 HI_FLASH_SUPPORT_MASK = 0xFFFF, 131 } hi_spi_flash_chip_attribute; 132 133 typedef struct { 134 hi_char *chip_name; 135 hi_u8 chip_id[HI_FLASH_CHIP_ID_NUM]; 136 hi_u8 freq_read; 137 hi_u8 freq_lowpower; 138 hi_u8 freq_hpm; 139 hi_u16 chip_attribute; 140 hi_u8 cmd_suspend; 141 hi_u8 cmd_resume; 142 hi_u8 cmd_readsr; 143 hi_u8 sus_bits; 144 } hi_spi_flash_basic_info; 145 146 typedef struct { 147 hi_u32 flash_offset; 148 hi_u8 *ram_data; 149 hi_u32 size; 150 } spi_flash_prv_addr_info; 151 152 typedef struct { 153 hi_u8 chip_id[HI_FLASH_CHIP_ID_NUM]; /* flash chip ID */ 154 hi_u8 freq_high : 2; 155 hi_u8 freq_midle : 2; 156 hi_u8 freq_low : 2; 157 hi_u8 voltage : 2; 158 } flash_vlt_sfc_info; 159 160 #define HI_FLASH_SUPPORT_CHIPS (HI_FLASH_SUPPORT_4K_ERASE | \ 161 HI_FLASH_SUPPORT_64K_ERASE | \ 162 HI_FLASH_SUPPORT_CHIP_ERASE | \ 163 HI_FLASH_SUPPORT_AREA_LOCK_NV | \ 164 HI_FLASH_SUPPORT_AREA_LOCK_VOLATILE) 165 #define HI_FLASH_SUPPORT_DEFAULT (HI_FLASH_SUPPORT_4K_ERASE | \ 166 HI_FLASH_SUPPORT_64K_ERASE | \ 167 HI_FLASH_SUPPORT_CHIP_ERASE) 168 169 #define PRODUCT_CFG_FLASH_BLOCK_SIZE 0x1000 170 /*****************************************************************************/ 171 #define HISFC300_DMA_MAX_SIZE 2048 172 #define HISFC300_DMA_MAX_MASK 0x7FF 173 174 /*****************************************************************************/ 175 #define HISFC300_REG_BUF_SIZE 64 176 #define HISFC300_REG_BUF_MASK 0x3F 177 178 #define HISFC300_BUS_CONFIG2 0x0204 179 #define HISFC300_BUS_BASE_ADDR_CS1 0x0218 180 #define HISFC300_BUS_ALIAS_ADDR 0x021C 181 #define HISFC300_BUS_ALIAS_CS 0x0220 182 #define HISFC300_CMD_DATABUF64 0x04FC 183 184 /***************SFC of Hi1131HV100********************************************/ 185 #define SFC_REG_BASE_ADDRESS HI_SFC_REG_BASE 186 #define SFC_BUFFER_BASE_ADDRESS 0x400000 187 188 #define SFC_REG_GLOBAL_CONFIG 0x0100 189 #define SFC_REG_GLOBAL_CONFIG_ADDR_MODE_4B (1 << 2) 190 #define SFC_REG_TIMING 0x0110 191 #define SFC_REG_GLOBAL_CONFIG_WP_ENABLE (1<<1) 192 #define sfc_timing_tshsl(_n) ((_n) & 0xF) 193 #define sfc_timing_tshwl(_n) (((_n) & 0xF) << 4) 194 #define sfc_timing_tcss(_n) (((_n) & 0x7) << 8) 195 #define sfc_timing_tcsh(_n) (((_n) & 0x7) << 12) 196 #define sfc_timing_trpd(_n) (((_n) & 0xFFF) << 16) 197 #define SFC_REG_INT_RAW_STATUS 0x0120 198 #define SFC_REG_INT_RAW_STATUS_DMA_DONE (1<<1) 199 #define SFC_REG_INT_STATUS 0x0124 200 #define SFC_REG_INT_MASK 0x0128 201 #define SFC_REG_INT_CLEAR 0x012C 202 #define SFC_REG_INT_CLEAR_DMA_DONE (1<<1) 203 #define SFC_REG_VERSION 0x01F8 204 #define SFC_REG_VERSION_SEL 0x01FC 205 206 #define SFC_REG_BUS_CONFIG1 0x0200 207 #define SFC_REG_BUS_CONFIG1_MASK_RD 0x8000ffff 208 #define SFC_REG_BUS_CONFIG1_MASK_WT 0x7fff0000 209 210 #define sfc_bus_config1_wr_ins(_n) (((_n) & 0xFF) << 22) 211 #define sfc_bus_config1_rd_ins(_n) (((_n) & 0xFF) << 8) 212 #define sfc_bus_config1_rd_prefetch_cnt(_n) (((_n) & 0x3) << 6) 213 #define sfc_bus_config1_rd_dummy_bytes(_n) (((_n) & 0x7) << 3) 214 #define sfc_bus_config1_rd_mem_if_type(_n) ((_n) & 0x7) 215 #define SFC_BUS_CONFIG1_RD_ENABLE ((hi_u32)1 << 31) 216 217 #define SFC_REG_BUS_FLASH_SIZE 0x0210 218 #define SFC_REG_BUS_BASE_ADDR_CS0 0x0214 219 #define SFC_REG_BUS_BASE_ADDR_CS1 0x0218 220 221 #define SFC_REG_BUS_DMA_CTRL 0X0240 222 #define SFC_BUS_DMA_CTRL_START (1<<0) 223 #define sfc_bus_dma_ctrl_read(_dir) ((_dir) << 1) 224 #define sfc_bus_dma_ctrl_cs(_cs) (((_cs) & 0x01) << 4) 225 #define SFC_REG_BUS_DMA_MEM_SADDR 0X0244 /* DMA DDR start address R */ 226 #define SFC_REG_BUS_DMA_FLASH_SADDR 0X0248 227 #define SFC_REG_BUS_DMA_LEN 0x024C 228 #define SFC_REG_BUS_DMA_AHB_CTRL 0X0250 229 #define SFC_BUS_DMA_AHB_CTRL_INCR4_EN (1<<0) 230 #define SFC_BUS_DMA_AHB_CTRL_INCR8_EN (1<<1) 231 #define SFC_BUS_DMA_AHB_CTRL_INCR16_EN (1<<2) 232 233 #define SFC_REG_CMD_CONFIG 0x0300 234 #define sfc_cmd_config_mem_if_type(_n) (((_n) & 0x07) << 17) 235 #define sfc_cmd_config_data_cnt(_n) ((((_n) - 1) & HISFC300_REG_BUF_MASK) << 9) 236 #define SFC_CMD_CONFIG_RW (1<<8) 237 #define SFC_CMD_CONFIG_DATA_EN (1<<7) 238 #define sfc_cmd_config_dummy_byte_cnt(_n) (((_n) & 0x07) << 4) 239 #define SFC_CMD_CONFIG_ADDR_EN (1<<3) 240 #define SFC_CMD_CONFIG_SEL_CS (0x01 << 1) 241 #define SFC_CMD_CONFIG_START (1 << 0) 242 #define SFC_REG_CMD_INS 0x0308 243 244 #define SFC_REG_CMD_ADDR 0x030C 245 #define SFC_CMD_ADDR_MASK 0x3FFFFFFF 246 #define SFC_REG_CMD_DATABUF1 0x0400 247 248 #define SPI_SR3_DRV_MASK 0x3 249 250 #define SFC_ERASE_OPT_MAX_NUM 4 251 252 typedef enum { 253 SPI_SR3_DRV_100PCT = 0, 254 SPI_SR3_DRV_75PCT, 255 SPI_SR3_DRV_50PCT, 256 SPI_SR3_DRV_25PCT, 257 SPI_SR3_DRV_MAX, 258 } hi_flash_drv_strength; 259 260 #define SFC_CMD_WRITE (0<<8) 261 #define SFC_CMD_READ (1<<8) 262 263 typedef enum { 264 HI_FLASH_CHECK_PARAM_OPT_READ, 265 HI_FLASH_CHECK_PARAM_OPT_WRITE, 266 HI_FLASH_CHECK_PARAM_OPT_ERASE, 267 } hi_flash_check_param_opt; 268 269 typedef struct spi_flash_ctrl { 270 hi_bool init; 271 hi_bool sus_enable; 272 hi_bool limit_0_to_1; 273 hi_u8 reserve; 274 hi_spi_flash_basic_info basic_info; 275 spi_flash_operation opt_read; 276 spi_flash_operation opt_write; 277 spi_flash_operation array_opt_erase[SFC_ERASE_OPT_MAX_NUM]; 278 hi_u32 chip_size; 279 hi_u32 erase_size; 280 hi_u32 dma_ram_size; 281 hi_u8 *dma_ram_buffer; 282 hi_u8 *back_up_buf; 283 hi_u32 (*read)(struct spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 read_size, 284 hi_void* ram_addr, hi_bool b_is_crash); 285 hi_u32 (*write)(struct spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 write_size, 286 hi_void* ram_addr, hi_bool b_is_crash); 287 hi_u32 (*erase)(struct spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 erase_size, hi_bool is_crash); 288 hi_bool (*is_busy)(hi_void); 289 hi_u32 mutex_handle; 290 hi_pvoid usr_data; 291 } hi_spi_flash_ctrl; 292 293 /*****************************************************************************/ 294 #define hisfc_read(_reg) \ 295 reg_read_val(SFC_REG_BASE_ADDRESS +(_reg)) 296 297 #define hisfc_write(_reg, _value) \ 298 reg_write32(SFC_REG_BASE_ADDRESS + (_reg), (_value)) 299 300 HI_EXTERN hi_u32 spi_flash_read_chip_id(hi_u8 *chip_id, hi_u8 id_len); 301 HI_EXTERN hi_u32 spi_flash_configure_driver_strength(hi_flash_drv_strength drv_strength); 302 303 HI_EXTERN hi_u32 spif_map_chipsize(hi_u32 chip_size); 304 HI_EXTERN hi_u32 spif_dma_read(hi_spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 read_size, 305 hi_void* ram_addr, hi_bool is_crash); 306 HI_EXTERN hi_u32 spif_reg_erase(hi_spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 erase_size, hi_bool is_crash); 307 HI_EXTERN hi_u32 spif_dma_write(hi_spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 write_size, 308 hi_void* ram_addr, hi_bool is_crash); 309 HI_EXTERN hi_bool spif_is_busy(hi_void); 310 HI_EXTERN hi_u32 spi_flash_basic_info_probe(HI_INOUT hi_spi_flash_ctrl* spif_ctrl, hi_u8 *chip_id, 311 hi_u8 id_len, hi_spi_flash_basic_info *spi_info_tbl, hi_u32 tbl_size); 312 HI_EXTERN hi_u32 flash_write_prv(hi_spi_flash_ctrl* spif_ctrl, const spi_flash_prv_addr_info *info, hi_bool do_erase, 313 hi_bool is_crash); 314 HI_EXTERN hi_u32 flash_erase_prv(hi_spi_flash_ctrl* spif_ctrl, hi_u32 flash_addr, hi_u32 size, hi_bool is_crash); 315 HI_EXTERN hi_u32 flash_read_prv(hi_spi_flash_ctrl* spif_ctrl, const spi_flash_prv_addr_info *info, hi_bool is_crash); 316 HI_EXTERN hi_u32 flash_suspend_prv_default(const hi_spi_flash_ctrl *spif_ctrl, hi_u32 timeout); 317 HI_EXTERN hi_void flash_resume_prv_default(const hi_spi_flash_ctrl *spif_ctrl, hi_u32 timeout); 318 HI_EXTERN hi_void spif_send_cmd(hi_u8 cmd); 319 HI_EXTERN hi_u32 spi_flash_read_reg(hi_u8 cmd, hi_u8 *data, hi_u8 data_len); 320 HI_EXTERN hi_u32 spi_flash_write_reg(hi_u8 cmd, const hi_u8 *data, hi_u8 data_len); 321 HI_EXTERN hi_u32 sfc_check_para(const hi_spi_flash_ctrl* spif_ctrl, hi_u32 addr, hi_u32 size, 322 hi_flash_check_param_opt opt); 323 HI_EXTERN hi_u32 flash_ioctl(const hi_spi_flash_ctrl* spif_ctrl, hi_u16 cmd, hi_void* data); 324 HI_EXTERN hi_u32 spi_flash_enable_quad_mode(hi_void); 325 HI_EXTERN hi_void spif_bus_config(const spi_flash_operation* spi_operation, hi_u8 cmd, hi_bool blto_read); 326 HI_EXTERN hi_void spif_register_irq_soft_patch(hi_void_callback prepare, hi_void_callback resume); 327 HI_EXTERN hi_void spif_wait_config_start(hi_void); 328 HI_EXTERN hi_u32 spif_write_enable(hi_bool is_crash); 329 HI_EXTERN hi_u32 spif_wait_ready(hi_bool is_crash, hi_u8 val, hi_u8 bit_mask); 330 331 332 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_standard_read; 333 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_fast_read; 334 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_fast_dual_out_read; 335 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_fast_quad_out_read; 336 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_fast_quad_eb_out_read; 337 338 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_page_program_write; 339 340 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_sector_erase; 341 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_32k_erase; 342 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_64k_erase; 343 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_chip_erase1; 344 HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_chip_erase2; 345 HI_EXTERN HI_CONST hi_spi_flash_basic_info g_flash_default_info_tbl[HI_FLASH_DEFAULT_TYPE_NUM]; 346 347 #ifdef HI_FLASH_SUPPORT_REF_VBAT 348 #ifdef HI_FLASH_SUPPORT_UPDATE_SFC_FREQ 349 hi_u32 sfc_config_get_update_time(hi_u32 *time_ms); 350 hi_u32 sfc_config_set_update_time(hi_u32 time_ms); 351 hi_void sfc_config_set_voltage_threshold_increment(hi_u8 voltage_increment); 352 hi_u32 sfc_config_get_voltage_threshold_increment(hi_u8 *voltage_increment); 353 354 #endif 355 #endif 356 357 /* flash protect */ 358 #define PROTECT_TIMEOUT_1 6000 359 #define PROTECT_TIMEOUT_2 3600000 360 #define PROTECT_TIMEOUT_AUTO 0xFFFFFFFF 361 #define PROTECT_FLASH_ALL 0x6 /* 0x6: 000110 */ 362 363 #ifdef HI_BOARD_ASIC 364 /* if support flash protect:#define HI_FLASH_SUPPORT_FLASH_PROTECT */ 365 #define HI_FLASH_SUPPORT_FLASH_PROTECT 366 #endif 367 368 typedef enum { 369 HI_FLASH_PROTECT_TYPE_1 = 0x0, 370 HI_FLASH_PROTECT_TYPE_2, 371 HI_FLASH_PROTECT_NONE, 372 HI_FLASH_PROTECT_TYPE_MAX, 373 }hi_flash_protect_type; 374 375 typedef struct { 376 hi_u32 default_type : 6; 377 hi_u32 enable : 1; 378 hi_u32 is_volatile : 1; 379 hi_u32 init : 1; 380 hi_u32 current_block : 13; 381 hi_u32 reserve : 10; 382 hi_u32 timer_timeout; 383 hi_u32 timer_handle; 384 } hi_flash_protect_ctrl; 385 386 typedef struct { 387 hi_u32 cmp_bp : 6; 388 hi_u32 block : 13; 389 hi_u32 reseve : 13; 390 } hi_flash_protect_size; 391 392 typedef struct { 393 hi_u32 support_flash_protect : 1; 394 hi_u32 protect_all : 1; 395 hi_u32 reserve : 30; 396 hi_u32 (*protect_all_area)(hi_void); 397 } support_flash_protect; 398 support_flash_protect *flash_get_support_flash_protect_info(hi_void); 399 hi_spi_flash_ctrl *flash_get_spi_flash_ctrl_info(hi_void); 400 401 #ifdef HI_FLASH_SUPPORT_FLASH_PROTECT 402 hi_u32 flash_protect(hi_u32 flash_offset, hi_u32 size, hi_u32 timeout, hi_bool is_volatile); 403 hi_u32 flash_protect_set_protect(hi_u8 cmp_bp, hi_bool is_volatile, hi_bool forced_write); 404 #endif 405 hi_u32 hi_flash_protect_init(hi_flash_protect_type type); 406 hi_u32 hi_flash_protect_deinit(hi_void); 407 hi_u32 hi_flash_protect_enable(hi_bool enable); 408 409 hi_u32 flash_lock(hi_void); 410 hi_u32 flash_unlock(hi_void); 411 hi_u8 get_flash_op_during_flash(void); /* flash option is during crash */ 412 413 hi_u32 hi_flash_write_fs(const hi_u32 flash_offset, hi_u32 size, const hi_u8 *ram_data, hi_bool do_erase); 414 415 #ifdef HI_FLASH_SUPPORT_COUNT_DEBUG 416 417 #define SECTOR_SIZE 4096 418 #define SECTOR_NUM 512 419 #define FLASH_OPT_RECORD_SIZE 2048 420 typedef struct { 421 hi_u16 write_times[SECTOR_NUM]; 422 hi_u16 erase_times[SECTOR_NUM]; 423 } hi_flash_opt_record; /* 2KB */ 424 425 hi_void hi_flash_record_opt_init(hi_void); 426 hi_flash_opt_record* hi_flash_get_opt_record(hi_void); 427 #endif 428 429 hi_void hi_flash_record_flash_opt(hi_void); 430 431 #endif 432