1 /* 2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __RK_VENC_CMD_H__ 17 #define __RK_VENC_CMD_H__ 18 19 #include "mpp_frame.h" 20 #include "rk_venc_rc.h" 21 22 /* 23 * Configure of encoder is very complicated. So we divide configures into 24 * four parts: 25 * 26 * 1. Rate control parameter 27 * This is quality and bitrate request from user. 28 * 29 * 2. Data source MppFrame parameter 30 * This is data source buffer information. 31 * Now it is PreP config 32 * PreP : Encoder Preprocess configuration 33 * 34 * 3. Video codec infomation 35 * This is user custormized stream information. 36 * including: 37 * H.264 / H.265 / vp8 / mjpeg 38 * 39 * 4. Misc parameter 40 * including: 41 * Split : Slice split configuration 42 * GopRef: Reference gop configuration 43 * ROI : Region Of Interest 44 * OSD : On Screen Display 45 * MD : Motion Detection 46 * 47 * The module transcation flow is as follows: 48 * 49 * + + 50 * User | Mpi/Mpp | EncImpl 51 * | | Hal 52 * | | 53 * +----------+ | +---------+ | +-----------+ 54 * | | | | +-----RcCfg-----> | 55 * | RcCfg +---------> | | | EncImpl | 56 * | | | | | +-Frame-----> | 57 * +----------+ | | | | | +--+-----^--+ 58 * | | | | | | | 59 * | | | | | | | 60 * +----------+ | | | | | syntax | 61 * | | | | | | | | | 62 * | MppFrame +---------> MppEnc +---+ | | result 63 * | | | | | | | | | 64 * +----------+ | | | | | | | 65 * | | | | | +--v-----+--+ 66 * | | | +-Frame-----> | 67 * +----------+ | | | | | | 68 * | | | | +---CodecCfg----> Hal | 69 * | CodecCfg +---------> | | | | 70 * | | | | <-----Extra-----> | 71 * +----------+ | +---------+ | +-----------+ 72 * | | 73 * | | 74 * + + 75 * 76 * The function call flow is shown below: 77 * 78 * mpi mpp_enc controller hal 79 * + + + + 80 * | | | | 81 * | | | | 82 * +----------init------------> | | 83 * | | | | 84 * | | | | 85 * | PrepCfg | | | 86 * +---------control----------> PrepCfg | | 87 * | +-----control-----> | 88 * | | | PrepCfg | 89 * | +--------------------------control--------> 90 * | | | allocate 91 * | | | buffer 92 * | | | | 93 * | RcCfg | | | 94 * +---------control----------> RcCfg | | 95 * | +-----control-----> | 96 * | | rc_init | 97 * | | | | 98 * | | | | 99 * | CodecCfg | | | 100 * +---------control----------> | CodecCfg | 101 * | +--------------------------control--------> 102 * | | | generate 103 * | | | sps/pps 104 * | | | Get extra info | 105 * | +--------------------------control--------> 106 * | Get extra info | | | 107 * +---------control----------> | | 108 * | | | | 109 * | | | | 110 * | ROICfg | | | 111 * +---------control----------> | ROICfg | 112 * | +--------------------------control--------> 113 * | | | | 114 * | OSDCfg | | | 115 * +---------control----------> | OSDCfg | 116 * | +--------------------------control--------> 117 * | | | | 118 * | MDCfg | | | 119 * +---------control----------> | MDCfg | 120 * | +--------------------------control--------> 121 * | | | | 122 * | Set extra info | | | 123 * +---------control----------> | Set extra info | 124 * | +--------------------------control--------> 125 * | | | | 126 * | task | | | 127 * +----------encode----------> task | | 128 * | +-----encode------> | 129 * | | encode | 130 * | | | syntax | 131 * | +--------------------------gen_reg--------> 132 * | | | | 133 * | | | | 134 * | +---------------------------start---------> 135 * | | | | 136 * | | | | 137 * | +---------------------------wait----------> 138 * | | | | 139 * | | callback | | 140 * | +-----------------> | 141 * +--OSD-MD--encode----------> | | 142 * | . | | | 143 * | . | | | 144 * | . | | | 145 * +--OSD-MD--encode----------> | | 146 * | | | | 147 * +----------deinit----------> | | 148 * + + + + 149 */ 150 151 /* 152 * base working mode parameter 153 */ 154 typedef enum MppEncBaseCfgChange_e { 155 MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0), 156 MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF), 157 } MppEncBaseCfgChange; 158 159 typedef struct MppEncBaseCfg_t { 160 unsigned int change; 161 162 signed int low_delay; 163 } MppEncBaseCfg; 164 165 /* 166 * Rate control parameter 167 */ 168 typedef enum MppEncRcCfgChange_e { 169 MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0), 170 MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1), 171 MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */ 172 MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denorminator */ 173 MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denorminator */ 174 MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7), 175 MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8), 176 MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9), 177 MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10), 178 MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11), 179 MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12), 180 MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13), 181 MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14), 182 MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15), 183 /* qp related change flag */ 184 MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16), 185 MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17), 186 MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18), 187 MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19), 188 MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20), 189 MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21), 190 MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22), 191 MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23), 192 MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24), 193 MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25), 194 MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26), 195 MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), 196 } MppEncRcCfgChange; 197 198 typedef enum MppEncRcQuality_e { 199 MPP_ENC_RC_QUALITY_WORST, 200 MPP_ENC_RC_QUALITY_WORSE, 201 MPP_ENC_RC_QUALITY_MEDIUM, 202 MPP_ENC_RC_QUALITY_BETTER, 203 MPP_ENC_RC_QUALITY_BEST, 204 MPP_ENC_RC_QUALITY_CQP, 205 MPP_ENC_RC_QUALITY_AQ_ONLY, 206 MPP_ENC_RC_QUALITY_BUTT 207 } MppEncRcQuality; 208 209 typedef struct MppEncRcCfg_t { 210 unsigned int change; 211 212 /* 213 * rc_mode - rate control mode 214 * 215 * mpp provide two rate control mode: 216 * 217 * Constant Bit Rate (CBR) mode 218 * - paramter 'bps*' define target bps 219 * - paramter quality and qp will not take effect 220 * 221 * Variable Bit Rate (VBR) mode 222 * - paramter 'quality' define 5 quality levels 223 * - paramter 'bps*' is used as reference but not strict condition 224 * - special Constant QP (CQP) mode is under VBR mode 225 * CQP mode will work with qp in CodecCfg. But only use for test 226 * 227 * default: CBR 228 */ 229 MppEncRcMode rc_mode; 230 231 /* 232 * quality - quality parameter, only takes effect in VBR mode 233 * 234 * Mpp does not give the direct parameter in different protocol. 235 * 236 * Mpp provide total 5 quality level: 237 * Worst - worse - Medium - better - best 238 * 239 * extra CQP level means special constant-qp (CQP) mode 240 * 241 * default value: Medium 242 */ 243 MppEncRcQuality quality; 244 245 /* 246 * bit rate parameters 247 * mpp gives three bit rate control parameter for control 248 * bps_target - target bit rate, unit: bit per second 249 * bps_max - maximun bit rate, unit: bit per second 250 * bps_min - minimun bit rate, unit: bit per second 251 * if user need constant bit rate set parameters to the similar value 252 * if user need variable bit rate set parameters as they need 253 */ 254 signed int bps_target; 255 signed int bps_max; 256 signed int bps_min; 257 258 /* 259 * frame rate parameters have great effect on rate control 260 * 261 * fps_in_flex 262 * 0 - fix input frame rate 263 * 1 - variable input frame rate 264 * 265 * fps_in_num 266 * input frame rate numerator, if 0 then default 30 267 * 268 * fps_in_denorm 269 * input frame rate denorminator, if 0 then default 1 270 * 271 * fps_out_flex 272 * 0 - fix output frame rate 273 * 1 - variable output frame rate 274 * 275 * fps_out_num 276 * output frame rate numerator, if 0 then default 30 277 * 278 * fps_out_denorm 279 * output frame rate denorminator, if 0 then default 1 280 */ 281 signed int fps_in_flex; 282 signed int fps_in_num; 283 signed int fps_in_denorm; 284 signed int fps_out_flex; 285 signed int fps_out_num; 286 signed int fps_out_denorm; 287 288 /* 289 * gop - group of picture, gap between Intra frame 290 * 0 for only 1 I frame the rest are all P frames 291 * 1 for all I frame 292 * 2 for I P I P I P 293 * 3 for I P P I P P 294 * etc... 295 */ 296 signed int gop; 297 298 /* 299 * skip_cnt - max continuous frame skip count 300 * 0 - frame skip is not allow 301 */ 302 signed int skip_cnt; 303 304 /* 305 * max_reenc_times - max reencode time for one frame 306 * 0 - reencode is not allowed 307 * 1~3 max reencode time is limited to 3 308 */ 309 unsigned int max_reenc_times; 310 311 /* 312 * stats_time - the time of bitrate statistics 313 */ 314 signed int stats_time; 315 316 /* 317 * drop frame parameters 318 * used on bitrate is far over the max bitrate 319 * 320 * drop_mode 321 * 322 * MPP_ENC_RC_DROP_FRM_DISABLED 323 * - do not drop frame when bitrate overflow. 324 * MPP_ENC_RC_DROP_FRM_NORMAL 325 * - do not encode the dropped frame when bitrate overflow. 326 * MPP_ENC_RC_DROP_FRM_PSKIP 327 * - encode a all skip frame when bitrate overflow. 328 * 329 * drop_threshold 330 * 331 * The percentage threshold over max_bitrate for trigger frame drop. 332 * 333 * drop_gap 334 * The max continuous frame drop number 335 */ 336 MppEncRcDropFrmMode drop_mode; 337 unsigned int drop_threshold; 338 unsigned int drop_gap; 339 340 MppEncRcSuperFrameMode super_mode; 341 unsigned int super_i_thd; 342 unsigned int super_p_thd; 343 344 MppEncRcPriority rc_priority; 345 346 unsigned int debreath_en; 347 unsigned int debre_strength; 348 signed int max_i_prop; 349 signed int min_i_prop; 350 signed int init_ip_ratio; 351 352 /* general qp control */ 353 signed int qp_init; 354 signed int qp_max; 355 signed int qp_max_i; 356 signed int qp_min; 357 signed int qp_min_i; 358 signed int qp_max_step; /* delta qp between each two P frame */ 359 signed int qp_delta_ip; /* delta qp between I and P */ 360 signed int qp_delta_vi; /* delta qp between vi and P */ 361 362 signed int hier_qp_en; 363 signed int hier_qp_delta[4]; 364 signed int hier_frame_num[4]; 365 } MppEncRcCfg; 366 367 typedef enum MppEncHwCfgChange_e { 368 /* qp related hardware config flag */ 369 MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0), 370 MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1), 371 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2), 372 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), 373 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), 374 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), 375 MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), 376 } MppEncHwCfgChange; 377 378 /* 379 * Hardware related rate control config 380 * 381 * This config will open some detail feature to external user to control 382 * hardware behavior directly. 383 */ 384 typedef struct MppEncHwCfg_t { 385 unsigned int change; 386 387 /* vepu541/vepu540 */ 388 signed int qp_delta_row; /* delta qp between two row in P frame */ 389 signed int qp_delta_row_i; /* delta qp between two row in I frame */ 390 unsigned int aq_thrd_i[16]; 391 unsigned int aq_thrd_p[16]; 392 signed int aq_step_i[16]; 393 signed int aq_step_p[16]; 394 } MppEncHwCfg; 395 396 /* 397 * Mpp preprocess parameter 398 */ 399 typedef enum MppEncPrepCfgChange_e { 400 MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */ 401 MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */ 402 /* transform parameter */ 403 MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on ration */ 404 MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */ 405 /* enhancement parameter */ 406 MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */ 407 MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */ 408 /* color related parameter */ 409 MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */ 410 MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */ 411 MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */ 412 MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */ 413 414 MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF), 415 } MppEncPrepCfgChange; 416 417 /* 418 * Preprocess sharpen parameter 419 * 420 * 5x5 sharpen core 421 * 422 * enable_y - enable luma sharpen 423 * enable_uv - enable chroma sharpen 424 */ 425 typedef struct { 426 unsigned int enable_y; 427 unsigned int enable_uv; 428 signed int coef[5]; 429 signed int div; 430 signed int threshold; 431 } MppEncPrepSharpenCfg; 432 433 /* 434 * input frame rotation parameter 435 * 0 - disable rotation 436 * 1 - 90 degree 437 * 2 - 180 degree 438 * 3 - 270 degree 439 */ 440 typedef enum MppEncRotationCfg_e { 441 MPP_ENC_ROT_0, 442 MPP_ENC_ROT_90, 443 MPP_ENC_ROT_180, 444 MPP_ENC_ROT_270, 445 MPP_ENC_ROT_BUTT 446 } MppEncRotationCfg; 447 448 typedef struct MppEncPrepCfg_t { 449 unsigned int change; 450 451 /* 452 * Mpp encoder input data dimension config 453 * 454 * width / height / hor_stride / ver_stride / format 455 * These information will be used for buffer allocation and rc config init 456 * The output format is always YUV420. So if input is RGB then color 457 * conversion will be done internally 458 */ 459 signed int width; 460 signed int height; 461 signed int hor_stride; 462 signed int ver_stride; 463 464 /* 465 * Mpp encoder input data format config 466 */ 467 MppFrameFormat format; 468 MppFrameColorSpace color; 469 MppFrameColorPrimaries colorprim; 470 MppFrameColorTransferCharacteristic colortrc; 471 MppFrameColorRange range; 472 473 MppEncRotationCfg rotation; 474 475 /* 476 * input frame mirroring parameter 477 * 0 - disable mirroring 478 * 1 - horizontal mirroring 479 * 2 - vertical mirroring 480 */ 481 signed int mirroring; 482 483 signed int denoise; 484 485 MppEncPrepSharpenCfg sharpen; 486 } MppEncPrepCfg; 487 488 /* 489 * Mpp Motion Detection parameter 490 * 491 * Mpp can output Motion Detection infomation for each frame. 492 * If user euqueue a encode task with KEY_MOTION_INFO by following function 493 * then encoder will output Motion Detection information to the buffer. 494 * 495 * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); 496 * 497 * Motion Detection information will be organized in this way: 498 * 1. Each 16x16 block will have a 32 bit block information which contains 499 * 15 bit SAD(Sum of Abstract Difference value 500 * 9 bit signed horizontal motion vector 501 * 8 bit signed vertical motion vector 502 * 2. The sequence of MD information in the buffer is corresponding to the 503 * block position in the frame, left-to right, top-to-bottom. 504 * 3. If the width of the frame is not a multiple of 256 pixels (16 macro 505 * blocks), DMA would extend the frame to a multiple of 256 pixels and 506 * the extended blocks' MD information are 32'h0000_0000. 507 * 4. Buffer must be ion buffer and 1024 byte aligned. 508 */ 509 typedef struct MppEncMDBlkInfo_t { 510 unsigned int sad : 15; /* bit 0~14 - SAD */ 511 signed int mvx : 9; /* bit 15~23 - signed horizontal mv */ 512 signed int mvy : 8; /* bit 24~31 - signed vertical mv */ 513 } MppEncMDBlkInfo; 514 515 typedef enum MppEncHeaderMode_e { 516 /* default mode: attach vps/sps/pps only on first frame */ 517 MPP_ENC_HEADER_MODE_DEFAULT, 518 /* IDR mode: attach vps/sps/pps on each IDR frame */ 519 MPP_ENC_HEADER_MODE_EACH_IDR, 520 MPP_ENC_HEADER_MODE_BUTT, 521 } MppEncHeaderMode; 522 523 typedef enum MppEncSeiMode_e { 524 MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ 525 MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ 526 MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ 527 } MppEncSeiMode; 528 529 /* 530 * Mpp codec parameter 531 * parameter is defined from here 532 */ 533 534 /* 535 * H.264 configurable parameter 536 */ 537 typedef enum MppEncH264CfgChange_e { 538 /* change on stream type */ 539 MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0), 540 /* change on svc / profile / level */ 541 MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1), 542 /* change on entropy_coding_mode / cabac_init_idc */ 543 MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2), 544 545 /* change on transform8x8_mode */ 546 MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4), 547 /* change on constrained_intra_pred_mode */ 548 MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5), 549 /* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */ 550 MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6), 551 /* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */ 552 MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7), 553 /* change on use_longterm */ 554 MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8), 555 /* change on scaling_list_mode */ 556 MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9), 557 /* change on poc type */ 558 MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10), 559 /* change on log2 max poc lsb minus 4 */ 560 MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11), 561 /* change on log2 max frame number minus 4 */ 562 MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12), 563 /* change on gaps_in_frame_num_value_allowed_flag */ 564 MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13), 565 566 /* change on max_qp / min_qp */ 567 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16), 568 /* change on max_qp_i / min_qp_i */ 569 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17), 570 /* change on max_qp_step */ 571 MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18), 572 /* change on qp_delta_ip */ 573 MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19), 574 /* change on intra_refresh_mode / intra_refresh_arg */ 575 MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20), 576 /* change on max long-term reference frame count */ 577 MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21), 578 /* change on max temporal id */ 579 MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22), 580 /* change on adding prefix nal */ 581 MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23), 582 /* change on base layer priority id */ 583 MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24), 584 585 /* change on vui */ 586 MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28), 587 MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF), 588 } MppEncH264CfgChange; 589 590 typedef struct MppEncH264Cfg_t { 591 unsigned int change; 592 593 /* 594 * H.264 stream format 595 * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' 596 * 1 - Plain NAL units without startcode 597 */ 598 signed int stream_type; 599 600 /* 601 * H.264 codec syntax config 602 * 603 * do NOT setup the three option below unless you are familiar with encoder detail 604 * poc_type - picture order count type 0 ~ 2 605 * log2_max_poc_lsb - used in sps with poc_type 0, 606 * log2_max_frame_num - used in sps 607 */ 608 unsigned int poc_type; 609 unsigned int log2_max_poc_lsb; 610 unsigned int log2_max_frame_num; 611 unsigned int gaps_not_allowed; 612 613 /* 614 * H.264 profile_idc parameter 615 * 66 - Baseline profile 616 * 77 - Main profile 617 * 100 - High profile 618 */ 619 signed int profile; 620 621 /* 622 * H.264 level_idc parameter 623 * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps 624 * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps 625 * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps 626 * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps 627 * 50 / 51 / 52 - 4K@30fps 628 */ 629 signed int level; 630 631 /* 632 * H.264 entropy coding method 633 * 0 - CAVLC 634 * 1 - CABAC 635 * When CABAC is select cabac_init_idc can be range 0~2 636 */ 637 signed int entropy_coding_mode; 638 signed int cabac_init_idc; 639 640 /* 641 * 8x8 intra prediction and 8x8 transform enable flag 642 * This flag can only be enable under High profile 643 * 0 : disable (BP/MP) 644 * 1 : enable (HP) 645 */ 646 signed int transform8x8_mode; 647 648 /* 649 * 0 : disable 650 * 1 : enable 651 */ 652 signed int constrained_intra_pred_mode; 653 654 /* 655 * 0 : flat scaling list 656 * 1 : default scaling list for all cases 657 * 2 : customized scaling list (not supported) 658 */ 659 signed int scaling_list_mode; 660 661 /* 662 * chroma qp offset (-12 - 12) 663 */ 664 signed int chroma_cb_qp_offset; 665 signed int chroma_cr_qp_offset; 666 667 /* 668 * H.264 deblock filter mode flag 669 * 0 : enable 670 * 1 : disable 671 * 2 : disable deblocking filter at slice boundaries 672 * 673 * deblock filter offset alpha (-6 - 6) 674 * deblock filter offset beta (-6 - 6) 675 */ 676 signed int deblock_disable; 677 signed int deblock_offset_alpha; 678 signed int deblock_offset_beta; 679 680 /* 681 * H.264 long term reference picture enable flag 682 * 0 - disable 683 * 1 - enable 684 */ 685 signed int use_longterm; 686 687 /* 688 * quality config 689 * qp_max - 8 ~ 51 690 * qp_max_i - 10 ~ 40 691 * qp_min - 8 ~ 48 692 * qp_min_i - 10 ~ 40 693 * qp_max_step - max delta qp step between two frames 694 */ 695 signed int qp_init; 696 signed short qp_max; 697 signed short qp_max_i; 698 signed short qp_min; 699 signed short qp_min_i; 700 signed short qp_max_step; 701 signed short qp_delta_ip; 702 703 /* 704 * intra fresh config 705 * 706 * intra_refresh_mode 707 * 0 - no intra refresh 708 * 1 - intra refresh by MB row 709 * 2 - intra refresh by MB column 710 * 3 - intra refresh by MB gap 711 * 712 * intra_refresh_arg 713 * mode 0 - no effect 714 * mode 1 - refresh MB row number 715 * mode 2 - refresh MB colmn number 716 * mode 3 - refresh MB gap count 717 */ 718 signed int intra_refresh_mode; 719 signed int intra_refresh_arg; 720 721 /* extra mode config */ 722 signed int max_ltr_frames; 723 signed int max_tid; 724 signed int prefix_mode; 725 signed int base_layer_pid; 726 } MppEncH264Cfg; 727 728 #define H265E_MAX_ROI_NUMBER 64 729 730 typedef struct H265eRect_t { 731 signed int left; 732 signed int right; 733 signed int top; 734 signed int bottom; 735 } H265eRect; 736 737 typedef struct H265eRoi_Region_t { 738 unsigned char level; 739 H265eRect rect; 740 } H265eRoiRegion; 741 742 /* 743 * roi region only can be setting when rc_enable = 1 744 */ 745 typedef struct MppEncH265RoiCfg_t { 746 /* 747 * the value is defined by H265eCtuMethod 748 */ 749 750 unsigned char method; 751 /* 752 * the number of roi,the value must less than H265E_MAX_ROI_NUMBER 753 */ 754 signed int num; 755 756 /* delat qp using in roi region */ 757 unsigned int delta_qp; 758 759 /* roi region */ 760 H265eRoiRegion region[H265E_MAX_ROI_NUMBER]; 761 } MppEncH265RoiCfg; 762 763 typedef struct H265eCtuQp_t { 764 /* the qp value using in ctu region */ 765 unsigned int qp; 766 767 /* 768 * define the ctu region 769 * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size 770 * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates 771 */ 772 H265eRect rect; 773 } H265eCtu; 774 775 typedef struct H265eCtuRegion_t { 776 /* 777 * the value is defined by H265eCtuMethod 778 */ 779 unsigned char method; 780 781 /* 782 * the number of ctu,the value must less than H265E_MAX_ROI_NUMBER 783 */ 784 signed int num; 785 786 /* ctu region */ 787 H265eCtu ctu[H265E_MAX_ROI_NUMBER]; 788 } MppEncH265CtuCfg; 789 790 /* 791 * define the method when set CTU/ROI parameters 792 * this value is using by method in H265eCtuRegion or H265eRoi struct 793 */ 794 typedef enum { 795 H265E_METHOD_CTU_SIZE, 796 H264E_METHOD_COORDINATE, 797 } H265eCtuMethod; 798 799 /* 800 * H.265 configurable parameter 801 */ 802 typedef struct MppEncH265VuiCfg_t { 803 unsigned int change; 804 signed int vui_present; 805 signed int vui_aspect_ratio; 806 signed int vui_sar_size; 807 signed int full_range; 808 signed int time_scale; 809 } MppEncH265VuiCfg; 810 811 typedef enum MppEncH265CfgChange_e { 812 /* change on stream type */ 813 MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0), 814 MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1), 815 MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2), 816 MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3), 817 MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4), 818 MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5), 819 MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6), 820 MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7), 821 MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8), 822 MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9), 823 MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10), 824 MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11), 825 MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12), 826 MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13), 827 MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14), 828 MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15), 829 MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16), 830 MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17), 831 MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18), 832 MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), 833 MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), 834 MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), 835 MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), 836 } MppEncH265CfgChange; 837 838 typedef struct MppEncH265SliceCfg_t { 839 /* default value: 0, means no slice split */ 840 unsigned int split_enable; 841 842 /* 0: by bits number; 1: by lcu line number */ 843 unsigned int split_mode; 844 845 /* 846 * when splitmode is 0, this value presents bits number, 847 * when splitmode is 1, this value presents lcu line number 848 */ 849 unsigned int slice_size; 850 unsigned int loop_filter_across_slices_enabled_flag; 851 } MppEncH265SliceCfg; 852 853 typedef struct MppEncH265CuCfg_t { 854 unsigned int cu32x32_en; /* default: 1 */ 855 unsigned int cu16x16_en; /* default: 1 */ 856 unsigned int cu8x8_en; /* default: 1 */ 857 unsigned int cu4x4_en; /* default: 1 */ 858 859 // intra pred 860 unsigned int constrained_intra_pred_flag; /* default: 0 */ 861 unsigned int strong_intra_smoothing_enabled_flag; /* INTRA_SMOOTH */ 862 unsigned int pcm_enabled_flag; /* default: 0, enable ipcm */ 863 unsigned int pcm_loop_filter_disabled_flag; 864 } MppEncH265CuCfg; 865 866 typedef struct MppEncH265RefCfg_t { 867 unsigned int num_lt_ref_pic; /* default: 0 */ 868 } MppEncH265RefCfg; 869 870 typedef struct MppEncH265DblkCfg_t { 871 unsigned int slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ 872 signed int slice_beta_offset_div2; /* default value: 0. [-6,+6] */ 873 signed int slice_tc_offset_div2; /* default value: 0. [-6,+6] */ 874 } MppEncH265DblkCfg_t; 875 876 typedef struct MppEncH265SaoCfg_t { 877 unsigned int slice_sao_luma_flag; 878 unsigned int slice_sao_chroma_flag; 879 } MppEncH265SaoCfg; 880 881 typedef struct MppEncH265TransCfg_t { 882 unsigned int transquant_bypass_enabled_flag; 883 unsigned int transform_skip_enabled_flag; 884 unsigned int defalut_ScalingList_enable; /* default: 0 */ 885 signed int cb_qp_offset; 886 signed int cr_qp_offset; 887 } MppEncH265TransCfg; 888 889 typedef struct MppEncH265MergeCfg_t { 890 unsigned int max_mrg_cnd; 891 unsigned int merge_up_flag; 892 unsigned int merge_left_flag; 893 } MppEncH265MergesCfg; 894 895 typedef struct MppEncH265EntropyCfg_t { 896 unsigned int cabac_init_flag; /* default: 0 */ 897 } MppEncH265EntropyCfg; 898 899 typedef struct MppEncH265Cfg_t { 900 unsigned int change; 901 902 /* H.265 codec syntax config */ 903 signed int profile; 904 signed int level; 905 signed int tier; 906 907 /* constraint intra prediction flag */ 908 signed int const_intra_pred; 909 signed int ctu_size; 910 signed int max_cu_size; 911 signed int tmvp_enable; 912 signed int amp_enable; 913 signed int wpp_enable; 914 signed int merge_range; 915 signed int sao_enable; 916 unsigned int num_ref; 917 918 /* quality config */ 919 signed int max_qp; 920 signed int min_qp; 921 signed int max_i_qp; 922 signed int min_i_qp; 923 signed int ip_qp_delta; 924 signed int max_delta_qp; 925 signed int intra_qp; 926 signed int gop_delta_qp; 927 signed int qp_init; 928 signed int qp_max_step; 929 signed int raw_dealt_qp; 930 unsigned char qpmax_map[8]; 931 unsigned char qpmin_map[8]; 932 signed int qpmap_mode; 933 934 /* intra fresh config */ 935 signed int intra_refresh_mode; 936 signed int intra_refresh_arg; 937 938 /* slice mode config */ 939 signed int independ_slice_mode; 940 signed int independ_slice_arg; 941 signed int depend_slice_mode; 942 signed int depend_slice_arg; 943 944 MppEncH265CuCfg cu_cfg; 945 MppEncH265SliceCfg slice_cfg; 946 MppEncH265EntropyCfg entropy_cfg; 947 MppEncH265TransCfg trans_cfg; 948 MppEncH265SaoCfg sao_cfg; 949 MppEncH265DblkCfg_t dblk_cfg; 950 MppEncH265RefCfg ref_cfg; 951 MppEncH265MergesCfg merge_cfg; 952 953 /* extra info */ 954 MppEncH265VuiCfg vui; 955 956 MppEncH265CtuCfg ctu; 957 MppEncH265RoiCfg roi; 958 } MppEncH265Cfg; 959 960 /* 961 * motion jpeg configurable parameter 962 */ 963 typedef enum MppEncJpegCfgChange_e { 964 /* change on quant parameter */ 965 MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0), 966 MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1), 967 MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2), 968 MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF), 969 } MppEncJpegCfgChange; 970 971 typedef struct MppEncJpegCfg_t { 972 unsigned int change; 973 signed int quant; 974 /* 975 * quality factor config 976 * 977 * q_factor - 1 ~ 99 978 * qf_max - 1 ~ 99 979 * qf_min - 1 ~ 99 980 * qtable_y: qtable for luma 981 * qtable_u: qtable for chroma 982 * qtable_v: default equal qtable_u 983 */ 984 signed int q_factor; 985 signed int qf_max; 986 signed int qf_min; 987 unsigned char *qtable_y; 988 unsigned char *qtable_u; 989 unsigned char *qtable_v; 990 } MppEncJpegCfg; 991 992 /* 993 * vp8 configurable parameter 994 */ 995 typedef enum MppEncVP8CfgChange_e { 996 MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0), 997 MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1), 998 MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF), 999 } MppEncVP8CfgChange; 1000 1001 typedef struct MppEncVp8Cfg_t { 1002 unsigned int change; 1003 signed int quant; 1004 1005 signed int qp_init; 1006 signed int qp_max; 1007 signed int qp_max_i; 1008 signed int qp_min; 1009 signed int qp_min_i; 1010 signed int qp_max_step; 1011 signed int disable_ivf; 1012 } MppEncVp8Cfg; 1013 1014 /** 1015 * @ingroup rk_mpi 1016 * @brief MPP encoder codec configuration parameters 1017 * @details The encoder codec configuration parameters are different for each 1018 * compression codings. For example, H.264 encoder can configure 1019 * profile, level, qp, etc. while jpeg encoder can configure qp 1020 * only. The detailed parameters can refer the corresponding data 1021 * structure such as MppEncH264Cfg and MppEncJpegCfg. This data 1022 * structure is associated with MPP_ENC_SET_CODEC_CFG command. 1023 */ 1024 typedef struct MppEncCodecCfg_t { 1025 MppCodingType coding; 1026 1027 union { 1028 unsigned int change; 1029 MppEncH264Cfg h264; 1030 MppEncH265Cfg h265; 1031 MppEncJpegCfg jpeg; 1032 MppEncVp8Cfg vp8; 1033 }; 1034 } MppEncCodecCfg; 1035 1036 typedef enum MppEncSliceSplit_e { 1037 /* change on quant parameter */ 1038 MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), 1039 MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), 1040 MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1041 } MppEncSliceSplitChange; 1042 1043 typedef enum MppEncSplitMode_e { 1044 MPP_ENC_SPLIT_NONE, 1045 MPP_ENC_SPLIT_BY_BYTE, 1046 MPP_ENC_SPLIT_BY_CTU, 1047 } MppEncSplitMode; 1048 1049 typedef struct MppEncSliceSplit_t { 1050 unsigned int change; 1051 1052 /* 1053 * slice split mode 1054 * 1055 * MPP_ENC_SPLIT_NONE - No slice is split 1056 * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number 1057 * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number 1058 */ 1059 unsigned int split_mode; 1060 1061 /* 1062 * slice split size parameter 1063 * 1064 * When split by byte number this value is the max byte number for each 1065 * slice. 1066 * When split by macroblock / ctu number this value is the MB/CTU number 1067 * for each slice. 1068 */ 1069 unsigned int split_arg; 1070 } MppEncSliceSplit; 1071 1072 /** 1073 * @brief Mpp ROI parameter 1074 * Region configure define a rectangle as ROI 1075 * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. 1076 * These parameters MUST retain in memory when encoder is running. 1077 * Both absolute qp and relative qp are supported in vepu541. 1078 * Only absolute qp is supported in rv1108 1079 */ 1080 typedef struct MppEncROIRegion_t { 1081 unsigned short x; /**< horizontal position of top left corner */ 1082 unsigned short y; /**< vertical position of top left corner */ 1083 unsigned short w; /**< width of ROI rectangle */ 1084 unsigned short h; /**< height of ROI rectangle */ 1085 unsigned short intra; /**< flag of forced intra macroblock */ 1086 signed short quality; /**< absolute / relative qp of macroblock */ 1087 unsigned short qp_area_idx; /**< qp min max area select*/ 1088 unsigned char area_map_en; /**< enable area map */ 1089 unsigned char abs_qp_en; /**< absolute qp enable flag*/ 1090 } MppEncROIRegion; 1091 1092 /** 1093 * @brief MPP encoder's ROI configuration 1094 */ 1095 typedef struct MppEncROICfg_t { 1096 unsigned int number; /**< ROI rectangle number */ 1097 MppEncROIRegion *regions; /**< ROI parameters */ 1098 } MppEncROICfg; 1099 1100 /* 1101 * Mpp OSD parameter 1102 * 1103 * Mpp OSD support total 8 regions 1104 * Mpp OSD support 256-color palette two mode palette: 1105 * 1. Configurable OSD palette 1106 * When palette is set. 1107 * 2. fixed OSD palette 1108 * When palette is NULL. 1109 * 1110 * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, 1111 * every level composed of 32 bits defined below: 1112 * Y : 8 bits 1113 * U : 8 bits 1114 * V : 8 bits 1115 * alpha : 8 bits 1116 */ 1117 #define MPP_ENC_OSD_PLT_WHITE ((255 << 24) | (128 << 16) | (128 << 8) | 235) 1118 #define MPP_ENC_OSD_PLT_YELLOW ((255 << 24) | (146 << 16) | (16 << 8) | 210) 1119 #define MPP_ENC_OSD_PLT_CYAN ((255 << 24) | (16 << 16) | (166 << 8) | 170) 1120 #define MPP_ENC_OSD_PLT_GREEN ((255 << 24) | (34 << 16) | (54 << 8) | 145) 1121 #define MPP_ENC_OSD_PLT_TRANS ((0 << 24) | (222 << 16) | (202 << 8) | 106) 1122 #define MPP_ENC_OSD_PLT_RED ((255 << 24) | (240 << 16) | (90 << 8) | 81) 1123 #define MPP_ENC_OSD_PLT_BLUE ((255 << 24) | (110 << 16) | (240 << 8) | 41) 1124 #define MPP_ENC_OSD_PLT_BLACK ((255 << 24) | (128 << 16) | (128 << 8) | 16) 1125 1126 typedef enum MppEncOSDPltType_e { 1127 MPP_ENC_OSD_PLT_TYPE_DEFAULT, 1128 MPP_ENC_OSD_PLT_TYPE_USERDEF, 1129 MPP_ENC_OSD_PLT_TYPE_BUTT, 1130 } MppEncOSDPltType; 1131 1132 /* OSD palette value define */ 1133 typedef union MppEncOSDPltVal_u { 1134 struct { 1135 unsigned int v : 8; 1136 unsigned int u : 8; 1137 unsigned int y : 8; 1138 unsigned int alpha : 8; 1139 }; 1140 unsigned int val; 1141 } MppEncOSDPltVal; 1142 1143 typedef struct MppEncOSDPlt_t { 1144 MppEncOSDPltVal data[256]; 1145 } MppEncOSDPlt; 1146 1147 typedef enum MppEncOSDPltCfgChange_e { 1148 MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ 1149 MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ 1150 MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1151 } MppEncOSDPltCfgChange; 1152 1153 typedef struct MppEncOSDPltCfg_t { 1154 unsigned int change; 1155 MppEncOSDPltType type; 1156 MppEncOSDPlt *plt; 1157 } MppEncOSDPltCfg; 1158 1159 /* position info is unit in 16 pixels(one MB), and 1160 * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; 1161 * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; 1162 */ 1163 typedef struct MppEncOSDRegion_t { 1164 unsigned int enable; 1165 unsigned int inverse; 1166 unsigned int start_mb_x; 1167 unsigned int start_mb_y; 1168 unsigned int num_mb_x; 1169 unsigned int num_mb_y; 1170 unsigned int buf_offset; 1171 } MppEncOSDRegion; 1172 1173 /* if num_region > 0 && region==NULL 1174 * use old osd data 1175 */ 1176 typedef struct MppEncOSDData_t { 1177 MppBuffer buf; 1178 unsigned int num_region; 1179 MppEncOSDRegion region[8]; 1180 } MppEncOSDData; 1181 1182 typedef struct MppEncOSDRegion2_t { 1183 unsigned int enable; 1184 unsigned int inverse; 1185 unsigned int start_mb_x; 1186 unsigned int start_mb_y; 1187 unsigned int num_mb_x; 1188 unsigned int num_mb_y; 1189 unsigned int buf_offset; 1190 MppBuffer buf; 1191 } MppEncOSDRegion2; 1192 1193 typedef struct MppEncOSDData2_t { 1194 unsigned int num_region; 1195 MppEncOSDRegion2 region[8]; 1196 } MppEncOSDData2; 1197 1198 typedef struct MppEncUserData_t { 1199 unsigned int len; 1200 void *pdata; 1201 } MppEncUserData; 1202 1203 typedef struct MppEncUserDataFull_t { 1204 unsigned int len; 1205 unsigned char *uuid; 1206 void *pdata; 1207 } MppEncUserDataFull; 1208 1209 typedef struct MppEncUserDataSet_t { 1210 unsigned int count; 1211 MppEncUserDataFull *datas; 1212 } MppEncUserDataSet; 1213 1214 #endif /* __RK_VENC_CMD_H__ */ 1215