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1 /*
2  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef __VPU_H__
17 #define __VPU_H__
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 #define VPU_SUCCESS (0)
24 #define VPU_FAILURE (-1)
25 
26 #define VPU_HW_WAIT_OK VPU_SUCCESS
27 #define VPU_HW_WAIT_ERROR VPU_FAILURE
28 #define VPU_HW_WAIT_TIMEOUT 1
29 
30 // vpu decoder 60 registers, size 240B
31 #define VPU_REG_NUM_DEC (60)
32 // vpu post processor 41 registers, size 164B
33 #define VPU_REG_NUM_PP (41)
34 // vpu decoder + post processor 101 registers, size 404B
35 #define VPU_REG_NUM_DEC_PP (VPU_REG_NUM_DEC + VPU_REG_NUM_PP)
36 // vpu encoder 96 registers, size 384B
37 #define VPU_REG_NUM_ENC (96)
38 
39 typedef enum {
40     VPU_ENC = 0x0,
41     VPU_DEC = 0x1,
42     VPU_PP = 0x2,
43     VPU_DEC_PP = 0x3,
44     VPU_DEC_HEVC = 0x4,
45     VPU_DEC_RKV = 0x5,
46     VPU_ENC_RKV = 0x6,
47     VPU_DEC_AVS = 0x7,
48     VPU_ENC_VEPU22 = 0x8,
49     VPU_TYPE_BUTT,
50 } VPU_CLIENT_TYPE;
51 
52 /* Hardware decoder configuration description */
53 
54 typedef struct VPUHwDecConfig {
55     unsigned int maxDecPicWidth;       /* Maximum video decoding width supported  */
56     unsigned int maxPpOutPicWidth;     /* Maximum output width of Post-Processor */
57     unsigned int h264Support;          /* HW supports h.264 */
58     unsigned int jpegSupport;          /* HW supports JPEG */
59     unsigned int mpeg4Support;         /* HW supports MPEG-4 */
60     unsigned int customMpeg4Support;   /* HW supports custom MPEG-4 features */
61     unsigned int vc1Support;           /* HW supports VC-1 Simple */
62     unsigned int mpeg2Support;         /* HW supports MPEG-2 */
63     unsigned int ppSupport;            /* HW supports post-processor */
64     unsigned int ppConfig;             /* HW post-processor functions bitmask */
65     unsigned int sorensonSparkSupport; /* HW supports Sorenson Spark */
66     unsigned int refBufSupport;        /* HW supports reference picture buffering */
67     unsigned int vp6Support;           /* HW supports VP6 */
68     unsigned int vp7Support;           /* HW supports VP7 */
69     unsigned int vp8Support;           /* HW supports VP8 */
70     unsigned int avsSupport;           /* HW supports AVS */
71     unsigned int jpegESupport;         /* HW supports JPEG extensions */
72     unsigned int rvSupport;            /* HW supports REAL */
73     unsigned int mvcSupport;           /* HW supports H264 MVC extension */
74 } VPUHwDecConfig_t;
75 
76 /* Hardware encoder configuration description */
77 
78 typedef struct VPUHwEndConfig {
79     unsigned int maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */
80     unsigned int h264Enabled;     /* HW supports H.264 */
81     unsigned int jpegEnabled;     /* HW supports JPEG */
82     unsigned int mpeg4Enabled;    /* HW supports MPEG-4 */
83     unsigned int vsEnabled;       /* HW supports video stabilization */
84     unsigned int rgbEnabled;      /* HW supports RGB input */
85     unsigned int reg_size;        /* HW bus type in use */
86     unsigned int reserv[2];
87 } VPUHwEncConfig_t;
88 
89 typedef enum {
90     // common command
91     VPU_CMD_REGISTER,
92     VPU_CMD_REGISTER_ACK_OK,
93     VPU_CMD_REGISTER_ACK_FAIL,
94     VPU_CMD_UNREGISTER,
95 
96     VPU_SEND_CONFIG,
97     VPU_SEND_CONFIG_ACK_OK,
98     VPU_SEND_CONFIG_ACK_FAIL,
99 
100     VPU_GET_HW_INFO,
101     VPU_GET_HW_INFO_ACK_OK,
102     VPU_GET_HW_INFO_ACK_FAIL,
103 
104     VPU_CMD_BUTT,
105 } VPU_CMD_TYPE;
106 
107 int VPUClientInit(VPU_CLIENT_TYPE type);
108 signed int VPUClientRelease(int socket);
109 signed int VPUClientSendReg(int socket, unsigned int *regs, unsigned int nregs);
110 signed int VPUClientSendReg2(signed int socket, signed int offset, signed int size, void *param);
111 signed int VPUClientWaitResult(int socket, unsigned int *regs, unsigned int nregs, VPU_CMD_TYPE *cmd, signed int *len);
112 signed int VPUClientGetHwCfg(int socket, unsigned int *cfg, unsigned int cfg_size);
113 signed int VPUClientGetIOMMUStatus(void);
114 unsigned int VPUCheckSupportWidth(void);
115 
116 #ifdef __cplusplus
117 }
118 #endif
119 
120 #endif /* __VPU_H__ */
121