1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 */ 5 6 #ifndef _PINCTRL_ROCKCHIP_H 7 #define _PINCTRL_ROCKCHIP_H 8 9 enum rockchip_pinctrl_type { 10 PX30, 11 RV1108, 12 RV1126, 13 RK1808, 14 RK2928, 15 RK3066B, 16 RK3128, 17 RK3188, 18 RK3288, 19 RK3308, 20 RK3368, 21 RK3399, 22 RK3568, 23 }; 24 25 struct rockchip_gpio_regs { 26 u32 port_dr; 27 u32 port_ddr; 28 u32 int_en; 29 u32 int_mask; 30 u32 int_type; 31 u32 int_polarity; 32 u32 int_bothedge; 33 u32 int_status; 34 u32 int_rawstatus; 35 u32 debounce; 36 u32 dbclk_div_en; 37 u32 dbclk_div_con; 38 u32 port_eoi; 39 u32 ext_port; 40 u32 version_id; 41 }; 42 43 /** 44 * @type: iomux variant using IOMUX_* constants 45 * @offset: if initialized to -1 it will be autocalculated, by specifying 46 * an initial offset value the relevant source offset can be reset 47 * to a new value for autocalculating the following iomux registers. 48 */ 49 struct rockchip_iomux { 50 int type; 51 int offset; 52 }; 53 54 /** 55 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 56 */ 57 enum rockchip_pin_drv_type { 58 DRV_TYPE_IO_DEFAULT = 0, 59 DRV_TYPE_IO_1V8_OR_3V0, 60 DRV_TYPE_IO_1V8_ONLY, 61 DRV_TYPE_IO_1V8_3V0_AUTO, 62 DRV_TYPE_IO_3V3_ONLY, 63 DRV_TYPE_MAX 64 }; 65 66 /** 67 * enum type index corresponding to rockchip_pull_list arrays index. 68 */ 69 enum rockchip_pin_pull_type { PULL_TYPE_IO_DEFAULT = 0, PULL_TYPE_IO_1V8_ONLY, PULL_TYPE_MAX }; 70 71 /** 72 * enum mux route register type, should be invalid/default/topgrf/pmugrf. 73 * INVALID: means do not need to set mux route 74 * DEFAULT: means same regmap as pin iomux 75 * TOPGRF: means mux route setting in topgrf 76 * PMUGRF: means mux route setting in pmugrf 77 */ 78 enum rockchip_pin_route_type { 79 ROUTE_TYPE_DEFAULT = 0, 80 ROUTE_TYPE_TOPGRF = 1, 81 ROUTE_TYPE_PMUGRF = 2, 82 83 ROUTE_TYPE_INVALID = -1, 84 }; 85 86 enum rockchip_mux_route_location { 87 ROCKCHIP_ROUTE_SAME = 0, 88 ROCKCHIP_ROUTE_PMU, 89 ROCKCHIP_ROUTE_GRF, 90 }; 91 92 /** 93 * @drv_type: drive strength variant using rockchip_perpin_drv_type 94 * @offset: if initialized to -1 it will be autocalculated, by specifying 95 * an initial offset value the relevant source offset can be reset 96 * to a new value for autocalculating the following drive strength 97 * registers. if used chips own cal_drv func instead to calculate 98 * registers offset, the variant could be ignored. 99 */ 100 struct rockchip_drv { 101 enum rockchip_pin_drv_type drv_type; 102 int offset; 103 }; 104 105 /** 106 * @dev: device of the gpio bank 107 * @reg_base: register base of the gpio bank 108 * @reg_pull: optional separate register for additional pull settings 109 * @clk: clock of the gpio bank 110 * @db_clk: clock of the gpio debounce 111 * @irq: interrupt of the gpio bank 112 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 113 * @pin_base: first pin number 114 * @nr_pins: number of pins in this bank 115 * @name: name of the bank 116 * @bank_num: number of the bank, to account for holes 117 * @iomux: array describing the 4 iomux sources of the bank 118 * @drv: array describing the 4 drive strength sources of the bank 119 * @pull_type: array describing the 4 pull type sources of the bank 120 * @of_node: dt node of this bank 121 * @drvdata: common pinctrl basedata 122 * @domain: irqdomain of the gpio bank 123 * @gpio_chip: gpiolib chip 124 * @grange: gpio range 125 * @slock: spinlock for the gpio bank 126 * @route_mask: bits describing the routing pins of per bank 127 */ 128 struct rockchip_pin_bank { 129 struct device *dev; 130 131 void __iomem *reg_base; 132 struct regmap *regmap_pull; 133 struct clk *clk; 134 struct clk *db_clk; 135 int irq; 136 u32 saved_masks; 137 u32 pin_base; 138 u8 nr_pins; 139 char *name; 140 u8 bank_num; 141 struct rockchip_iomux iomux[4]; 142 struct rockchip_drv drv[4]; 143 enum rockchip_pin_pull_type pull_type[4]; 144 struct device_node *of_node; 145 struct rockchip_pinctrl *drvdata; 146 struct irq_domain *domain; 147 struct gpio_chip gpio_chip; 148 struct pinctrl_gpio_range grange; 149 raw_spinlock_t slock; 150 const struct rockchip_gpio_regs *gpio_regs; 151 u32 gpio_type; 152 u32 toggle_edge_mode; 153 u32 recalced_mask; 154 u32 route_mask; 155 }; 156 157 /** 158 * struct rockchip_mux_recalced_data: represent a pin iomux data. 159 * @num: bank number. 160 * @pin: pin number. 161 * @bit: index at register. 162 * @reg: register offset. 163 * @mask: mask bit 164 */ 165 struct rockchip_mux_recalced_data { 166 u8 num; 167 u8 pin; 168 u32 reg; 169 u8 bit; 170 u8 mask; 171 }; 172 173 /** 174 * struct rockchip_mux_recalced_data: represent a pin iomux data. 175 * @bank_num: bank number. 176 * @pin: index at register or used to calc index. 177 * @func: the min pin. 178 * @route_location: the mux route location (same, pmu, grf). 179 * @route_offset: the max pin. 180 * @route_val: the register offset. 181 */ 182 struct rockchip_mux_route_data { 183 u8 bank_num; 184 u8 pin; 185 u8 func; 186 enum rockchip_mux_route_location route_location; 187 u32 route_offset; 188 u32 route_val; 189 }; 190 191 struct rockchip_pin_ctrl { 192 struct rockchip_pin_bank *pin_banks; 193 u32 nr_banks; 194 u32 nr_pins; 195 char *label; 196 enum rockchip_pinctrl_type type; 197 int grf_mux_offset; 198 int pmu_mux_offset; 199 int grf_drv_offset; 200 int pmu_drv_offset; 201 struct rockchip_mux_recalced_data *iomux_recalced; 202 u32 niomux_recalced; 203 struct rockchip_mux_route_data *iomux_routes; 204 u32 niomux_routes; 205 206 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 207 208 int (*soc_data_init)(struct rockchip_pinctrl *info); 209 210 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); 211 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); 212 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); 213 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); 214 }; 215 216 struct rockchip_pin_config { 217 unsigned int func; 218 unsigned long *configs; 219 unsigned int nconfigs; 220 }; 221 222 /** 223 * struct rockchip_pin_group: represent group of pins of a pinmux function. 224 * @name: name of the pin group, used to lookup the group. 225 * @pins: the pins included in this group. 226 * @npins: number of pins included in this group. 227 * @func: the mux function number to be programmed when selected. 228 * @configs: the config values to be set for each pin 229 * @nconfigs: number of configs for each pin 230 */ 231 struct rockchip_pin_group { 232 const char *name; 233 unsigned int npins; 234 unsigned int *pins; 235 struct rockchip_pin_config *data; 236 }; 237 238 /** 239 * struct rockchip_pmx_func: represent a pin function. 240 * @name: name of the pin function, used to lookup the function. 241 * @groups: one or more names of pin groups that provide this function. 242 * @num_groups: number of groups included in @groups. 243 */ 244 struct rockchip_pmx_func { 245 const char *name; 246 const char **groups; 247 u8 ngroups; 248 }; 249 250 struct rockchip_pinctrl { 251 struct regmap *regmap_base; 252 int reg_size; 253 struct regmap *regmap_pull; 254 struct regmap *regmap_pmu; 255 struct device *dev; 256 struct rockchip_pin_ctrl *ctrl; 257 struct pinctrl_desc pctl; 258 struct pinctrl_dev *pctl_dev; 259 struct rockchip_pin_group *groups; 260 unsigned int ngroups; 261 struct rockchip_pmx_func *functions; 262 unsigned int nfunctions; 263 }; 264 265 #endif 266