1 // SPDX-License-Identifier: GPL-2.0+
2 /* Synopsys DesignWare 8250 library. */
3
4 #include <linux/bitops.h>
5 #include <linux/device.h>
6 #include <linux/io.h>
7 #include <linux/kernel.h>
8 #include <linux/serial_8250.h>
9 #include <linux/serial_core.h>
10
11 #include "8250_dwlib.h"
12
13 /* Offsets for the DesignWare specific registers */
14 #define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
15 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
16 #define DW_UART_UCV 0xf8 /* UART Component Version */
17
18 /* Component Parameter Register bits */
19 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
20 #define DW_UART_CPR_AFCE_MODE (1 << 4)
21 #define DW_UART_CPR_THRE_MODE (1 << 5)
22 #define DW_UART_CPR_SIR_MODE (1 << 6)
23 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
24 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
25 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
26 #define DW_UART_CPR_FIFO_STAT (1 << 10)
27 #define DW_UART_CPR_SHADOW (1 << 11)
28 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
29 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
30 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
31
32 /* Helper for FIFO size calculation */
33 #define DW_UART_CPR_FIFO_SIZE(a) ((((a) >> 16) & 0xff) * 16)
34
35 #define DWLIB_THREE 3
36 #define DWLIB_FOUR 4
37 #define DWLIB_EIGHT 8
38 #define DWLIB_SIXTEEN 16
39 #define DWLIB_EIGHT_TWENTYFOUR 24
40
dw8250_readl_ext(struct uart_port * p,int offset)41 static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
42 {
43 if (p->iotype == UPIO_MEM32BE) {
44 return ioread32be(p->membase + offset);
45 }
46 return readl(p->membase + offset);
47 }
48
dw8250_writel_ext(struct uart_port * p,int offset,u32 reg)49 static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
50 {
51 if (p->iotype == UPIO_MEM32BE) {
52 iowrite32be(reg, p->membase + offset);
53 } else {
54 writel(reg, p->membase + offset);
55 }
56 }
57
58 /*
59 * divisor = div(I) + div(F)
60 * "I" means integer, "F" means fractional
61 * quot = div(I) = clk / (16 * baud)
62 * frac = div(F) * 2^dlf_size
63 *
64 * let rem = clk % (16 * baud)
65 * we have: div(F) * (16 * baud) = rem
66 * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
67 */
dw8250_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)68 static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud, unsigned int *frac)
69 {
70 unsigned int quot, rem, base_baud = baud * 16;
71 struct dw8250_port_data *d = p->private_data;
72
73 quot = p->uartclk / base_baud;
74 rem = p->uartclk % base_baud;
75 *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
76
77 return quot;
78 }
79
dw8250_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)80 static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, unsigned int quot, unsigned int quot_frac)
81 {
82 dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
83 serial8250_do_set_divisor(p, baud, quot, quot_frac);
84 }
85
dw8250_setup_port(struct uart_port * p)86 void dw8250_setup_port(struct uart_port *p)
87 {
88 struct uart_8250_port *up = up_to_u8250p(p);
89 u32 reg;
90
91 /*
92 * If the Component Version Register returns zero, we know that
93 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
94 */
95 reg = dw8250_readl_ext(p, DW_UART_UCV);
96 if (!reg) {
97 return;
98 }
99
100 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", (reg >> DWLIB_EIGHT_TWENTYFOUR) & 0xff,
101 (reg >> DWLIB_SIXTEEN) & 0xff, (reg >> DWLIB_EIGHT) & 0xff);
102
103 dw8250_writel_ext(p, DW_UART_DLF, ~0U);
104 reg = dw8250_readl_ext(p, DW_UART_DLF);
105 dw8250_writel_ext(p, DW_UART_DLF, 0);
106
107 if (reg) {
108 struct dw8250_port_data *d = p->private_data;
109
110 d->dlf_size = fls(reg);
111 p->get_divisor = dw8250_get_divisor;
112 p->set_divisor = dw8250_set_divisor;
113 }
114
115 reg = dw8250_readl_ext(p, DW_UART_CPR);
116 #ifdef CONFIG_ARCH_ROCKCHIP
117 /*
118 * The UART CPR may be 0 of some rockchip soc,
119 * but it supports fifo and AFC, fifo entry is 32 default.
120 */
121 if (reg == 0) {
122 reg = 0x00023ff2;
123 }
124 #endif
125 if (!reg) {
126 return;
127 }
128
129 /* Select the type based on FIFO */
130 if (reg & DW_UART_CPR_FIFO_MODE) {
131 p->type = PORT_16550A;
132 p->flags |= UPF_FIXED_TYPE;
133 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
134 #ifdef CONFIG_ARCH_ROCKCHIP
135 up->tx_loadsz = p->fifosize * DWLIB_THREE / DWLIB_FOUR;
136 #endif
137 up->capabilities = UART_CAP_FIFO;
138 }
139
140 if (reg & DW_UART_CPR_AFCE_MODE) {
141 up->capabilities |= UART_CAP_AFE;
142 }
143
144 if (reg & DW_UART_CPR_SIR_MODE) {
145 up->capabilities |= UART_CAP_IRDA;
146 }
147 }
148 EXPORT_SYMBOL_GPL(dw8250_setup_port);
149