1 /* 2 * Copyright (c) 2022 FuZhou Lockzhiner Electronic Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __SOC_H 17 #define __SOC_H 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #ifndef __ASSEMBLY__ 23 /* ================================================================================ */ 24 /* ================ DMA REQ =============== */ 25 /* ================================================================================ */ 26 typedef enum { 27 DMA_REQ_UART0_TX = 0, 28 DMA_REQ_UART0_RX = 1, 29 DMA_REQ_UART1_TX = 2, 30 DMA_REQ_UART1_RX = 3, 31 DMA_REQ_SPI0_TX = 4, 32 DMA_REQ_SPI0_RX = 5, 33 DMA_REQ_SPI1_TX = 6, 34 DMA_REQ_SPI1_RX = 7, 35 DMA_REQ_PWM = 8, 36 DMA_REQ_AUDIOPWM = 9, 37 DMA_REQ_I2S0_TX = 10, 38 DMA_REQ_I2S0_RX = 11, 39 DMA_REQ_I2S1_TX = 12, 40 DMA_REQ_I2S1_RX = 13, 41 DMA_REQ_PDM = 14, 42 DMA_REQ_VOP = 15, 43 } DMA_REQ_Type; 44 45 /* ================================================================================ */ 46 /* ================ IRQ ================ */ 47 /* ================================================================================ */ 48 typedef enum { 49 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 50 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 51 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 52 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 53 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 54 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 55 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 56 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 57 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 58 /****** RK2206 specific Interrupt Numbers **********************************************************************/ 59 DMAC_CH0_IRQn = 0, 60 WDT0_IRQn = 1, 61 TOUCH_NEG_IRQn = 2, 62 DMAC_CH1_IRQn = 3, 63 TIMER0_IRQn = 4, 64 TIMER1_IRQn = 5, 65 TIMER2_IRQn = 6, 66 TIMER3_IRQn = 7, 67 TIMER4_IRQn = 8, 68 TIMER5_IRQn = 9, 69 TIMER6_IRQn = 10, 70 I2C0_IRQn = 11, 71 I2C1_IRQn = 12, 72 I2C2_IRQn = 13, 73 SPIMST0_IRQn = 14, 74 SPIMST1_IRQn = 15, 75 UART0_IRQn = 16, 76 UART1_IRQn = 17, 77 UART2_IRQn = 18, 78 PWM_4CH_0_IRQn = 19, 79 PWM_4CH_1_IRQn = 20, 80 PWM_4CH_2_IRQn = 21, 81 SARADC_IRQn = 22, 82 B2A0_INT0_IRQn = 23, 83 B2A0_INT1_IRQn = 24, 84 B2A0_INT2_IRQn = 25, 85 B2A0_INT3_IRQn = 26, 86 B2A1_INT0_IRQn = 27, 87 B2A1_INT1_IRQn = 28, 88 B2A1_INT2_IRQn = 29, 89 B2A1_INT3_IRQn = 30, 90 FSPI0_IRQn = 31, 91 FSPI1_IRQn = 32, 92 VOP_INTR_IRQn = 33, 93 CACHE0_I_IRQn = 34, 94 CACHE0_D_IRQn = 35, 95 DSP_ERROR_IRQn = 36, 96 HYPERX8_IRQn = 37, 97 USB2OTG_IRQn = 38, 98 USB2OTG_BVALID_IRQn = 39, 99 USB2OTG_ID_IRQn = 40, 100 USB2OTG_LINESTATE_IRQn = 41, 101 USB2OTG_DISCONNECT_IRQn = 42, 102 SD_MMC_IRQn = 43, 103 ADUPWM_IRQn = 44, 104 PVTM_IRQn = 45, 105 CRYPTO_IRQn = 46, 106 VICAP_IRQn = 47, 107 PMU_IRQn = 48, 108 GPIO0_IRQn = 49, 109 GPIO1_IRQn = 50, 110 TRIM_IRQn = 51, 111 I2S0_IRQn = 52, 112 I2S1_IRQn = 53, 113 PDM_IRQn = 54, 114 VAD_IRQn = 55, 115 EFUSE_IRQn = 56, 116 TOUCH_IRQn = 57, 117 PMIC_IRQn = 58, 118 SPISLV0_IRQn = 59, 119 DMAC_CH2_IRQn = 60, 120 DMAC_CH3_IRQn = 61, 121 DMAC_CH4_IRQn = 62, 122 DMAC_CH5_IRQn = 63, 123 TSADC_IRQn = 64, 124 NUM_INTERRUPTS 125 } IRQn_Type; 126 #endif /* __ASSEMBLY__ */ 127 128 #define NVIC_PERIPH_IRQ_NUM MAX_IRQn 129 #define NVIC_PERIPH_IRQ_OFFSET 16 130 131 /* ================================================================================ */ 132 /* ================ Processor and Core Peripheral Section ================ */ 133 /* ================================================================================ */ 134 135 #define __CM4_REV 0x0001U /* Core revision r0p1 */ 136 #define __MPU_PRESENT 1U /* RK2206 provides an MPU */ 137 #define __VTOR_PRESENT 1U /* VTOR present */ 138 #define __NVIC_PRIO_BITS 3U /* RK2206 uses 3 Bits for the Priority Levels */ 139 #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ 140 #define __FPU_PRESENT 1U /* FPU present */ 141 #define PLL_INPUT_OSC_RATE (40000000U) /* RK2206 OSC Rate */ 142 143 #ifndef __ASSEMBLY__ 144 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 145 #include "system_rk2206.h" 146 #endif /* __ASSEMBLY__ */ 147 #include "rk2206.h" 148 #include "rk2206_usb.h" 149 150 /****************************************************************************************/ 151 /* */ 152 /* Module Structure Section */ 153 /* */ 154 /****************************************************************************************/ 155 #ifndef __ASSEMBLY__ 156 /* SPINLOCK Register Structure Define */ 157 struct SPINLOCK_REG { 158 __IO uint32_t STATUS[64]; /* Address Offset: 0x0000 */ 159 }; 160 #endif 161 /****************************************************************************************/ 162 /* */ 163 /* Module Address Section */ 164 /* */ 165 /****************************************************************************************/ 166 /* Memory Base */ 167 #define XIP_MAP0_BASE0 0x10000000U /* FSPI0 map address0 */ 168 #define XIP_MAP1_BASE0 0x18000000U /* HYPERBUS/FSPI1 map address0 */ 169 #define DSP_ITCM_BASE 0x20400000U /* DSP itcm base address */ 170 #define DSP_ITCM_END 0x20407fffU /* DSP itcm end address */ 171 #define DSP_DTCM_BASE 0x20600000U /* DSP dtcm base address */ 172 #define DSP_DTCM_END 0x2062ffffU /* DSP dtcm end address */ 173 #define XIP_MAP0_BASE1 0x30000000U /* FSPI0 map address1 */ 174 #define XIP_MAP1_BASE1 0x38000000U /* HYPERBUS/FSPI1 map address1 */ 175 #define SDMMC_BASE MMC_BASE /* MMC base address */ 176 #define USB_BASE 0x43040000U /* USB base address */ 177 #define USB_SNPS_PHY_BASE 0x41050340U /* USB SYSNOPSYS PHY base address */ 178 #define USB_PHY_CON_BASE (GRF->SOC_UOC2) /* USB PHY control base address */ 179 /****************************************************************************************/ 180 /* */ 181 /* Module Variable Section */ 182 /* */ 183 /****************************************************************************************/ 184 /* Module Variable Define */ 185 #define USB ((struct USB_GLOBAL_REG *) USB_BASE) 186 #define SPINLOCK ((struct SPINLOCK_REG *) GRF->HW_SPINLOCK) 187 188 #define IS_PCD_INSTANCE(instance) ((instance) == USB) 189 #define IS_HCD_INSTANCE(instance) ((instance) == USB) 190 #define IS_SPINLOCK_INSTANCE(instance) ((instance) == SPINLOCK) 191 192 /****************************************************************************************/ 193 /* */ 194 /* Register Bitmap Section */ 195 /* */ 196 /****************************************************************************************/ 197 /*****************************************CACHE******************************************/ 198 /* CACHE LINE SIZE */ 199 #define CACHE_LINE_SHIFT (5U) 200 #define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) 201 #define CACHE_LINE_ADDR_MASK (0xFFFFFFFFU << CACHE_LINE_SHIFT) 202 #define CACHE_M_CLEAN 0x0U 203 #define CACHE_M_INVALID 0x2U 204 #define CACHE_M_CLEAN_INVALID 0x4U 205 #define CACHE_M_INVALID_ALL 0x6U 206 207 #define CACHE_REVISION DCACHE_REVISION 208 /*****************************************TIMER******************************************/ 209 #define TIMER_CHAN_CNT 7 210 /*****************************************MBOX*******************************************/ 211 #define MBOX_CNT 2 212 #define MBOX_CHAN_CNT 4 213 /*****************************************DMA********************************************/ 214 #define DMA_NUM_CHANNELS 6 215 /*****************************************FSPI*******************************************/ 216 #define FSPI_CHIP_CNT (0x2U) 217 /*****************************************PMU********************************************/ 218 #ifndef __ASSEMBLY__ 219 typedef enum PD_Id { 220 PD_INVALID = 0, 221 } ePD_Id; 222 #endif 223 /*****************************************USB********************************************/ 224 #define USB_PHY_SUSPEND_MASK \ 225 (GRF_SOC_UOC2_OTGPHY_SOFT_CON_SEL_MASK | GRF_SOC_UOC2_GRF_CON_OTG_UTMI_SUSPEND_N_MASK) 226 #define USB_PHY_RESUME_MASK \ 227 (GRF_SOC_UOC2_OTGPHY_SOFT_CON_SEL_MASK | GRF_SOC_UOC2_GRF_CON_OTG_UTMI_SUSPEND_N_MASK) 228 #define USB_PHY_CON_SHIFT GRF_SOC_UOC2_OTGPHY_SOFT_CON_SEL_SHIFT 229 #define USB_PHY_SUSPEND_VAL 0x01U 230 #define USB_PHY_RESUME_VAL 0x02U 231 232 #ifdef __cplusplus 233 } 234 #endif /* __cplusplus */ 235 #endif /* __SOC_H */ 236