1 /* 2 * Copyright (c) 2022 FuZhou Lockzhiner Electronic Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _LINK_H 17 #define _LINK_H 18 19 #ifdef __cplusplus 20 #if __cplusplus 21 extern "C" { 22 #endif /* __cplusplus */ 23 #endif /* __cplusplus */ 24 25 #define PART_BLOCK_SIZE 0X200 // 512Byte 26 #define PART_SYSTEM_ADDR 0x00 27 #define PART_SYSTEM_BLOCKS 0x80 // 64K 28 #define PART_LOADER_ADDR (PART_SYSTEM_ADDR + PART_SYSTEM_BLOCKS * PART_BLOCK_SIZE) 29 #define PART_LOADER_BLOCKS 0x80 // 64K 30 #define PART_LITEOS_ADDR (PART_LOADER_ADDR + PART_LOADER_BLOCKS * PART_BLOCK_SIZE) 31 #define PART_LITEOS_BLOCKS 0x0F00 // (1M - 128K) 32 #define PART_ROOTFS_ADDR (PART_LITEOS_ADDR + PART_LITEOS_BLOCKS * PART_BLOCK_SIZE) 33 #define PART_ROOTFS_BLOCKS 0X2000 // 4M 34 #define PART_USERFS_ADDR (PART_ROOTFS_ADDR + PART_ROOTFS_BLOCKS * PART_BLOCK_SIZE) 35 #define PART_USERFS_BLOCKS 0x1000 // 2M 36 37 #define FIRMWARE_VENDOR_OFFSET (PART_LITEOS_ADDR + 1 * PART_BLOCK_SIZE); 38 #define FIRMWARE_WIFI_OFFSET 0x20c00 39 #define FIRMWARE_WIFI_SIZE 0x40000 40 41 /* if GRF_SOC_CON0.remap==1’b1, ICACHE access: 0X00080000 or 0x00000000 */ 42 #define SRAM0_ICACHE_ADDR 0x00080000 43 #define SRAM0_DCACHE_ADDR 0x20000000 44 #define SRAM0_SIZE 0x20000 // 128K 45 46 #define SRAM1_ICACHE_ADDR 0x000A0000 47 #define SRAM1_DCACHE_ADDR 0x20020000 48 #define SRAM1_SIZE 0x20000 // 128K 49 50 #define XIP_ADDR 0x10000000 51 #define XIP_SIZE 0x800000 // 8M 52 53 #define SRAM_CODE_ADDR SRAM0_ICACHE_ADDR 54 #define SRAM_CODE_SIZE 0x26000 // 128K 55 56 #define SRAM_DATA_ADDR (SRAM0_DCACHE_ADDR + SRAM_CODE_SIZE) 57 #define SRAM_DATA_SIZE (SRAM0_SIZE + SRAM1_SIZE - SRAM_CODE_SIZE) 58 59 #define PSRAM_ADDR 0x38000000 60 #define PSRAM_SIZE 0x00800000 61 62 #define SYS_STACK_SIZE 0x100000 63 64 #ifdef __cplusplus 65 #if __cplusplus 66 } 67 #endif /* __cplusplus */ 68 #endif /* __cplusplus */ 69 70 #endif /* _LINK_H */ 71