1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rk3568-cru.h>
14 #include "clk.h"
15
16 #define RK3568_GRF_SOC_CON1 0x504
17 #define RK3568_GRF_SOC_CON2 0x508
18 #define RK3568_GRF_SOC_STATUS0 0x580
19 #define RK3568_PMU_GRF_SOC_CON0 0x100
20
21 #define RK3568_FRAC_MAX_PRATE 1000000000
22 #define RK3568_SPDIF_FRAC_MAX_PRATE 600000000
23 #define RK3568_UART_FRAC_MAX_PRATE 600000000
24 #define RK3568_DCLK_PARENT_MAX_PRATE 600000000
25
26 enum rk3568_pmu_plls {
27 ppll,
28 hpll,
29 };
30
31 enum rk3568_plls {
32 apll,
33 dpll,
34 gpll,
35 cpll,
36 npll,
37 vpll,
38 };
39
40 static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
41 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
42 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
43 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
44 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
45 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
46 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
47 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
48 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
57 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
58 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
59 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
60 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
61 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
62 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
63 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
64 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
65 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
66 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
67 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
68 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
69 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
70 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
71 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
72 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
73 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
74 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
75 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
76 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
77 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
78 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
79 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
80 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
81 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
82 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
83 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
84 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
85 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
86 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
87 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
88 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
89 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
90 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
91 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
92 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
93 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
94 {},
95 };
96
97 #define RK3568_DIV_ATCLK_CORE_MASK 0x1f
98 #define RK3568_DIV_ATCLK_CORE_SHIFT 0
99 #define RK3568_DIV_GICCLK_CORE_MASK 0x1f
100 #define RK3568_DIV_GICCLK_CORE_SHIFT 8
101 #define RK3568_DIV_PCLK_CORE_MASK 0x1f
102 #define RK3568_DIV_PCLK_CORE_SHIFT 0
103 #define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f
104 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8
105 #define RK3568_DIV_ACLK_CORE_MASK 0x1f
106 #define RK3568_DIV_ACLK_CORE_SHIFT 8
107
108 #define RK3568_DIV_SCLK_CORE_MASK 0xf
109 #define RK3568_DIV_SCLK_CORE_SHIFT 0
110 #define RK3568_MUX_SCLK_CORE_MASK 0x3
111 #define RK3568_MUX_SCLK_CORE_SHIFT 8
112 #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1
113 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15
114 #define RK3568_MUX_CLK_CORE_APLL_MASK 0x1
115 #define RK3568_MUX_CLK_CORE_APLL_SHIFT 7
116 #define RK3568_MUX_CLK_PVTPLL_MASK 0x1
117 #define RK3568_MUX_CLK_PVTPLL_SHIFT 15
118
119 #define RK3568_CLKSEL1(_sclk_core) \
120 { \
121 .reg = RK3568_CLKSEL_CON(2), \
122 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \
123 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, RK3568_MUX_SCLK_CORE_SHIFT) | \
124 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, RK3568_DIV_SCLK_CORE_SHIFT), \
125 }
126
127 #define RK3568_CLKSEL2(_aclk_core) \
128 { \
129 .reg = RK3568_CLKSEL_CON(5), \
130 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, RK3568_DIV_ACLK_CORE_SHIFT), \
131 }
132
133 #define RK3568_CLKSEL3(_atclk_core, _gic_core) \
134 { \
135 .reg = RK3568_CLKSEL_CON(3), \
136 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, RK3568_DIV_ATCLK_CORE_SHIFT) | \
137 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, RK3568_DIV_GICCLK_CORE_SHIFT), \
138 }
139
140 #define RK3568_CLKSEL4(_pclk_core, _periph_core) \
141 { \
142 .reg = RK3568_CLKSEL_CON(4), \
143 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, RK3568_DIV_PCLK_CORE_SHIFT) | \
144 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, RK3568_DIV_PERIPHCLK_CORE_SHIFT), \
145 }
146
147 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
148 { \
149 .prate = _prate##U, \
150 .divs = { \
151 RK3568_CLKSEL1(_sclk), \
152 RK3568_CLKSEL2(_acore), \
153 RK3568_CLKSEL3(_atcore, _gicclk), \
154 RK3568_CLKSEL4(_pclk, _periph), \
155 }, \
156 }
157
158 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
159 RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
160 RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
161 RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
162 RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
163 RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
164 RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
165 RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
166 RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
167 RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
168 RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
169 RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
170 RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
171 RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
172 RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
173 RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
174 };
175
176 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
177 .core_reg[0] = RK3568_CLKSEL_CON(0),
178 .div_core_shift[0] = 0,
179 .div_core_mask[0] = 0x1f,
180 .core_reg[1] = RK3568_CLKSEL_CON(0),
181 .div_core_shift[1] = 8,
182 .div_core_mask[1] = 0x1f,
183 .core_reg[2] = RK3568_CLKSEL_CON(1),
184 .div_core_shift[2] = 0,
185 .div_core_mask[2] = 0x1f,
186 .core_reg[3] = RK3568_CLKSEL_CON(1),
187 .div_core_shift[3] = 8,
188 .div_core_mask[3] = 0x1f,
189 .num_cores = 4,
190 .mux_core_alt = 1,
191 .mux_core_main = 0,
192 .mux_core_shift = 6,
193 .mux_core_mask = 0x1,
194 };
195
196 PNAME(mux_pll_p) = {"xin24m"};
197 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "clk_rtc_32k"};
198 PNAME(clk_i2s0_8ch_tx_p) = {"clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half"};
199 PNAME(clk_i2s0_8ch_rx_p) = {"clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half"};
200 PNAME(clk_i2s1_8ch_tx_p) = {"clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half"};
201 PNAME(clk_i2s1_8ch_rx_p) = {"clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half"};
202 PNAME(clk_i2s2_2ch_p) = {"clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
203 PNAME(clk_i2s3_2ch_tx_p) = {"clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half"};
204 PNAME(clk_i2s3_2ch_rx_p) = {"clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half"};
205 PNAME(mclk_spdif_8ch_p) = {"mclk_spdif_8ch_src", "mclk_spdif_8ch_frac"};
206 PNAME(sclk_audpwm_p) = {"sclk_audpwm_src", "sclk_audpwm_frac"};
207 PNAME(sclk_uart1_p) = {"clk_uart1_src", "clk_uart1_frac", "xin24m"};
208 PNAME(sclk_uart2_p) = {"clk_uart2_src", "clk_uart2_frac", "xin24m"};
209 PNAME(sclk_uart3_p) = {"clk_uart3_src", "clk_uart3_frac", "xin24m"};
210 PNAME(sclk_uart4_p) = {"clk_uart4_src", "clk_uart4_frac", "xin24m"};
211 PNAME(sclk_uart5_p) = {"clk_uart5_src", "clk_uart5_frac", "xin24m"};
212 PNAME(sclk_uart6_p) = {"clk_uart6_src", "clk_uart6_frac", "xin24m"};
213 PNAME(sclk_uart7_p) = {"clk_uart7_src", "clk_uart7_frac", "xin24m"};
214 PNAME(sclk_uart8_p) = {"clk_uart8_src", "clk_uart8_frac", "xin24m"};
215 PNAME(sclk_uart9_p) = {"clk_uart9_src", "clk_uart9_frac", "xin24m"};
216 PNAME(sclk_uart0_p) = {"sclk_uart0_div", "sclk_uart0_frac", "xin24m"};
217 PNAME(clk_rtc32k_pmu_p) = {"clk_32k_pvtm", "xin32k", "clk_rtc32k_frac"};
218 PNAME(mpll_gpll_cpll_npll_p) = {"mpll", "gpll", "cpll", "npll"};
219 PNAME(gpll_cpll_npll_p) = {"gpll", "cpll", "npll"};
220 PNAME(npll_gpll_p) = {"npll", "gpll"};
221 PNAME(cpll_gpll_p) = {"cpll", "gpll"};
222 PNAME(gpll_cpll_p) = {"gpll", "cpll"};
223 PNAME(gpll_cpll_npll_vpll_p) = {"gpll", "cpll", "npll", "vpll"};
224 PNAME(apll_gpll_npll_p) = {"apll", "gpll", "npll"};
225 PNAME(sclk_core_pre_p) = {"sclk_core_src", "npll"};
226 PNAME(gpll150_gpll100_gpll75_xin24m_p) = {"gpll_150m", "gpll_100m", "gpll_75m", "xin24m"};
227 PNAME(clk_gpu_pre_mux_p) = {"clk_gpu_src", "gpu_pvtpll_out"};
228 PNAME(clk_npu_pre_ndft_p) = {"clk_npu_src", "clk_npu_np5"};
229 PNAME(clk_npu_p) = {"clk_npu_pre_ndft", "npu_pvtpll_out"};
230 PNAME(dpll_gpll_cpll_p) = {"dpll", "gpll", "cpll"};
231 PNAME(clk_ddr1x_p) = {"clk_ddrphy1x_src", "dpll"};
232 PNAME(gpll200_gpll150_gpll100_xin24m_p) = {"gpll_200m", "gpll_150m", "gpll_100m", "xin24m"};
233 PNAME(gpll100_gpll75_gpll50_p) = {"gpll_100m", "gpll_75m", "cpll_50m"};
234 PNAME(i2s0_mclkout_tx_p) = {"mclk_i2s0_8ch_tx", "xin_osc0_half"};
235 PNAME(i2s0_mclkout_rx_p) = {"mclk_i2s0_8ch_rx", "xin_osc0_half"};
236 PNAME(i2s1_mclkout_tx_p) = {"mclk_i2s1_8ch_tx", "xin_osc0_half"};
237 PNAME(i2s1_mclkout_rx_p) = {"mclk_i2s1_8ch_rx", "xin_osc0_half"};
238 PNAME(i2s2_mclkout_p) = {"mclk_i2s2_2ch", "xin_osc0_half"};
239 PNAME(i2s3_mclkout_tx_p) = {"mclk_i2s3_2ch_tx", "xin_osc0_half"};
240 PNAME(i2s3_mclkout_rx_p) = {"mclk_i2s3_2ch_rx", "xin_osc0_half"};
241 PNAME(mclk_pdm_p) = {"gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m"};
242 PNAME(clk_i2c_p) = {"gpll_200m", "gpll_100m", "xin24m", "cpll_100m"};
243 PNAME(gpll200_gpll150_gpll100_p) = {"gpll_200m", "gpll_150m", "gpll_100m"};
244 PNAME(gpll300_gpll200_gpll100_p) = {"gpll_300m", "gpll_200m", "gpll_100m"};
245 PNAME(clk_nandc_p) = {"gpll_200m", "gpll_150m", "cpll_100m", "xin24m"};
246 PNAME(sclk_sfc_p) = {"xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m"};
247 PNAME(gpll200_gpll150_cpll125_p) = {"gpll_200m", "gpll_150m", "cpll_125m"};
248 PNAME(cclk_emmc_p) = {"xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k"};
249 PNAME(aclk_pipe_p) = {"gpll_400m", "gpll_300m", "gpll_200m", "xin24m"};
250 PNAME(gpll200_cpll125_p) = {"gpll_200m", "cpll_125m"};
251 PNAME(gpll300_gpll200_gpll100_xin24m_p) = {"gpll_300m", "gpll_200m", "gpll_100m", "xin24m"};
252 PNAME(clk_sdmmc_p) = {"xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k"};
253 PNAME(cpll125_cpll50_cpll25_xin24m_p) = {"cpll_125m", "cpll_50m", "cpll_25m", "xin24m"};
254 PNAME(clk_gmac_ptp_p) = {"cpll_62p5", "gpll_100m", "cpll_50m", "xin24m"};
255 PNAME(cpll333_gpll300_gpll200_p) = {"cpll_333m", "gpll_300m", "gpll_200m"};
256 PNAME(cpll_gpll_hpll_p) = {"cpll", "gpll", "hpll"};
257 PNAME(gpll_usb480m_xin24m_p) = {"gpll", "usb480m", "xin24m", "xin24m"};
258 PNAME(gpll300_cpll250_gpll100_xin24m_p) = {"gpll_300m", "cpll_250m", "gpll_100m", "xin24m"};
259 PNAME(cpll_gpll_hpll_vpll_p) = {"cpll", "gpll", "hpll", "vpll"};
260 PNAME(hpll_vpll_gpll_cpll_p) = {"hpll", "vpll", "gpll", "cpll"};
261 PNAME(gpll400_cpll333_gpll200_p) = {"gpll_400m", "cpll_333m", "gpll_200m"};
262 PNAME(gpll100_gpll75_cpll50_xin24m_p) = {"gpll_100m", "gpll_75m", "cpll_50m", "xin24m"};
263 PNAME(xin24m_gpll100_cpll100_p) = {"xin24m", "gpll_100m", "cpll_100m"};
264 PNAME(gpll_cpll_usb480m_p) = {"gpll", "cpll", "usb480m"};
265 PNAME(gpll100_xin24m_cpll100_p) = {"gpll_100m", "xin24m", "cpll_100m"};
266 PNAME(gpll200_xin24m_cpll100_p) = {"gpll_200m", "xin24m", "cpll_100m"};
267 PNAME(xin24m_32k_p) = {"xin24m", "clk_rtc_32k"};
268 PNAME(cpll500_gpll400_gpll300_xin24m_p) = {"cpll_500m", "gpll_400m", "gpll_300m", "xin24m"};
269 PNAME(gpll400_gpll300_gpll200_xin24m_p) = {"gpll_400m", "gpll_300m", "gpll_200m", "xin24m"};
270 PNAME(xin24m_cpll100_p) = {"xin24m", "cpll_100m"};
271 PNAME(ppll_usb480m_cpll_gpll_p) = {"ppll", "usb480m", "cpll", "gpll"};
272 PNAME(clk_usbphy0_ref_p) = {"clk_ref24m", "xin_osc0_usbphy0_g"};
273 PNAME(clk_usbphy1_ref_p) = {"clk_ref24m", "xin_osc0_usbphy1_g"};
274 PNAME(clk_mipidsiphy0_ref_p) = {"clk_ref24m", "xin_osc0_mipidsiphy0_g"};
275 PNAME(clk_mipidsiphy1_ref_p) = {"clk_ref24m", "xin_osc0_mipidsiphy1_g"};
276 PNAME(clk_wifi_p) = {"clk_wifi_osc0", "clk_wifi_div"};
277 PNAME(clk_pciephy0_ref_p) = {"clk_pciephy0_osc0", "clk_pciephy0_div"};
278 PNAME(clk_pciephy1_ref_p) = {"clk_pciephy1_osc0", "clk_pciephy1_div"};
279 PNAME(clk_pciephy2_ref_p) = {"clk_pciephy2_osc0", "clk_pciephy2_div"};
280 PNAME(mux_gmac1_p) = {"clk_mac1_2top", "gmac1_clkin"};
281 PNAME(mux_gmac1_rgmii_speed_p) = {"clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5"};
282 PNAME(mux_gmac1_rmii_speed_p) = {"clk_gmac1_rx_div20", "clk_gmac1_rx_div2"};
283 PNAME(mux_gmac1_rx_tx_p) = {"clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii"};
284 PNAME(clk_hdmi_ref_p) = {"hpll", "hpll_ph0"};
285 PNAME(clk_pdpmu_p) = {"ppll", "gpll"};
286 PNAME(clk_mac_2top_p) = {"cpll_125m", "cpll_50m", "cpll_25m", "ppll"};
287 PNAME(clk_pwm0_p) = {"xin24m", "clk_pdpmu"};
288 PNAME(aclk_rkvdec_pre_p) = {"gpll", "cpll"};
289 PNAME(clk_rkvdec_core_p) = {"gpll", "cpll", "dummy_npll", "dummy_vpll"};
290 PNAME(clk_32k_ioe_p) = {"clk_rtc_32k", "xin32k"};
291 PNAME(i2s1_mclkout_p) = {"i2s1_mclkout_rx", "i2s1_mclkout_tx"};
292 PNAME(i2s3_mclkout_p) = {"i2s3_mclkout_rx", "i2s3_mclkout_tx"};
293 PNAME(i2s1_mclk_rx_ioe_p) = {"i2s1_mclkin_rx", "i2s1_mclkout_rx"};
294 PNAME(i2s1_mclk_tx_ioe_p) = {"i2s1_mclkin_tx", "i2s1_mclkout_tx"};
295 PNAME(i2s2_mclk_ioe_p) = {"i2s2_mclkin", "i2s2_mclkout"};
296 PNAME(i2s3_mclk_ioe_p) = {"i2s3_mclkin", "i2s3_mclkout"};
297
298 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
299 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, 0, RK3568_PMU_PLL_CON(0), RK3568_PMU_MODE_CON0, 0, 4, 0,
300 rk3568_pll_rates),
301 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 0, RK3568_PMU_PLL_CON(16), RK3568_PMU_MODE_CON0, 2, 7, 0,
302 rk3568_pll_rates),
303 };
304
305 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
306 [apll] =
307 PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3568_PLL_CON(0), RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
308 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3568_PLL_CON(8), RK3568_MODE_CON0, 2, 1, 0, NULL),
309 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RK3568_PLL_CON(24), RK3568_MODE_CON0, 4, 2, 0,
310 rk3568_pll_rates),
311 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, RK3568_PLL_CON(16), RK3568_MODE_CON0, 6, 3, 0,
312 rk3568_pll_rates),
313 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, CLK_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0, 10, 5,
314 0, rk3568_pll_rates),
315 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 0, RK3568_PLL_CON(40), RK3568_MODE_CON0, 12, 6, 0,
316 rk3568_pll_rates),
317 };
318
319 #define MFLAGS CLK_MUX_HIWORD_MASK
320 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
321 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
322
323 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = MUX(
324 CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
325
326 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = MUX(
327 CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
328
329 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = MUX(
330 CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
331
332 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = MUX(
333 CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
334
335 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
336 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
337
338 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = MUX(
339 CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
340
341 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = MUX(
342 CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
343
344 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
345 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
346
347 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
348 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
349
350 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
351 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
352
353 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
354 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
355
356 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
357 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
358
359 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
360 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
361
362 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
363 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
364
365 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
366 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
367
368 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
369 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
370
371 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
372 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
373
374 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
375 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
376
377 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
378 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
379
380 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
381 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
382 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
383
384 static struct rockchip_clk_branch rk3568_clk_npu_np5 __initdata =
385 COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
386 RK3568_CLKGATE_CON(3), 1, GFLAGS);
387
388 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
389 /*
390 * Clock-Architecture Diagram 1
391 */
392 /* SRC_CLK */
393 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
394 RK3568_CLKGATE_CON(35), 0, GFLAGS),
395 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
396 RK3568_CLKGATE_CON(35), 1, GFLAGS),
397 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
398 RK3568_CLKGATE_CON(35), 2, GFLAGS),
399 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
400 RK3568_CLKGATE_CON(35), 3, GFLAGS),
401 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
402 RK3568_CLKGATE_CON(35), 4, GFLAGS),
403 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
404 RK3568_CLKGATE_CON(35), 5, GFLAGS),
405 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
406 RK3568_CLKGATE_CON(35), 6, GFLAGS),
407 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
408 RK3568_CLKGATE_CON(35), 7, GFLAGS),
409 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
410 RK3568_CLKGATE_CON(35), 8, GFLAGS),
411 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
412 RK3568_CLKGATE_CON(35), 9, GFLAGS),
413 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
414 RK3568_CLKGATE_CON(35), 10, GFLAGS),
415 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
416 RK3568_CLKGATE_CON(35), 11, GFLAGS),
417 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
418 RK3568_CLKGATE_CON(35), 12, GFLAGS),
419 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
420 RK3568_CLKGATE_CON(35), 13, GFLAGS),
421 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
422 RK3568_CLKGATE_CON(35), 14, GFLAGS),
423 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
424 RK3568_CLKGATE_CON(35), 15, GFLAGS),
425 FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
426 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
427 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK3568_MODE_CON0, 14, 2, MFLAGS),
428
429 /* PD_CORE */
430 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4,
431 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 5, GFLAGS),
432 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
433 RK3568_CLKGATE_CON(0), 7, GFLAGS),
434
435 COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(3), 0, 5,
436 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 8, GFLAGS),
437 COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(3), 8, 5,
438 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 9, GFLAGS),
439 COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(4), 0, 5,
440 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 10, GFLAGS),
441 COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(4), 8, 5,
442 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 11, GFLAGS),
443 COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(5), 0, 4,
444 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 14, GFLAGS),
445 COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(5), 4, 4,
446 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 15, GFLAGS),
447 COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(5), 8, 5,
448 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(1), 0, GFLAGS),
449
450 COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
451 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, RK3568_CLKGATE_CON(1), 2, GFLAGS),
452
453 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, RK3568_CLKGATE_CON(1), 10, GFLAGS),
454 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, RK3568_CLKGATE_CON(1), 11, GFLAGS),
455 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(1), 12, GFLAGS),
456 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, RK3568_CLKGATE_CON(1), 9, GFLAGS),
457
458 /* PD_GPU */
459 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(6), 6, 2,
460 MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(2), 0, GFLAGS),
461 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(6), 11, 1,
462 MFLAGS | CLK_MUX_READ_ONLY),
463 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
464 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
465 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, RK3568_CLKGATE_CON(2), 3, GFLAGS),
466
467 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, RK3568_CLKGATE_CON(2), 6, GFLAGS),
468 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, RK3568_CLKGATE_CON(2), 7, GFLAGS),
469 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, RK3568_CLKGATE_CON(2), 8, GFLAGS),
470 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(2), 9, GFLAGS),
471
472 /* PD_NPU */
473 COMPOSITE_BROTHER(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
474 RK3568_CLKGATE_CON(3), 0, GFLAGS, &rk3568_clk_npu_np5),
475 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
476 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
477 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
478 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
479 RK3568_CLKGATE_CON(3), 2, GFLAGS),
480 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
481 RK3568_CLKGATE_CON(3), 3, GFLAGS),
482 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, RK3568_CLKGATE_CON(3), 4, GFLAGS),
483 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, RK3568_CLKGATE_CON(3), 7, GFLAGS),
484 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, RK3568_CLKGATE_CON(3), 8, GFLAGS),
485
486 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, RK3568_CLKGATE_CON(3), 9, GFLAGS),
487 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, RK3568_CLKGATE_CON(3), 10, GFLAGS),
488 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, RK3568_CLKGATE_CON(3), 11, GFLAGS),
489 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(3), 12, GFLAGS),
490
491 /* PD_DDR */
492 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(9), 6, 2,
493 MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(4), 0, GFLAGS),
494 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
495
496 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
497 RK3568_CLKGATE_CON(4), 2, GFLAGS),
498 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(4), 15, GFLAGS),
499
500 /* PD_GIC_AUDIO */
501 COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
502 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, RK3568_CLKGATE_CON(5), 0, GFLAGS),
503 COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
504 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, RK3568_CLKGATE_CON(5), 1, GFLAGS),
505 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 8, GFLAGS),
506 COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, RK3568_CLKSEL_CON(10), 12, 2,
507 MFLAGS, RK3568_CLKGATE_CON(5), 9, GFLAGS),
508 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(5), 4, GFLAGS),
509 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(5), 7, GFLAGS),
510 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 10, GFLAGS),
511 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 11, GFLAGS),
512 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 12, GFLAGS),
513 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 13, GFLAGS),
514
515 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0,
516 7, DFLAGS, RK3568_CLKGATE_CON(6), 0, GFLAGS),
517 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
518 RK3568_CLKSEL_CON(12), 0, RK3568_CLKGATE_CON(6), 1, GFLAGS, &rk3568_i2s0_8ch_tx_fracmux,
519 RK3568_FRAC_MAX_PRATE),
520 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, RK3568_CLKGATE_CON(6), 2, GFLAGS),
521 COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(11),
522 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 3, GFLAGS),
523
524 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0,
525 7, DFLAGS, RK3568_CLKGATE_CON(6), 4, GFLAGS),
526 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
527 RK3568_CLKSEL_CON(14), 0, RK3568_CLKGATE_CON(6), 5, GFLAGS, &rk3568_i2s0_8ch_rx_fracmux,
528 RK3568_FRAC_MAX_PRATE),
529 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, RK3568_CLKGATE_CON(6), 6, GFLAGS),
530 COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(13),
531 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 7, GFLAGS),
532
533 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0,
534 7, DFLAGS, RK3568_CLKGATE_CON(6), 8, GFLAGS),
535 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
536 RK3568_CLKSEL_CON(16), 0, RK3568_CLKGATE_CON(6), 9, GFLAGS, &rk3568_i2s1_8ch_tx_fracmux,
537 RK3568_FRAC_MAX_PRATE),
538 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, RK3568_CLKGATE_CON(6), 10, GFLAGS),
539 COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(15),
540 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 11, GFLAGS),
541
542 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0,
543 7, DFLAGS, RK3568_CLKGATE_CON(6), 12, GFLAGS),
544 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
545 RK3568_CLKSEL_CON(18), 0, RK3568_CLKGATE_CON(6), 13, GFLAGS, &rk3568_i2s1_8ch_rx_fracmux,
546 RK3568_FRAC_MAX_PRATE),
547 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, RK3568_CLKGATE_CON(6), 14, GFLAGS),
548 COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(17),
549 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 15, GFLAGS),
550
551 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7,
552 DFLAGS, RK3568_CLKGATE_CON(7), 0, GFLAGS),
553 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
554 RK3568_CLKSEL_CON(20), 0, RK3568_CLKGATE_CON(7), 1, GFLAGS, &rk3568_i2s2_2ch_fracmux,
555 RK3568_FRAC_MAX_PRATE),
556 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, RK3568_CLKGATE_CON(7), 2, GFLAGS),
557 COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(19), 15, 1,
558 MFLAGS, RK3568_CLKGATE_CON(7), 3, GFLAGS),
559
560 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0,
561 7, DFLAGS, RK3568_CLKGATE_CON(7), 4, GFLAGS),
562 COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
563 RK3568_CLKSEL_CON(22), 0, RK3568_CLKGATE_CON(7), 5, GFLAGS, &rk3568_i2s3_2ch_tx_fracmux,
564 RK3568_FRAC_MAX_PRATE),
565 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, RK3568_CLKGATE_CON(7), 6, GFLAGS),
566 COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(21),
567 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 7, GFLAGS),
568
569 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0,
570 7, DFLAGS, RK3568_CLKGATE_CON(7), 8, GFLAGS),
571 COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
572 RK3568_CLKSEL_CON(84), 0, RK3568_CLKGATE_CON(7), 9, GFLAGS, &rk3568_i2s3_2ch_rx_fracmux,
573 RK3568_FRAC_MAX_PRATE),
574 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, RK3568_CLKGATE_CON(7), 10, GFLAGS),
575 COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(83),
576 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 11, GFLAGS),
577
578 MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
579 RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
580 MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
581 RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
582 MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p, 0, RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
583 MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p, 0, RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
584 MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p, 0, RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
585 MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p, 0, RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
586
587 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 14, GFLAGS),
588 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, RK3568_CLKGATE_CON(5), 15,
589 GFLAGS),
590 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(7), 12, GFLAGS),
591 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(7), 13, GFLAGS),
592
593 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7,
594 DFLAGS, RK3568_CLKGATE_CON(7), 14, GFLAGS),
595 COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
596 RK3568_CLKSEL_CON(24), 0, RK3568_CLKGATE_CON(7), 15, GFLAGS, &rk3568_spdif_8ch_fracmux,
597 RK3568_SPDIF_FRAC_MAX_PRATE),
598
599 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(8), 0, GFLAGS),
600 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
601 RK3568_CLKGATE_CON(8), 1, GFLAGS),
602 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
603 RK3568_CLKSEL_CON(26), 0, RK3568_CLKGATE_CON(8), 2, GFLAGS, &rk3568_audpwm_fracmux,
604 RK3568_FRAC_MAX_PRATE),
605
606 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(8), 3, GFLAGS),
607 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
608 RK3568_CLKGATE_CON(8), 4, GFLAGS),
609 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, RK3568_CLKGATE_CON(8), 5, GFLAGS),
610 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, RK3568_CLKGATE_CON(8), 6, GFLAGS),
611
612 /* PD_SECURE_FLASH */
613 COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, CLK_IS_CRITICAL,
614 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, RK3568_CLKGATE_CON(8), 7, GFLAGS),
615 COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
616 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, RK3568_CLKGATE_CON(8), 8, GFLAGS),
617 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, RK3568_CLKGATE_CON(8), 11, GFLAGS),
618 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(8), 12, GFLAGS),
619 COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, RK3568_CLKSEL_CON(27), 4, 2,
620 MFLAGS, RK3568_CLKGATE_CON(8), 13, GFLAGS),
621 COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, RK3568_CLKSEL_CON(27), 6, 2,
622 MFLAGS, RK3568_CLKGATE_CON(8), 14, GFLAGS),
623 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(8), 15, GFLAGS),
624 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(9), 10, GFLAGS),
625 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(9), 11, GFLAGS),
626 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(26), 9, GFLAGS),
627 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, RK3568_CLKGATE_CON(26), 10, GFLAGS),
628 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, RK3568_CLKGATE_CON(26), 11, GFLAGS),
629 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 0, GFLAGS),
630 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
631 RK3568_CLKGATE_CON(9), 1, GFLAGS),
632 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 2, GFLAGS),
633 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 3, GFLAGS),
634 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, RK3568_CLKGATE_CON(9), 4,
635 GFLAGS),
636 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 5, GFLAGS),
637 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 6, GFLAGS),
638 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
639 RK3568_CLKGATE_CON(9), 7, GFLAGS),
640 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, RK3568_CLKGATE_CON(9),
641 8, GFLAGS),
642 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, RK3568_CLKGATE_CON(9), 9, GFLAGS),
643 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
644 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
645
646 /* PD_PIPE */
647 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, RK3568_CLKGATE_CON(10),
648 0, GFLAGS),
649 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, RK3568_CLKGATE_CON(10),
650 1, GFLAGS),
651 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 0, GFLAGS),
652 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 1, GFLAGS),
653 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 2, GFLAGS),
654 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, RK3568_CLKGATE_CON(12), 3, GFLAGS),
655 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, RK3568_CLKGATE_CON(12), 4, GFLAGS),
656 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 8, GFLAGS),
657 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 9, GFLAGS),
658 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 10, GFLAGS),
659 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, RK3568_CLKGATE_CON(12), 11, GFLAGS),
660 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, RK3568_CLKGATE_CON(12), 12, GFLAGS),
661 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, RK3568_CLKGATE_CON(13), 0, GFLAGS),
662 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, RK3568_CLKGATE_CON(13), 1, GFLAGS),
663 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, RK3568_CLKGATE_CON(13), 2, GFLAGS),
664 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, RK3568_CLKGATE_CON(13), 3, GFLAGS),
665 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, RK3568_CLKGATE_CON(13), 4, GFLAGS),
666 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, RK3568_CLKGATE_CON(11), 0, GFLAGS),
667 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, RK3568_CLKGATE_CON(11), 1, GFLAGS),
668 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, RK3568_CLKGATE_CON(11), 2, GFLAGS),
669 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, RK3568_CLKGATE_CON(11), 4, GFLAGS),
670 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, RK3568_CLKGATE_CON(11), 5, GFLAGS),
671 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, RK3568_CLKGATE_CON(11), 6, GFLAGS),
672 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, RK3568_CLKGATE_CON(11), 8, GFLAGS),
673 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, RK3568_CLKGATE_CON(11), 9, GFLAGS),
674 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, RK3568_CLKGATE_CON(11), 10, GFLAGS),
675 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, RK3568_CLKGATE_CON(10), 8, GFLAGS),
676 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, RK3568_CLKGATE_CON(10), 9, GFLAGS),
677 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
678 RK3568_CLKGATE_CON(10), 10, GFLAGS),
679 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, RK3568_CLKGATE_CON(10), 12, GFLAGS),
680 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, RK3568_CLKGATE_CON(10), 13, GFLAGS),
681 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
682 RK3568_CLKGATE_CON(10), 14, GFLAGS),
683 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
684 RK3568_CLKGATE_CON(10), 4, GFLAGS),
685 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, RK3568_CLKGATE_CON(13), 6, GFLAGS),
686
687 /* PD_PHP */
688 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
689 RK3568_CLKGATE_CON(14), 8, GFLAGS),
690 COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(30), 2, 2,
691 MFLAGS, RK3568_CLKGATE_CON(14), 9, GFLAGS),
692 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
693 RK3568_CLKGATE_CON(14), 10, GFLAGS),
694 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, RK3568_CLKGATE_CON(15), 0, GFLAGS),
695 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
696 RK3568_CLKGATE_CON(15), 1, GFLAGS),
697 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
698 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
699
700 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, RK3568_CLKGATE_CON(15), 2, GFLAGS),
701 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
702 RK3568_CLKGATE_CON(15), 3, GFLAGS),
703 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
704 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
705
706 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
707 RK3568_CLKGATE_CON(15), 7, GFLAGS),
708 COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, RK3568_CLKSEL_CON(31), 14, 2,
709 MFLAGS, RK3568_CLKGATE_CON(15), 8, GFLAGS),
710 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, RK3568_CLKGATE_CON(15), 12, GFLAGS),
711
712 /* PD_USB */
713 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
714 RK3568_CLKGATE_CON(16), 0, GFLAGS),
715 COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(32), 2, 2,
716 MFLAGS, RK3568_CLKGATE_CON(16), 1, GFLAGS),
717 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, RK3568_CLKGATE_CON(16), 2,
718 GFLAGS),
719 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 12, GFLAGS),
720 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 13, GFLAGS),
721 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 14, GFLAGS),
722 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 15, GFLAGS),
723 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, RK3568_CLKGATE_CON(17), 0, GFLAGS),
724 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
725 RK3568_CLKGATE_CON(17), 1, GFLAGS),
726 MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
727 MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
728
729 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, RK3568_CLKGATE_CON(17), 3, GFLAGS),
730 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, RK3568_CLKGATE_CON(17), 4, GFLAGS),
731 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
732 RK3568_CLKGATE_CON(17), 5, GFLAGS),
733 COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, RK3568_CLKSEL_CON(33), 14, 2,
734 MFLAGS, RK3568_CLKGATE_CON(17), 6, GFLAGS),
735 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, RK3568_CLKGATE_CON(17), 10, GFLAGS),
736 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
737 RK3568_CLKGATE_CON(17), 2, GFLAGS),
738 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(33), 2,
739 1, MFLAGS),
740 FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
741 FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
742 FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
743 FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
744 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, RK3568_CLKSEL_CON(33), 4, 2,
745 MFLAGS),
746 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
747 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(33), 0, 2,
748 MFLAGS),
749
750 /* PD_PERI */
751 COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IS_CRITICAL,
752 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, RK3568_CLKGATE_CON(14), 0, GFLAGS),
753 COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
754 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, RK3568_CLKGATE_CON(14), 1, GFLAGS),
755
756 /* PD_VI */
757 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
758 RK3568_CLKGATE_CON(18), 0, GFLAGS),
759 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, RK3568_CLKGATE_CON(18), 1,
760 GFLAGS),
761 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, RK3568_CLKGATE_CON(18), 2,
762 GFLAGS),
763 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, RK3568_CLKGATE_CON(18), 9, GFLAGS),
764 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, RK3568_CLKGATE_CON(18), 10, GFLAGS),
765 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
766 RK3568_CLKGATE_CON(18), 11, GFLAGS),
767 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, RK3568_CLKGATE_CON(18), 13, GFLAGS),
768 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, RK3568_CLKGATE_CON(19), 0, GFLAGS),
769 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, RK3568_CLKGATE_CON(19), 1, GFLAGS),
770 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
771 RK3568_CLKGATE_CON(19), 2, GFLAGS),
772 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, RK3568_CLKGATE_CON(19), 4, GFLAGS),
773 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
774 RK3568_CLKGATE_CON(19), 8, GFLAGS),
775 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
776 RK3568_CLKGATE_CON(19), 9, GFLAGS),
777 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6,
778 DFLAGS, RK3568_CLKGATE_CON(19), 10, GFLAGS),
779
780 /* PD_VO */
781 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
782 RK3568_CLKGATE_CON(20), 0, GFLAGS),
783 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, RK3568_CLKGATE_CON(20), 1,
784 GFLAGS),
785 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, RK3568_CLKGATE_CON(20), 2,
786 GFLAGS),
787 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
788 RK3568_CLKGATE_CON(20), 6, GFLAGS),
789 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3568_CLKGATE_CON(20), 8, GFLAGS),
790 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, RK3568_CLKGATE_CON(20), 9, GFLAGS),
791 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
792 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS),
793 COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
794 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 11, GFLAGS,
795 RK3568_DCLK_PARENT_MAX_PRATE),
796 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
797 RK3568_CLKGATE_CON(20), 12, GFLAGS),
798 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, RK3568_CLKGATE_CON(20), 13, GFLAGS),
799 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, RK3568_CLKGATE_CON(21), 0, GFLAGS),
800 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, RK3568_CLKGATE_CON(21), 1, GFLAGS),
801 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 2, GFLAGS),
802 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 3, GFLAGS),
803 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, RK3568_CLKGATE_CON(21), 4, GFLAGS),
804 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, RK3568_CLKGATE_CON(21), 5, GFLAGS),
805 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 6, GFLAGS),
806 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 7, GFLAGS),
807 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 8, GFLAGS),
808 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
809 RK3568_CLKGATE_CON(21), 9, GFLAGS),
810
811 /* PD_VPU */
812 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
813 RK3568_CLKGATE_CON(22), 0, GFLAGS),
814 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
815 RK3568_CLKGATE_CON(22), 1, GFLAGS),
816 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK3568_CLKGATE_CON(22), 4, GFLAGS),
817 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK3568_CLKGATE_CON(22), 5, GFLAGS),
818
819 /* PD_RGA */
820 COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(43), 0, 2,
821 MFLAGS, RK3568_CLKGATE_CON(23), 0, GFLAGS),
822 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
823 RK3568_CLKGATE_CON(23), 1, GFLAGS),
824 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
825 RK3568_CLKGATE_CON(22), 12, GFLAGS),
826 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 4, GFLAGS),
827 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 5, GFLAGS),
828 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
829 RK3568_CLKGATE_CON(23), 6, GFLAGS),
830 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 7, GFLAGS),
831 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 8, GFLAGS),
832 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
833 RK3568_CLKGATE_CON(23), 9, GFLAGS),
834 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
835 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
836 RK3568_CLKGATE_CON(23), 11, GFLAGS),
837 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 12, GFLAGS),
838 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 13, GFLAGS),
839 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 14, GFLAGS),
840 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 15, GFLAGS),
841 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, RK3568_CLKGATE_CON(22), 14, GFLAGS),
842 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(22), 15, GFLAGS),
843
844 /* PD_RKVENC */
845 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5,
846 DFLAGS, RK3568_CLKGATE_CON(24), 0, GFLAGS),
847 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
848 RK3568_CLKGATE_CON(24), 1, GFLAGS),
849 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, RK3568_CLKGATE_CON(24), 6, GFLAGS),
850 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, RK3568_CLKGATE_CON(24), 7, GFLAGS),
851 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5,
852 DFLAGS, RK3568_CLKGATE_CON(24), 8, GFLAGS),
853 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(47), 7,
854 1, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 0, GFLAGS),
855 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
856 RK3568_CLKGATE_CON(25), 1, GFLAGS),
857 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK3568_CLKGATE_CON(25), 4, GFLAGS),
858 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK3568_CLKGATE_CON(25), 5, GFLAGS),
859 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5,
860 DFLAGS, RK3568_CLKGATE_CON(25), 6, GFLAGS),
861 COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(49),
862 14, 2, MFLAGS, 8, 5, DFLAGS, RK3568_CLKGATE_CON(25), 7, GFLAGS),
863 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(49), 6, 2, MFLAGS,
864 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 8, GFLAGS),
865
866 /* PD_BUS */
867 COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(50), 0,
868 2, MFLAGS, RK3568_CLKGATE_CON(26), 0, GFLAGS),
869 COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(50), 4, 2,
870 MFLAGS, RK3568_CLKGATE_CON(26), 1, GFLAGS),
871 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3568_CLKGATE_CON(26), 4, GFLAGS),
872 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3,
873 DFLAGS, RK3568_CLKGATE_CON(26), 5, GFLAGS),
874 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
875 RK3568_CLKGATE_CON(26), 6, GFLAGS),
876 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3568_CLKGATE_CON(26), 7, GFLAGS),
877 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, RK3568_CLKGATE_CON(26), 8, GFLAGS),
878 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(26), 12, GFLAGS),
879 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, RK3568_CLKGATE_CON(26), 13, GFLAGS),
880 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, RK3568_CLKGATE_CON(26), 14, GFLAGS),
881 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(32), 13, GFLAGS),
882 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(32), 14, GFLAGS),
883 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 15, GFLAGS),
884
885 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 12, GFLAGS),
886 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
887 RK3568_CLKGATE_CON(27), 13, GFLAGS),
888 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(53),
889 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(27), 14, GFLAGS, &rk3568_uart1_fracmux,
890 RK3568_UART_FRAC_MAX_PRATE),
891 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, RK3568_CLKGATE_CON(27), 15, GFLAGS),
892
893 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 0, GFLAGS),
894 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
895 RK3568_CLKGATE_CON(28), 1, GFLAGS),
896 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(55),
897 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 2, GFLAGS, &rk3568_uart2_fracmux,
898 RK3568_UART_FRAC_MAX_PRATE),
899 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, RK3568_CLKGATE_CON(28), 3, GFLAGS),
900
901 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 4, GFLAGS),
902 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
903 RK3568_CLKGATE_CON(28), 5, GFLAGS),
904 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(57),
905 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 6, GFLAGS, &rk3568_uart3_fracmux,
906 RK3568_UART_FRAC_MAX_PRATE),
907 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, RK3568_CLKGATE_CON(28), 7, GFLAGS),
908
909 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 8, GFLAGS),
910 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
911 RK3568_CLKGATE_CON(28), 9, GFLAGS),
912 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(59),
913 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 10, GFLAGS, &rk3568_uart4_fracmux,
914 RK3568_UART_FRAC_MAX_PRATE),
915 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, RK3568_CLKGATE_CON(28), 11, GFLAGS),
916
917 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 12, GFLAGS),
918 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
919 RK3568_CLKGATE_CON(28), 13, GFLAGS),
920 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(61),
921 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 14, GFLAGS, &rk3568_uart5_fracmux,
922 RK3568_UART_FRAC_MAX_PRATE),
923 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, RK3568_CLKGATE_CON(28), 15, GFLAGS),
924
925 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 0, GFLAGS),
926 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
927 RK3568_CLKGATE_CON(29), 1, GFLAGS),
928 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(63),
929 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 2, GFLAGS, &rk3568_uart6_fracmux,
930 RK3568_UART_FRAC_MAX_PRATE),
931 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, RK3568_CLKGATE_CON(29), 3, GFLAGS),
932
933 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 4, GFLAGS),
934 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
935 RK3568_CLKGATE_CON(29), 5, GFLAGS),
936 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(65),
937 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 6, GFLAGS, &rk3568_uart7_fracmux,
938 RK3568_UART_FRAC_MAX_PRATE),
939 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, RK3568_CLKGATE_CON(29), 7, GFLAGS),
940
941 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 8, GFLAGS),
942 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
943 RK3568_CLKGATE_CON(29), 9, GFLAGS),
944 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(67),
945 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 10, GFLAGS, &rk3568_uart8_fracmux,
946 RK3568_UART_FRAC_MAX_PRATE),
947 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, RK3568_CLKGATE_CON(29), 11, GFLAGS),
948
949 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 12, GFLAGS),
950 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
951 RK3568_CLKGATE_CON(29), 13, GFLAGS),
952 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(69),
953 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 14, GFLAGS, &rk3568_uart9_fracmux,
954 RK3568_UART_FRAC_MAX_PRATE),
955 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, RK3568_CLKGATE_CON(29), 15, GFLAGS),
956
957 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 5, GFLAGS),
958 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
959 RK3568_CLKGATE_CON(27), 6, GFLAGS),
960 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 7, GFLAGS),
961 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
962 RK3568_CLKGATE_CON(27), 8, GFLAGS),
963 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 9, GFLAGS),
964 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
965 RK3568_CLKGATE_CON(27), 10, GFLAGS),
966 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, RK3568_CLKGATE_CON(32), 10,
967 GFLAGS),
968 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 0, GFLAGS),
969 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 1, GFLAGS),
970 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 2, GFLAGS),
971 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 3, GFLAGS),
972 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 4, GFLAGS),
973 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 5, GFLAGS),
974 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 6, GFLAGS),
975 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 7, GFLAGS),
976 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 8, GFLAGS),
977 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 9, GFLAGS),
978 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 10, GFLAGS),
979 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
980 RK3568_CLKGATE_CON(30), 11, GFLAGS),
981 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 12, GFLAGS),
982 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
983 RK3568_CLKGATE_CON(30), 13, GFLAGS),
984 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 14, GFLAGS),
985 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
986 RK3568_CLKGATE_CON(30), 15, GFLAGS),
987 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 0, GFLAGS),
988 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 6, 1, MFLAGS,
989 RK3568_CLKGATE_CON(31), 1, GFLAGS),
990 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
991 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
992 RK3568_CLKGATE_CON(31), 11, GFLAGS),
993 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, RK3568_CLKGATE_CON(31), 12, GFLAGS),
994 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 13, GFLAGS),
995 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
996 RK3568_CLKGATE_CON(31), 14, GFLAGS),
997 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, RK3568_CLKGATE_CON(31), 15, GFLAGS),
998 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 0, GFLAGS),
999 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1000 RK3568_CLKGATE_CON(32), 1, GFLAGS),
1001 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, RK3568_CLKGATE_CON(32), 2, GFLAGS),
1002 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
1003 RK3568_CLKGATE_CON(32), 11, GFLAGS),
1004 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 2, GFLAGS),
1005 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 3, GFLAGS),
1006 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 4, GFLAGS),
1007 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 5, GFLAGS),
1008 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 6, GFLAGS),
1009 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 7, GFLAGS),
1010 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 8, GFLAGS),
1011 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 9, GFLAGS),
1012 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 3, GFLAGS),
1013 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, RK3568_CLKGATE_CON(32), 4, GFLAGS),
1014 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, RK3568_CLKGATE_CON(32), 5, GFLAGS),
1015 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, RK3568_CLKGATE_CON(32), 6, GFLAGS),
1016 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, RK3568_CLKGATE_CON(32), 7, GFLAGS),
1017 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, RK3568_CLKGATE_CON(32), 8, GFLAGS),
1018 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, RK3568_CLKGATE_CON(32), 9, GFLAGS),
1019
1020 /* PD_TOP */
1021 COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, CLK_IS_CRITICAL,
1022 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, RK3568_CLKGATE_CON(33), 0, GFLAGS),
1023 COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, CLK_IS_CRITICAL,
1024 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, RK3568_CLKGATE_CON(33), 1, GFLAGS),
1025 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(73), 8, 2,
1026 MFLAGS, RK3568_CLKGATE_CON(33), 2, GFLAGS),
1027 COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(73), 12, 2,
1028 MFLAGS, RK3568_CLKGATE_CON(33), 3, GFLAGS),
1029 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, RK3568_CLKGATE_CON(33), 8, GFLAGS),
1030 COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(73), 15, 1,
1031 MFLAGS, RK3568_CLKGATE_CON(33), 9, GFLAGS),
1032 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, RK3568_CLKGATE_CON(33), 13, GFLAGS),
1033 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, RK3568_CLKGATE_CON(33), 14, GFLAGS),
1034 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, RK3568_CLKGATE_CON(33), 15, GFLAGS),
1035 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, RK3568_CLKGATE_CON(34), 4, GFLAGS),
1036 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, RK3568_CLKGATE_CON(34), 5, GFLAGS),
1037 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, RK3568_CLKGATE_CON(34), 6, GFLAGS),
1038 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, RK3568_CLKGATE_CON(34), 11, GFLAGS),
1039 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, RK3568_CLKGATE_CON(34), 12, GFLAGS),
1040 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, RK3568_CLKGATE_CON(34), 13, GFLAGS),
1041 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, RK3568_CLKGATE_CON(34), 14, GFLAGS),
1042 };
1043
1044 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
1045 /* PD_PMU */
1046 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1047 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
1048 FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
1049
1050 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1051 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", CLK_IS_CRITICAL, RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
1052 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1053 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IS_CRITICAL, RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1054 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL, RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
1055 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
1056 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1057 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
1058 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
1059
1060 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, RK3568_PMU_CLKSEL_CON(1), 0,
1061 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, &rk3568_rtc32k_pmu_fracmux, 0),
1062
1063 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1064 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
1065
1066 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0,
1067 7, DFLAGS, RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1068 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
1069 RK3568_PMU_CLKSEL_CON(5), CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1070 &rk3568_uart0_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1071 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
1072
1073 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
1074 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
1075 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
1076 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
1077 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1078 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
1079 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
1080 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
1081 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
1082 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
1083 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
1084 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
1085 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
1086 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1087 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
1088 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1089 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
1090 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1091 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
1092 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1093 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
1094 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
1095 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
1096 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1097 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
1098 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
1099 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
1100 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 3, 1,
1101 MFLAGS),
1102 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
1103 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
1104 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
1105 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 7, 1,
1106 MFLAGS),
1107 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
1108 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
1109 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
1110 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 11, 1,
1111 MFLAGS),
1112 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
1113 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
1114 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
1115 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
1116
1117 MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", clk_32k_ioe_p, 0, RK3568_PMU_GRF_SOC_CON0, 0, 1, MFLAGS)};
1118
1119 static void __iomem *rk3568_cru_base;
1120 static void __iomem *rk3568_pmucru_base;
1121
rk3568_dump_cru(void)1122 static void rk3568_dump_cru(void)
1123 {
1124 if (rk3568_pmucru_base) {
1125 pr_warn("PMU CRU:\n");
1126 }
1127 if (rk3568_cru_base) {
1128 pr_warn("CRU:\n");
1129 }
1130 }
1131
rk3568_pmu_clk_init(struct device_node * np)1132 static void __init rk3568_pmu_clk_init(struct device_node *np)
1133 {
1134 struct rockchip_clk_provider *ctx;
1135 void __iomem *reg_base;
1136
1137 reg_base = of_iomap(np, 0);
1138 if (!reg_base) {
1139 pr_err("%s: could not map cru pmu region\n", __func__);
1140 return;
1141 }
1142
1143 rk3568_pmucru_base = reg_base;
1144
1145 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1146 if (IS_ERR(ctx)) {
1147 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1148 return;
1149 }
1150
1151 rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, ARRAY_SIZE(rk3568_pmu_pll_clks), RK3568_GRF_SOC_STATUS0);
1152
1153 rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, ARRAY_SIZE(rk3568_clk_pmu_branches));
1154
1155 rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK);
1156
1157 rockchip_clk_of_add_provider(np, ctx);
1158 }
1159
1160 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
1161
rk3568_clk_init(struct device_node * np)1162 static void __init rk3568_clk_init(struct device_node *np)
1163 {
1164 struct rockchip_clk_provider *ctx;
1165 void __iomem *reg_base;
1166 struct clk **clks;
1167
1168 reg_base = of_iomap(np, 0);
1169 if (!reg_base) {
1170 pr_err("%s: could not map cru region\n", __func__);
1171 return;
1172 }
1173
1174 rk3568_cru_base = reg_base;
1175
1176 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1177 if (IS_ERR(ctx)) {
1178 pr_err("%s: rockchip clk init failed\n", __func__);
1179 iounmap(reg_base);
1180 return;
1181 }
1182 clks = ctx->clk_data.clks;
1183
1184 rockchip_clk_register_plls(ctx, rk3568_pll_clks, ARRAY_SIZE(rk3568_pll_clks), RK3568_GRF_SOC_STATUS0);
1185
1186 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3568_cpuclk_data,
1187 rk3568_cpuclk_rates, ARRAY_SIZE(rk3568_cpuclk_rates));
1188
1189 rockchip_clk_register_branches(ctx, rk3568_clk_branches, ARRAY_SIZE(rk3568_clk_branches));
1190
1191 rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK);
1192
1193 rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
1194
1195 rockchip_clk_of_add_provider(np, ctx);
1196
1197 if (!rk_dump_cru) {
1198 rk_dump_cru = rk3568_dump_cru;
1199 }
1200 }
1201
1202 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
1203
1204 struct clk_rk3568_inits {
1205 void (*inits)(struct device_node *np);
1206 };
1207
1208 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
1209 .inits = rk3568_pmu_clk_init,
1210 };
1211
1212 static const struct clk_rk3568_inits clk_3568_cru_init = {
1213 .inits = rk3568_clk_init,
1214 };
1215
1216 static const struct of_device_id clk_rk3568_match_table[] = {{
1217 .compatible = "rockchip,rk3568-cru",
1218 .data = &clk_3568_cru_init,
1219 }, {
1220 .compatible = "rockchip,rk3568-pmucru",
1221 .data = &clk_rk3568_pmucru_init,
1222 }, {
1223 }};
1224 MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
1225
clk_rk3568_probe(struct platform_device * pdev)1226 static int __init clk_rk3568_probe(struct platform_device *pdev)
1227 {
1228 struct device_node *np = pdev->dev.of_node;
1229 const struct of_device_id *match;
1230 const struct clk_rk3568_inits *init_data;
1231
1232 match = of_match_device(clk_rk3568_match_table, &pdev->dev);
1233 if (!match || !match->data) {
1234 return -EINVAL;
1235 }
1236
1237 init_data = match->data;
1238 if (init_data->inits) {
1239 init_data->inits(np);
1240 }
1241
1242 return 0;
1243 }
1244
1245 static struct platform_driver clk_rk3568_driver = {
1246 .driver =
1247 {
1248 .name = "clk-rk3568",
1249 .of_match_table = clk_rk3568_match_table,
1250 .suppress_bind_attrs = true,
1251 },
1252 };
1253 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
1254
1255 MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
1256 MODULE_LICENSE("GPL");
1257 MODULE_ALIAS("platform:clk-rk3568");
1258