1 /* 2 * Copyright 2016 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __MPP_RC_DEFS_H__ 18 #define __MPP_RC_DEFS_H__ 19 20 #include "rk_venc_ref.h" 21 22 #define MAX_CPB_REFS (8) 23 24 typedef enum EncFrmType_e { 25 INTER_P_FRAME = 0, 26 INTER_B_FRAME = 1, 27 INTRA_FRAME = 2, 28 INTER_VI_FRAME = 3, 29 } EncFrmType; 30 31 /* 32 * EncFrmStatus controls record the encoding frame status and also control 33 * work flow of encoder. It is the communicat channel between encoder implement 34 * module, rate control module and hardware module. 35 * 36 * bit 0 ~ 31 frame status 37 * 0 ~ 15 current frame status 38 * 16 ~ 31 reference frame status 39 * bit 32 ~ 63 encoding flow control 40 */ 41 typedef union EncFrmStatus_u { 42 struct { 43 /* 44 * bit 0 ~ 31 frame status 45 */ 46 /* status flag */ 47 RK_U32 valid : 1; 48 /* 49 * 0 - write the reconstructed frame pixel to memory 50 * 1 - do not write the reconstructed frame pixel to memory 51 */ 52 RK_U32 non_recn : 1; 53 54 /* 55 * 0 - normal frame and normal dpb management 56 * 1 - save recon frame as first pass extra frame. Used in two pass mode 57 */ 58 RK_U32 save_pass1 : 1; 59 60 /* 61 * 0 - use normal input source frame as input 62 * 1 - use the previously stored first pass recon frame as input frame 63 */ 64 RK_U32 use_pass1 : 1; 65 66 /* reference status flag */ 67 /* 68 * 0 - inter frame 69 * 1 - intra frame 70 */ 71 RK_U32 is_intra : 1; 72 73 /* 74 * Valid when is_intra is true 75 * 0 - normal intra frame 76 * 1 - IDR frame 77 */ 78 RK_U32 is_idr : 1; 79 80 /* 81 * 0 - mark as reference frame 82 * 1 - mark as non-refernce frame 83 */ 84 RK_U32 is_non_ref : 1; 85 86 /* 87 * Valid when is_non_ref is false 88 * 0 - mark as short-term reference frame 89 * 1 - mark as long-term refernce frame 90 */ 91 RK_U32 is_lt_ref : 1; 92 93 /* bit 8 - 15 */ 94 RK_U32 lt_idx : 4; 95 RK_U32 temporal_id : 4; 96 97 /* distance between current frame and reference frame */ 98 MppEncRefMode ref_mode : 6; 99 RK_S32 ref_arg : 8; 100 RK_S32 ref_dist : 2; 101 102 /* 103 * bit 32 ~ 63 encoder flow control flags 104 */ 105 /* 106 * 0 - normal frame encoding 107 * 1 - current frame will be dropped 108 */ 109 RK_U32 drop : 1; 110 111 /* 112 * 0 - rate control module does not change frame type parameter 113 * 1 - rate control module changes frame type parameter reencode is needed 114 * to reprocess the dpb process. Also this means dpb module will follow 115 * the frame status parameter provided by rate control module. 116 */ 117 RK_U32 re_dpb_proc : 1; 118 119 /* 120 * 0 - current frame encoding is in normal flow 121 * 1 - current frame encoding is in reencode flow 122 */ 123 RK_U32 reencode : 1; 124 125 /* 126 * When true current frame size is super large then the frame should be reencoded. 127 */ 128 RK_U32 super_frame : 1; 129 130 /* 131 * When true currnet frame is force to encoded as software skip frame 132 */ 133 RK_U32 force_pskip : 1; 134 RK_U32 reserved1 : 3; 135 136 /* reencode times */ 137 RK_U32 reencode_times : 8; 138 139 /* sequential index for each frame */ 140 RK_U32 seq_idx : 16; 141 }; 142 RK_U64 val; 143 } EncFrmStatus; 144 145 typedef struct EncCpbStatus_t { 146 RK_S32 seq_idx; 147 148 EncFrmStatus curr; 149 EncFrmStatus refr; 150 151 /* initial cpb status for current frame encoding */ 152 EncFrmStatus init[MAX_CPB_REFS]; 153 /* final cpb status after current frame encoding */ 154 EncFrmStatus final[MAX_CPB_REFS]; 155 } EncCpbStatus; 156 157 #define ENC_RC_FORCE_QP (0x00000001) 158 159 typedef struct EncRcForceCfg_t { 160 RK_U32 force_flag; 161 RK_S32 force_qp; 162 RK_U32 reserve[6]; 163 } EncRcForceCfg; 164 165 /* 166 * communication channel between rc / hal / hardware 167 * 168 * rc -> hal bit_target / bit_max / bit_min 169 * hal -> hw quality_target / quality_max / quality_min 170 * hw -> rc / hal bit_real / quality_real / madi / madp 171 */ 172 typedef struct EncRcCommonInfo_t { 173 EncFrmType frame_type; 174 175 /* rc to hal */ 176 RK_S32 bit_target; 177 RK_S32 bit_max; 178 RK_S32 bit_min; 179 180 RK_S32 quality_target; 181 RK_S32 quality_max; 182 RK_S32 quality_min; 183 184 /* rc from hardware */ 185 RK_S32 bit_real; 186 RK_S32 quality_real; 187 RK_S32 madi; 188 RK_S32 madp; 189 190 RK_U32 iblk4_prop; // scale 256 191 RK_S32 reserve[15]; 192 } EncRcTaskInfo; 193 194 typedef struct EncRcTask_s { 195 EncCpbStatus cpb; 196 EncFrmStatus frm; 197 EncRcTaskInfo info; 198 EncRcForceCfg force; 199 MppFrame frame; 200 } EncRcTask; 201 202 #endif /* __MPP_RC_DEFS_H__ */ 203