1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __ROCKCHIP_DMC_TIMING_H__ 7 #define __ROCKCHIP_DMC_TIMING_H__ 8 9 /* hope this define can adapt all future platfor */ 10 static const char * const px30_dts_timing[] = { 11 "ddr2_speed_bin", 12 "ddr3_speed_bin", 13 "ddr4_speed_bin", 14 "pd_idle", 15 "sr_idle", 16 "sr_mc_gate_idle", 17 "srpd_lite_idle", 18 "standby_idle", 19 20 "auto_pd_dis_freq", 21 "auto_sr_dis_freq", 22 "ddr2_dll_dis_freq", 23 "ddr3_dll_dis_freq", 24 "ddr4_dll_dis_freq", 25 "phy_dll_dis_freq", 26 27 "ddr2_odt_dis_freq", 28 "phy_ddr2_odt_dis_freq", 29 "ddr2_drv", 30 "ddr2_odt", 31 "phy_ddr2_ca_drv", 32 "phy_ddr2_ck_drv", 33 "phy_ddr2_dq_drv", 34 "phy_ddr2_odt", 35 36 "ddr3_odt_dis_freq", 37 "phy_ddr3_odt_dis_freq", 38 "ddr3_drv", 39 "ddr3_odt", 40 "phy_ddr3_ca_drv", 41 "phy_ddr3_ck_drv", 42 "phy_ddr3_dq_drv", 43 "phy_ddr3_odt", 44 45 "phy_lpddr2_odt_dis_freq", 46 "lpddr2_drv", 47 "phy_lpddr2_ca_drv", 48 "phy_lpddr2_ck_drv", 49 "phy_lpddr2_dq_drv", 50 "phy_lpddr2_odt", 51 52 "lpddr3_odt_dis_freq", 53 "phy_lpddr3_odt_dis_freq", 54 "lpddr3_drv", 55 "lpddr3_odt", 56 "phy_lpddr3_ca_drv", 57 "phy_lpddr3_ck_drv", 58 "phy_lpddr3_dq_drv", 59 "phy_lpddr3_odt", 60 61 "lpddr4_odt_dis_freq", 62 "phy_lpddr4_odt_dis_freq", 63 "lpddr4_drv", 64 "lpddr4_dq_odt", 65 "lpddr4_ca_odt", 66 "phy_lpddr4_ca_drv", 67 "phy_lpddr4_ck_cs_drv", 68 "phy_lpddr4_dq_drv", 69 "phy_lpddr4_odt", 70 71 "ddr4_odt_dis_freq", 72 "phy_ddr4_odt_dis_freq", 73 "ddr4_drv", 74 "ddr4_odt", 75 "phy_ddr4_ca_drv", 76 "phy_ddr4_ck_drv", 77 "phy_ddr4_dq_drv", 78 "phy_ddr4_odt", 79 }; 80 81 struct px30_ddr_dts_config_timing { 82 unsigned int ddr2_speed_bin; 83 unsigned int ddr3_speed_bin; 84 unsigned int ddr4_speed_bin; 85 unsigned int pd_idle; 86 unsigned int sr_idle; 87 unsigned int sr_mc_gate_idle; 88 unsigned int srpd_lite_idle; 89 unsigned int standby_idle; 90 91 unsigned int auto_pd_dis_freq; 92 unsigned int auto_sr_dis_freq; 93 /* for ddr2 only */ 94 unsigned int ddr2_dll_dis_freq; 95 /* for ddr3 only */ 96 unsigned int ddr3_dll_dis_freq; 97 /* for ddr4 only */ 98 unsigned int ddr4_dll_dis_freq; 99 unsigned int phy_dll_dis_freq; 100 101 unsigned int ddr2_odt_dis_freq; 102 unsigned int phy_ddr2_odt_dis_freq; 103 unsigned int ddr2_drv; 104 unsigned int ddr2_odt; 105 unsigned int phy_ddr2_ca_drv; 106 unsigned int phy_ddr2_ck_drv; 107 unsigned int phy_ddr2_dq_drv; 108 unsigned int phy_ddr2_odt; 109 110 unsigned int ddr3_odt_dis_freq; 111 unsigned int phy_ddr3_odt_dis_freq; 112 unsigned int ddr3_drv; 113 unsigned int ddr3_odt; 114 unsigned int phy_ddr3_ca_drv; 115 unsigned int phy_ddr3_ck_drv; 116 unsigned int phy_ddr3_dq_drv; 117 unsigned int phy_ddr3_odt; 118 119 unsigned int phy_lpddr2_odt_dis_freq; 120 unsigned int lpddr2_drv; 121 unsigned int phy_lpddr2_ca_drv; 122 unsigned int phy_lpddr2_ck_drv; 123 unsigned int phy_lpddr2_dq_drv; 124 unsigned int phy_lpddr2_odt; 125 126 unsigned int lpddr3_odt_dis_freq; 127 unsigned int phy_lpddr3_odt_dis_freq; 128 unsigned int lpddr3_drv; 129 unsigned int lpddr3_odt; 130 unsigned int phy_lpddr3_ca_drv; 131 unsigned int phy_lpddr3_ck_drv; 132 unsigned int phy_lpddr3_dq_drv; 133 unsigned int phy_lpddr3_odt; 134 135 unsigned int lpddr4_odt_dis_freq; 136 unsigned int phy_lpddr4_odt_dis_freq; 137 unsigned int lpddr4_drv; 138 unsigned int lpddr4_dq_odt; 139 unsigned int lpddr4_ca_odt; 140 unsigned int phy_lpddr4_ca_drv; 141 unsigned int phy_lpddr4_ck_cs_drv; 142 unsigned int phy_lpddr4_dq_drv; 143 unsigned int phy_lpddr4_odt; 144 145 unsigned int ddr4_odt_dis_freq; 146 unsigned int phy_ddr4_odt_dis_freq; 147 unsigned int ddr4_drv; 148 unsigned int ddr4_odt; 149 unsigned int phy_ddr4_ca_drv; 150 unsigned int phy_ddr4_ck_drv; 151 unsigned int phy_ddr4_dq_drv; 152 unsigned int phy_ddr4_odt; 153 154 unsigned int ca_skew[15]; 155 unsigned int cs0_skew[44]; 156 unsigned int cs1_skew[44]; 157 158 unsigned int available; 159 }; 160 161 static const char * const rk1808_dts_ca_timing[] = { 162 "a0_ddr3a9_de-skew", 163 "a1_ddr3a14_de-skew", 164 "a2_ddr3a13_de-skew", 165 "a3_ddr3a11_de-skew", 166 "a4_ddr3a2_de-skew", 167 "a5_ddr3a4_de-skew", 168 "a6_ddr3a3_de-skew", 169 "a7_ddr3a6_de-skew", 170 "a8_ddr3a5_de-skew", 171 "a9_ddr3a1_de-skew", 172 "a10_ddr3a0_de-skew", 173 "a11_ddr3a7_de-skew", 174 "a12_ddr3casb_de-skew", 175 "a13_ddr3a8_de-skew", 176 "a14_ddr3odt0_de-skew", 177 "a15_ddr3ba1_de-skew", 178 "a16_ddr3rasb_de-skew", 179 "a17_ddr3null_de-skew", 180 "ba0_ddr3ba2_de-skew", 181 "ba1_ddr3a12_de-skew", 182 "bg0_ddr3ba0_de-skew", 183 "bg1_ddr3web_de-skew", 184 "cke_ddr3cke_de-skew", 185 "ck_ddr3ck_de-skew", 186 "ckb_ddr3ckb_de-skew", 187 "csb0_ddr3a10_de-skew", 188 "odt0_ddr3a15_de-skew", 189 "resetn_ddr3resetn_de-skew", 190 "actn_ddr3csb0_de-skew", 191 "csb1_ddr3csb1_de-skew", 192 "odt1_ddr3odt1_de-skew", 193 }; 194 195 static const char * const rk1808_dts_cs0_a_timing[] = { 196 "cs0_dm0_rx_de-skew", 197 "cs0_dm0_tx_de-skew", 198 "cs0_dq0_rx_de-skew", 199 "cs0_dq0_tx_de-skew", 200 "cs0_dq1_rx_de-skew", 201 "cs0_dq1_tx_de-skew", 202 "cs0_dq2_rx_de-skew", 203 "cs0_dq2_tx_de-skew", 204 "cs0_dq3_rx_de-skew", 205 "cs0_dq3_tx_de-skew", 206 "cs0_dq4_rx_de-skew", 207 "cs0_dq4_tx_de-skew", 208 "cs0_dq5_rx_de-skew", 209 "cs0_dq5_tx_de-skew", 210 "cs0_dq6_rx_de-skew", 211 "cs0_dq6_tx_de-skew", 212 "cs0_dq7_rx_de-skew", 213 "cs0_dq7_tx_de-skew", 214 "cs0_dqs0p_rx_de-skew", 215 "cs0_dqs0p_tx_de-skew", 216 "cs0_dqs0n_tx_de-skew", 217 "cs0_dm1_rx_de-skew", 218 "cs0_dm1_tx_de-skew", 219 "cs0_dq8_rx_de-skew", 220 "cs0_dq8_tx_de-skew", 221 "cs0_dq9_rx_de-skew", 222 "cs0_dq9_tx_de-skew", 223 "cs0_dq10_rx_de-skew", 224 "cs0_dq10_tx_de-skew", 225 "cs0_dq11_rx_de-skew", 226 "cs0_dq11_tx_de-skew", 227 "cs0_dq12_rx_de-skew", 228 "cs0_dq12_tx_de-skew", 229 "cs0_dq13_rx_de-skew", 230 "cs0_dq13_tx_de-skew", 231 "cs0_dq14_rx_de-skew", 232 "cs0_dq14_tx_de-skew", 233 "cs0_dq15_rx_de-skew", 234 "cs0_dq15_tx_de-skew", 235 "cs0_dqs1p_rx_de-skew", 236 "cs0_dqs1p_tx_de-skew", 237 "cs0_dqs1n_tx_de-skew", 238 "cs0_dqs0n_rx_de-skew", 239 "cs0_dqs1n_rx_de-skew", 240 }; 241 242 static const char * const rk1808_dts_cs0_b_timing[] = { 243 "cs0_dm2_rx_de-skew", 244 "cs0_dm2_tx_de-skew", 245 "cs0_dq16_rx_de-skew", 246 "cs0_dq16_tx_de-skew", 247 "cs0_dq17_rx_de-skew", 248 "cs0_dq17_tx_de-skew", 249 "cs0_dq18_rx_de-skew", 250 "cs0_dq18_tx_de-skew", 251 "cs0_dq19_rx_de-skew", 252 "cs0_dq19_tx_de-skew", 253 "cs0_dq20_rx_de-skew", 254 "cs0_dq20_tx_de-skew", 255 "cs0_dq21_rx_de-skew", 256 "cs0_dq21_tx_de-skew", 257 "cs0_dq22_rx_de-skew", 258 "cs0_dq22_tx_de-skew", 259 "cs0_dq23_rx_de-skew", 260 "cs0_dq23_tx_de-skew", 261 "cs0_dqs2p_rx_de-skew", 262 "cs0_dqs2p_tx_de-skew", 263 "cs0_dqs2n_tx_de-skew", 264 "cs0_dm3_rx_de-skew", 265 "cs0_dm3_tx_de-skew", 266 "cs0_dq24_rx_de-skew", 267 "cs0_dq24_tx_de-skew", 268 "cs0_dq25_rx_de-skew", 269 "cs0_dq25_tx_de-skew", 270 "cs0_dq26_rx_de-skew", 271 "cs0_dq26_tx_de-skew", 272 "cs0_dq27_rx_de-skew", 273 "cs0_dq27_tx_de-skew", 274 "cs0_dq28_rx_de-skew", 275 "cs0_dq28_tx_de-skew", 276 "cs0_dq29_rx_de-skew", 277 "cs0_dq29_tx_de-skew", 278 "cs0_dq30_rx_de-skew", 279 "cs0_dq30_tx_de-skew", 280 "cs0_dq31_rx_de-skew", 281 "cs0_dq31_tx_de-skew", 282 "cs0_dqs3p_rx_de-skew", 283 "cs0_dqs3p_tx_de-skew", 284 "cs0_dqs3n_tx_de-skew", 285 "cs0_dqs2n_rx_de-skew", 286 "cs0_dqs3n_rx_de-skew", 287 }; 288 289 static const char * const rk1808_dts_cs1_a_timing[] = { 290 "cs1_dm0_rx_de-skew", 291 "cs1_dm0_tx_de-skew", 292 "cs1_dq0_rx_de-skew", 293 "cs1_dq0_tx_de-skew", 294 "cs1_dq1_rx_de-skew", 295 "cs1_dq1_tx_de-skew", 296 "cs1_dq2_rx_de-skew", 297 "cs1_dq2_tx_de-skew", 298 "cs1_dq3_rx_de-skew", 299 "cs1_dq3_tx_de-skew", 300 "cs1_dq4_rx_de-skew", 301 "cs1_dq4_tx_de-skew", 302 "cs1_dq5_rx_de-skew", 303 "cs1_dq5_tx_de-skew", 304 "cs1_dq6_rx_de-skew", 305 "cs1_dq6_tx_de-skew", 306 "cs1_dq7_rx_de-skew", 307 "cs1_dq7_tx_de-skew", 308 "cs1_dqs0p_rx_de-skew", 309 "cs1_dqs0p_tx_de-skew", 310 "cs1_dqs0n_tx_de-skew", 311 "cs1_dm1_rx_de-skew", 312 "cs1_dm1_tx_de-skew", 313 "cs1_dq8_rx_de-skew", 314 "cs1_dq8_tx_de-skew", 315 "cs1_dq9_rx_de-skew", 316 "cs1_dq9_tx_de-skew", 317 "cs1_dq10_rx_de-skew", 318 "cs1_dq10_tx_de-skew", 319 "cs1_dq11_rx_de-skew", 320 "cs1_dq11_tx_de-skew", 321 "cs1_dq12_rx_de-skew", 322 "cs1_dq12_tx_de-skew", 323 "cs1_dq13_rx_de-skew", 324 "cs1_dq13_tx_de-skew", 325 "cs1_dq14_rx_de-skew", 326 "cs1_dq14_tx_de-skew", 327 "cs1_dq15_rx_de-skew", 328 "cs1_dq15_tx_de-skew", 329 "cs1_dqs1p_rx_de-skew", 330 "cs1_dqs1p_tx_de-skew", 331 "cs1_dqs1n_tx_de-skew", 332 "cs1_dqs0n_rx_de-skew", 333 "cs1_dqs1n_rx_de-skew", 334 }; 335 336 static const char * const rk1808_dts_cs1_b_timing[] = { 337 "cs1_dm2_rx_de-skew", 338 "cs1_dm2_tx_de-skew", 339 "cs1_dq16_rx_de-skew", 340 "cs1_dq16_tx_de-skew", 341 "cs1_dq17_rx_de-skew", 342 "cs1_dq17_tx_de-skew", 343 "cs1_dq18_rx_de-skew", 344 "cs1_dq18_tx_de-skew", 345 "cs1_dq19_rx_de-skew", 346 "cs1_dq19_tx_de-skew", 347 "cs1_dq20_rx_de-skew", 348 "cs1_dq20_tx_de-skew", 349 "cs1_dq21_rx_de-skew", 350 "cs1_dq21_tx_de-skew", 351 "cs1_dq22_rx_de-skew", 352 "cs1_dq22_tx_de-skew", 353 "cs1_dq23_rx_de-skew", 354 "cs1_dq23_tx_de-skew", 355 "cs1_dqs2p_rx_de-skew", 356 "cs1_dqs2p_tx_de-skew", 357 "cs1_dqs2n_tx_de-skew", 358 "cs1_dm3_rx_de-skew", 359 "cs1_dm3_tx_de-skew", 360 "cs1_dq24_rx_de-skew", 361 "cs1_dq24_tx_de-skew", 362 "cs1_dq25_rx_de-skew", 363 "cs1_dq25_tx_de-skew", 364 "cs1_dq26_rx_de-skew", 365 "cs1_dq26_tx_de-skew", 366 "cs1_dq27_rx_de-skew", 367 "cs1_dq27_tx_de-skew", 368 "cs1_dq28_rx_de-skew", 369 "cs1_dq28_tx_de-skew", 370 "cs1_dq29_rx_de-skew", 371 "cs1_dq29_tx_de-skew", 372 "cs1_dq30_rx_de-skew", 373 "cs1_dq30_tx_de-skew", 374 "cs1_dq31_rx_de-skew", 375 "cs1_dq31_tx_de-skew", 376 "cs1_dqs3p_rx_de-skew", 377 "cs1_dqs3p_tx_de-skew", 378 "cs1_dqs3n_tx_de-skew", 379 "cs1_dqs2n_rx_de-skew", 380 "cs1_dqs3n_rx_de-skew", 381 }; 382 383 struct rk1808_ddr_dts_config_timing { 384 unsigned int ddr2_speed_bin; 385 unsigned int ddr3_speed_bin; 386 unsigned int ddr4_speed_bin; 387 unsigned int pd_idle; 388 unsigned int sr_idle; 389 unsigned int sr_mc_gate_idle; 390 unsigned int srpd_lite_idle; 391 unsigned int standby_idle; 392 393 unsigned int auto_pd_dis_freq; 394 unsigned int auto_sr_dis_freq; 395 /* for ddr2 only */ 396 unsigned int ddr2_dll_dis_freq; 397 /* for ddr3 only */ 398 unsigned int ddr3_dll_dis_freq; 399 /* for ddr4 only */ 400 unsigned int ddr4_dll_dis_freq; 401 unsigned int phy_dll_dis_freq; 402 403 unsigned int ddr2_odt_dis_freq; 404 unsigned int phy_ddr2_odt_dis_freq; 405 unsigned int ddr2_drv; 406 unsigned int ddr2_odt; 407 unsigned int phy_ddr2_ca_drv; 408 unsigned int phy_ddr2_ck_drv; 409 unsigned int phy_ddr2_dq_drv; 410 unsigned int phy_ddr2_odt; 411 412 unsigned int ddr3_odt_dis_freq; 413 unsigned int phy_ddr3_odt_dis_freq; 414 unsigned int ddr3_drv; 415 unsigned int ddr3_odt; 416 unsigned int phy_ddr3_ca_drv; 417 unsigned int phy_ddr3_ck_drv; 418 unsigned int phy_ddr3_dq_drv; 419 unsigned int phy_ddr3_odt; 420 421 unsigned int phy_lpddr2_odt_dis_freq; 422 unsigned int lpddr2_drv; 423 unsigned int phy_lpddr2_ca_drv; 424 unsigned int phy_lpddr2_ck_drv; 425 unsigned int phy_lpddr2_dq_drv; 426 unsigned int phy_lpddr2_odt; 427 428 unsigned int lpddr3_odt_dis_freq; 429 unsigned int phy_lpddr3_odt_dis_freq; 430 unsigned int lpddr3_drv; 431 unsigned int lpddr3_odt; 432 unsigned int phy_lpddr3_ca_drv; 433 unsigned int phy_lpddr3_ck_drv; 434 unsigned int phy_lpddr3_dq_drv; 435 unsigned int phy_lpddr3_odt; 436 437 unsigned int lpddr4_odt_dis_freq; 438 unsigned int phy_lpddr4_odt_dis_freq; 439 unsigned int lpddr4_drv; 440 unsigned int lpddr4_dq_odt; 441 unsigned int lpddr4_ca_odt; 442 unsigned int phy_lpddr4_ca_drv; 443 unsigned int phy_lpddr4_ck_cs_drv; 444 unsigned int phy_lpddr4_dq_drv; 445 unsigned int phy_lpddr4_odt; 446 447 unsigned int ddr4_odt_dis_freq; 448 unsigned int phy_ddr4_odt_dis_freq; 449 unsigned int ddr4_drv; 450 unsigned int ddr4_odt; 451 unsigned int phy_ddr4_ca_drv; 452 unsigned int phy_ddr4_ck_drv; 453 unsigned int phy_ddr4_dq_drv; 454 unsigned int phy_ddr4_odt; 455 456 unsigned int ca_de_skew[31]; 457 unsigned int cs0_a_de_skew[44]; 458 unsigned int cs0_b_de_skew[44]; 459 unsigned int cs1_a_de_skew[44]; 460 unsigned int cs1_b_de_skew[44]; 461 462 unsigned int available; 463 }; 464 465 static const char * const rk3128_dts_timing[] = { 466 "ddr3_speed_bin", 467 "pd_idle", 468 "sr_idle", 469 "auto_pd_dis_freq", 470 "auto_sr_dis_freq", 471 "ddr3_dll_dis_freq", 472 "lpddr2_dll_dis_freq", 473 "phy_dll_dis_freq", 474 "ddr3_odt_dis_freq", 475 "phy_ddr3_odt_disb_freq", 476 "ddr3_drv", 477 "ddr3_odt", 478 "phy_ddr3_clk_drv", 479 "phy_ddr3_cmd_drv", 480 "phy_ddr3_dqs_drv", 481 "phy_ddr3_odt", 482 "lpddr2_drv", 483 "phy_lpddr2_clk_drv", 484 "phy_lpddr2_cmd_drv", 485 "phy_lpddr2_dqs_drv", 486 "ddr_2t", 487 }; 488 489 struct rk3128_ddr_dts_config_timing { 490 u32 ddr3_speed_bin; 491 u32 pd_idle; 492 u32 sr_idle; 493 u32 auto_pd_dis_freq; 494 u32 auto_sr_dis_freq; 495 u32 ddr3_dll_dis_freq; 496 u32 lpddr2_dll_dis_freq; 497 u32 phy_dll_dis_freq; 498 u32 ddr3_odt_dis_freq; 499 u32 phy_ddr3_odt_disb_freq; 500 u32 ddr3_drv; 501 u32 ddr3_odt; 502 u32 phy_ddr3_clk_drv; 503 u32 phy_ddr3_cmd_drv; 504 u32 phy_ddr3_dqs_drv; 505 u32 phy_ddr3_odt; 506 u32 lpddr2_drv; 507 u32 phy_lpddr2_clk_drv; 508 u32 phy_lpddr2_cmd_drv; 509 u32 phy_lpddr2_dqs_drv; 510 u32 ddr_2t; 511 u32 available; 512 }; 513 514 static const char * const rk3228_dts_timing[] = { 515 "dram_spd_bin", 516 "sr_idle", 517 "pd_idle", 518 "dram_dll_disb_freq", 519 "phy_dll_disb_freq", 520 "dram_odt_disb_freq", 521 "phy_odt_disb_freq", 522 "ddr3_drv", 523 "ddr3_odt", 524 "lpddr3_drv", 525 "lpddr3_odt", 526 "lpddr2_drv", 527 "phy_ddr3_clk_drv", 528 "phy_ddr3_cmd_drv", 529 "phy_ddr3_dqs_drv", 530 "phy_ddr3_odt", 531 "phy_lp23_clk_drv", 532 "phy_lp23_cmd_drv", 533 "phy_lp23_dqs_drv", 534 "phy_lp3_odt" 535 }; 536 537 struct rk3228_ddr_dts_config_timing { 538 u32 dram_spd_bin; 539 u32 sr_idle; 540 u32 pd_idle; 541 u32 dram_dll_dis_freq; 542 u32 phy_dll_dis_freq; 543 u32 dram_odt_dis_freq; 544 u32 phy_odt_dis_freq; 545 u32 ddr3_drv; 546 u32 ddr3_odt; 547 u32 lpddr3_drv; 548 u32 lpddr3_odt; 549 u32 lpddr2_drv; 550 u32 phy_ddr3_clk_drv; 551 u32 phy_ddr3_cmd_drv; 552 u32 phy_ddr3_dqs_drv; 553 u32 phy_ddr3_odt; 554 u32 phy_lp23_clk_drv; 555 u32 phy_lp23_cmd_drv; 556 u32 phy_lp23_dqs_drv; 557 u32 phy_lp3_odt; 558 }; 559 560 static const char * const rk3288_dts_timing[] = { 561 "ddr3_speed_bin", 562 "pd_idle", 563 "sr_idle", 564 565 "auto_pd_dis_freq", 566 "auto_sr_dis_freq", 567 /* for ddr3 only */ 568 "ddr3_dll_dis_freq", 569 "phy_dll_dis_freq", 570 571 "ddr3_odt_dis_freq", 572 "phy_ddr3_odt_dis_freq", 573 "ddr3_drv", 574 "ddr3_odt", 575 "phy_ddr3_drv", 576 "phy_ddr3_odt", 577 578 "lpddr2_drv", 579 "phy_lpddr2_drv", 580 581 "lpddr3_odt_dis_freq", 582 "phy_lpddr3_odt_dis_freq", 583 "lpddr3_drv", 584 "lpddr3_odt", 585 "phy_lpddr3_drv", 586 "phy_lpddr3_odt" 587 }; 588 589 struct rk3288_ddr_dts_config_timing { 590 unsigned int ddr3_speed_bin; 591 unsigned int pd_idle; 592 unsigned int sr_idle; 593 594 unsigned int auto_pd_dis_freq; 595 unsigned int auto_sr_dis_freq; 596 /* for ddr3 only */ 597 unsigned int ddr3_dll_dis_freq; 598 unsigned int phy_dll_dis_freq; 599 600 unsigned int ddr3_odt_dis_freq; 601 unsigned int phy_ddr3_odt_dis_freq; 602 unsigned int ddr3_drv; 603 unsigned int ddr3_odt; 604 unsigned int phy_ddr3_drv; 605 unsigned int phy_ddr3_odt; 606 607 unsigned int lpddr2_drv; 608 unsigned int phy_lpddr2_drv; 609 610 unsigned int lpddr3_odt_dis_freq; 611 unsigned int phy_lpddr3_odt_dis_freq; 612 unsigned int lpddr3_drv; 613 unsigned int lpddr3_odt; 614 unsigned int phy_lpddr3_drv; 615 unsigned int phy_lpddr3_odt; 616 617 unsigned int available; 618 }; 619 620 /* hope this define can adapt all future platfor */ 621 static const char * const rk3328_dts_timing[] = { 622 "ddr3_speed_bin", 623 "ddr4_speed_bin", 624 "pd_idle", 625 "sr_idle", 626 "sr_mc_gate_idle", 627 "srpd_lite_idle", 628 "standby_idle", 629 630 "auto_pd_dis_freq", 631 "auto_sr_dis_freq", 632 "ddr3_dll_dis_freq", 633 "ddr4_dll_dis_freq", 634 "phy_dll_dis_freq", 635 636 "ddr3_odt_dis_freq", 637 "phy_ddr3_odt_dis_freq", 638 "ddr3_drv", 639 "ddr3_odt", 640 "phy_ddr3_ca_drv", 641 "phy_ddr3_ck_drv", 642 "phy_ddr3_dq_drv", 643 "phy_ddr3_odt", 644 645 "lpddr3_odt_dis_freq", 646 "phy_lpddr3_odt_dis_freq", 647 "lpddr3_drv", 648 "lpddr3_odt", 649 "phy_lpddr3_ca_drv", 650 "phy_lpddr3_ck_drv", 651 "phy_lpddr3_dq_drv", 652 "phy_lpddr3_odt", 653 654 "lpddr4_odt_dis_freq", 655 "phy_lpddr4_odt_dis_freq", 656 "lpddr4_drv", 657 "lpddr4_dq_odt", 658 "lpddr4_ca_odt", 659 "phy_lpddr4_ca_drv", 660 "phy_lpddr4_ck_cs_drv", 661 "phy_lpddr4_dq_drv", 662 "phy_lpddr4_odt", 663 664 "ddr4_odt_dis_freq", 665 "phy_ddr4_odt_dis_freq", 666 "ddr4_drv", 667 "ddr4_odt", 668 "phy_ddr4_ca_drv", 669 "phy_ddr4_ck_drv", 670 "phy_ddr4_dq_drv", 671 "phy_ddr4_odt", 672 }; 673 674 static const char * const rk3328_dts_ca_timing[] = { 675 "ddr3a1_ddr4a9_de-skew", 676 "ddr3a0_ddr4a10_de-skew", 677 "ddr3a3_ddr4a6_de-skew", 678 "ddr3a2_ddr4a4_de-skew", 679 "ddr3a5_ddr4a8_de-skew", 680 "ddr3a4_ddr4a5_de-skew", 681 "ddr3a7_ddr4a11_de-skew", 682 "ddr3a6_ddr4a7_de-skew", 683 "ddr3a9_ddr4a0_de-skew", 684 "ddr3a8_ddr4a13_de-skew", 685 "ddr3a11_ddr4a3_de-skew", 686 "ddr3a10_ddr4cs0_de-skew", 687 "ddr3a13_ddr4a2_de-skew", 688 "ddr3a12_ddr4ba1_de-skew", 689 "ddr3a15_ddr4odt0_de-skew", 690 "ddr3a14_ddr4a1_de-skew", 691 "ddr3ba1_ddr4a15_de-skew", 692 "ddr3ba0_ddr4bg0_de-skew", 693 "ddr3ras_ddr4cke_de-skew", 694 "ddr3ba2_ddr4ba0_de-skew", 695 "ddr3we_ddr4bg1_de-skew", 696 "ddr3cas_ddr4a12_de-skew", 697 "ddr3ckn_ddr4ckn_de-skew", 698 "ddr3ckp_ddr4ckp_de-skew", 699 "ddr3cke_ddr4a16_de-skew", 700 "ddr3odt0_ddr4a14_de-skew", 701 "ddr3cs0_ddr4act_de-skew", 702 "ddr3reset_ddr4reset_de-skew", 703 "ddr3cs1_ddr4cs1_de-skew", 704 "ddr3odt1_ddr4odt1_de-skew", 705 }; 706 707 static const char * const rk3328_dts_cs0_timing[] = { 708 "cs0_dm0_rx_de-skew", 709 "cs0_dm0_tx_de-skew", 710 "cs0_dq0_rx_de-skew", 711 "cs0_dq0_tx_de-skew", 712 "cs0_dq1_rx_de-skew", 713 "cs0_dq1_tx_de-skew", 714 "cs0_dq2_rx_de-skew", 715 "cs0_dq2_tx_de-skew", 716 "cs0_dq3_rx_de-skew", 717 "cs0_dq3_tx_de-skew", 718 "cs0_dq4_rx_de-skew", 719 "cs0_dq4_tx_de-skew", 720 "cs0_dq5_rx_de-skew", 721 "cs0_dq5_tx_de-skew", 722 "cs0_dq6_rx_de-skew", 723 "cs0_dq6_tx_de-skew", 724 "cs0_dq7_rx_de-skew", 725 "cs0_dq7_tx_de-skew", 726 "cs0_dqs0_rx_de-skew", 727 "cs0_dqs0p_tx_de-skew", 728 "cs0_dqs0n_tx_de-skew", 729 730 "cs0_dm1_rx_de-skew", 731 "cs0_dm1_tx_de-skew", 732 "cs0_dq8_rx_de-skew", 733 "cs0_dq8_tx_de-skew", 734 "cs0_dq9_rx_de-skew", 735 "cs0_dq9_tx_de-skew", 736 "cs0_dq10_rx_de-skew", 737 "cs0_dq10_tx_de-skew", 738 "cs0_dq11_rx_de-skew", 739 "cs0_dq11_tx_de-skew", 740 "cs0_dq12_rx_de-skew", 741 "cs0_dq12_tx_de-skew", 742 "cs0_dq13_rx_de-skew", 743 "cs0_dq13_tx_de-skew", 744 "cs0_dq14_rx_de-skew", 745 "cs0_dq14_tx_de-skew", 746 "cs0_dq15_rx_de-skew", 747 "cs0_dq15_tx_de-skew", 748 "cs0_dqs1_rx_de-skew", 749 "cs0_dqs1p_tx_de-skew", 750 "cs0_dqs1n_tx_de-skew", 751 752 "cs0_dm2_rx_de-skew", 753 "cs0_dm2_tx_de-skew", 754 "cs0_dq16_rx_de-skew", 755 "cs0_dq16_tx_de-skew", 756 "cs0_dq17_rx_de-skew", 757 "cs0_dq17_tx_de-skew", 758 "cs0_dq18_rx_de-skew", 759 "cs0_dq18_tx_de-skew", 760 "cs0_dq19_rx_de-skew", 761 "cs0_dq19_tx_de-skew", 762 "cs0_dq20_rx_de-skew", 763 "cs0_dq20_tx_de-skew", 764 "cs0_dq21_rx_de-skew", 765 "cs0_dq21_tx_de-skew", 766 "cs0_dq22_rx_de-skew", 767 "cs0_dq22_tx_de-skew", 768 "cs0_dq23_rx_de-skew", 769 "cs0_dq23_tx_de-skew", 770 "cs0_dqs2_rx_de-skew", 771 "cs0_dqs2p_tx_de-skew", 772 "cs0_dqs2n_tx_de-skew", 773 774 "cs0_dm3_rx_de-skew", 775 "cs0_dm3_tx_de-skew", 776 "cs0_dq24_rx_de-skew", 777 "cs0_dq24_tx_de-skew", 778 "cs0_dq25_rx_de-skew", 779 "cs0_dq25_tx_de-skew", 780 "cs0_dq26_rx_de-skew", 781 "cs0_dq26_tx_de-skew", 782 "cs0_dq27_rx_de-skew", 783 "cs0_dq27_tx_de-skew", 784 "cs0_dq28_rx_de-skew", 785 "cs0_dq28_tx_de-skew", 786 "cs0_dq29_rx_de-skew", 787 "cs0_dq29_tx_de-skew", 788 "cs0_dq30_rx_de-skew", 789 "cs0_dq30_tx_de-skew", 790 "cs0_dq31_rx_de-skew", 791 "cs0_dq31_tx_de-skew", 792 "cs0_dqs3_rx_de-skew", 793 "cs0_dqs3p_tx_de-skew", 794 "cs0_dqs3n_tx_de-skew", 795 }; 796 797 static const char * const rk3328_dts_cs1_timing[] = { 798 "cs1_dm0_rx_de-skew", 799 "cs1_dm0_tx_de-skew", 800 "cs1_dq0_rx_de-skew", 801 "cs1_dq0_tx_de-skew", 802 "cs1_dq1_rx_de-skew", 803 "cs1_dq1_tx_de-skew", 804 "cs1_dq2_rx_de-skew", 805 "cs1_dq2_tx_de-skew", 806 "cs1_dq3_rx_de-skew", 807 "cs1_dq3_tx_de-skew", 808 "cs1_dq4_rx_de-skew", 809 "cs1_dq4_tx_de-skew", 810 "cs1_dq5_rx_de-skew", 811 "cs1_dq5_tx_de-skew", 812 "cs1_dq6_rx_de-skew", 813 "cs1_dq6_tx_de-skew", 814 "cs1_dq7_rx_de-skew", 815 "cs1_dq7_tx_de-skew", 816 "cs1_dqs0_rx_de-skew", 817 "cs1_dqs0p_tx_de-skew", 818 "cs1_dqs0n_tx_de-skew", 819 820 "cs1_dm1_rx_de-skew", 821 "cs1_dm1_tx_de-skew", 822 "cs1_dq8_rx_de-skew", 823 "cs1_dq8_tx_de-skew", 824 "cs1_dq9_rx_de-skew", 825 "cs1_dq9_tx_de-skew", 826 "cs1_dq10_rx_de-skew", 827 "cs1_dq10_tx_de-skew", 828 "cs1_dq11_rx_de-skew", 829 "cs1_dq11_tx_de-skew", 830 "cs1_dq12_rx_de-skew", 831 "cs1_dq12_tx_de-skew", 832 "cs1_dq13_rx_de-skew", 833 "cs1_dq13_tx_de-skew", 834 "cs1_dq14_rx_de-skew", 835 "cs1_dq14_tx_de-skew", 836 "cs1_dq15_rx_de-skew", 837 "cs1_dq15_tx_de-skew", 838 "cs1_dqs1_rx_de-skew", 839 "cs1_dqs1p_tx_de-skew", 840 "cs1_dqs1n_tx_de-skew", 841 842 "cs1_dm2_rx_de-skew", 843 "cs1_dm2_tx_de-skew", 844 "cs1_dq16_rx_de-skew", 845 "cs1_dq16_tx_de-skew", 846 "cs1_dq17_rx_de-skew", 847 "cs1_dq17_tx_de-skew", 848 "cs1_dq18_rx_de-skew", 849 "cs1_dq18_tx_de-skew", 850 "cs1_dq19_rx_de-skew", 851 "cs1_dq19_tx_de-skew", 852 "cs1_dq20_rx_de-skew", 853 "cs1_dq20_tx_de-skew", 854 "cs1_dq21_rx_de-skew", 855 "cs1_dq21_tx_de-skew", 856 "cs1_dq22_rx_de-skew", 857 "cs1_dq22_tx_de-skew", 858 "cs1_dq23_rx_de-skew", 859 "cs1_dq23_tx_de-skew", 860 "cs1_dqs2_rx_de-skew", 861 "cs1_dqs2p_tx_de-skew", 862 "cs1_dqs2n_tx_de-skew", 863 864 "cs1_dm3_rx_de-skew", 865 "cs1_dm3_tx_de-skew", 866 "cs1_dq24_rx_de-skew", 867 "cs1_dq24_tx_de-skew", 868 "cs1_dq25_rx_de-skew", 869 "cs1_dq25_tx_de-skew", 870 "cs1_dq26_rx_de-skew", 871 "cs1_dq26_tx_de-skew", 872 "cs1_dq27_rx_de-skew", 873 "cs1_dq27_tx_de-skew", 874 "cs1_dq28_rx_de-skew", 875 "cs1_dq28_tx_de-skew", 876 "cs1_dq29_rx_de-skew", 877 "cs1_dq29_tx_de-skew", 878 "cs1_dq30_rx_de-skew", 879 "cs1_dq30_tx_de-skew", 880 "cs1_dq31_rx_de-skew", 881 "cs1_dq31_tx_de-skew", 882 "cs1_dqs3_rx_de-skew", 883 "cs1_dqs3p_tx_de-skew", 884 "cs1_dqs3n_tx_de-skew", 885 }; 886 887 struct rk3328_ddr_dts_config_timing { 888 unsigned int ddr3_speed_bin; 889 unsigned int ddr4_speed_bin; 890 unsigned int pd_idle; 891 unsigned int sr_idle; 892 unsigned int sr_mc_gate_idle; 893 unsigned int srpd_lite_idle; 894 unsigned int standby_idle; 895 896 unsigned int auto_pd_dis_freq; 897 unsigned int auto_sr_dis_freq; 898 /* for ddr3 only */ 899 unsigned int ddr3_dll_dis_freq; 900 /* for ddr4 only */ 901 unsigned int ddr4_dll_dis_freq; 902 unsigned int phy_dll_dis_freq; 903 904 unsigned int ddr3_odt_dis_freq; 905 unsigned int phy_ddr3_odt_dis_freq; 906 unsigned int ddr3_drv; 907 unsigned int ddr3_odt; 908 unsigned int phy_ddr3_ca_drv; 909 unsigned int phy_ddr3_ck_drv; 910 unsigned int phy_ddr3_dq_drv; 911 unsigned int phy_ddr3_odt; 912 913 unsigned int lpddr3_odt_dis_freq; 914 unsigned int phy_lpddr3_odt_dis_freq; 915 unsigned int lpddr3_drv; 916 unsigned int lpddr3_odt; 917 unsigned int phy_lpddr3_ca_drv; 918 unsigned int phy_lpddr3_ck_drv; 919 unsigned int phy_lpddr3_dq_drv; 920 unsigned int phy_lpddr3_odt; 921 922 unsigned int lpddr4_odt_dis_freq; 923 unsigned int phy_lpddr4_odt_dis_freq; 924 unsigned int lpddr4_drv; 925 unsigned int lpddr4_dq_odt; 926 unsigned int lpddr4_ca_odt; 927 unsigned int phy_lpddr4_ca_drv; 928 unsigned int phy_lpddr4_ck_cs_drv; 929 unsigned int phy_lpddr4_dq_drv; 930 unsigned int phy_lpddr4_odt; 931 932 unsigned int ddr4_odt_dis_freq; 933 unsigned int phy_ddr4_odt_dis_freq; 934 unsigned int ddr4_drv; 935 unsigned int ddr4_odt; 936 unsigned int phy_ddr4_ca_drv; 937 unsigned int phy_ddr4_ck_drv; 938 unsigned int phy_ddr4_dq_drv; 939 unsigned int phy_ddr4_odt; 940 941 unsigned int ca_skew[15]; 942 unsigned int cs0_skew[44]; 943 unsigned int cs1_skew[44]; 944 945 unsigned int available; 946 }; 947 948 struct rk3328_ddr_de_skew_setting { 949 unsigned int ca_de_skew[30]; 950 unsigned int cs0_de_skew[84]; 951 unsigned int cs1_de_skew[84]; 952 }; 953 954 struct rk3368_dram_timing { 955 u32 dram_spd_bin; 956 u32 sr_idle; 957 u32 pd_idle; 958 u32 dram_dll_dis_freq; 959 u32 phy_dll_dis_freq; 960 u32 dram_odt_dis_freq; 961 u32 phy_odt_dis_freq; 962 u32 ddr3_drv; 963 u32 ddr3_odt; 964 u32 lpddr3_drv; 965 u32 lpddr3_odt; 966 u32 lpddr2_drv; 967 u32 phy_clk_drv; 968 u32 phy_cmd_drv; 969 u32 phy_dqs_drv; 970 u32 phy_odt; 971 u32 ddr_2t; 972 }; 973 974 struct rk3399_dram_timing { 975 unsigned int ddr3_speed_bin; 976 unsigned int pd_idle; 977 unsigned int sr_idle; 978 unsigned int sr_mc_gate_idle; 979 unsigned int srpd_lite_idle; 980 unsigned int standby_idle; 981 unsigned int auto_lp_dis_freq; 982 unsigned int ddr3_dll_dis_freq; 983 unsigned int phy_dll_dis_freq; 984 unsigned int ddr3_odt_dis_freq; 985 unsigned int ddr3_drv; 986 unsigned int ddr3_odt; 987 unsigned int phy_ddr3_ca_drv; 988 unsigned int phy_ddr3_dq_drv; 989 unsigned int phy_ddr3_odt; 990 unsigned int lpddr3_odt_dis_freq; 991 unsigned int lpddr3_drv; 992 unsigned int lpddr3_odt; 993 unsigned int phy_lpddr3_ca_drv; 994 unsigned int phy_lpddr3_dq_drv; 995 unsigned int phy_lpddr3_odt; 996 unsigned int lpddr4_odt_dis_freq; 997 unsigned int lpddr4_drv; 998 unsigned int lpddr4_dq_odt; 999 unsigned int lpddr4_ca_odt; 1000 unsigned int phy_lpddr4_ca_drv; 1001 unsigned int phy_lpddr4_ck_cs_drv; 1002 unsigned int phy_lpddr4_dq_drv; 1003 unsigned int phy_lpddr4_odt; 1004 }; 1005 1006 /* name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew */ 1007 static const char * const rv1126_dts_ca_timing[] = { 1008 "a0_a3_a3_cke1-a_de-skew", 1009 "a1_ba1_null_cke0-b_de-skew", 1010 "a2_a9_a9_a4-a_de-skew", 1011 "a3_a15_null_a5-b_de-skew", 1012 "a4_a6_a6_ck-a_de-skew", 1013 "a5_a12_null_odt0-b_de-skew", 1014 "a6_ba2_null_a0-a_de-skew", 1015 "a7_a4_a4_odt0-a_de-skew", 1016 "a8_a1_a1_cke0-a_de-skew", 1017 "a9_a5_a5_a5-a_de-skew", 1018 "a10_a8_a8_clkb-a_de-skew", 1019 "a11_a7_a7_ca2-a_de-skew", 1020 "a12_rasn_null_ca1-a_de-skew", 1021 "a13_a13_null_ca3-a_de-skew", 1022 "a14_a14_null_csb1-b_de-skew", 1023 "a15_a10_null_ca0-b_de-skew", 1024 "a16_a11_null_csb0-b_de-skew", 1025 "a17_null_null_null_de-skew", 1026 "ba0_csb1_csb1_csb0-a_de-skew", 1027 "ba1_wen_null_cke1-b_de-skew", 1028 "bg0_odt1_odt1_csb1-a_de-skew", 1029 "bg1_a2_a2_odt1-a_de-skew", 1030 "cke0_casb_null_ca1-b_de-skew", 1031 "ck_ck_ck_ck-b_de-skew", 1032 "ckb_ckb_ckb_ckb-b_de-skew", 1033 "csb0_odt0_odt0_ca2-b_de-skew", 1034 "odt0_csb0_csb0_ca4-b_de-skew", 1035 "resetn_resetn_null-resetn_de-skew", 1036 "actn_cke_cke_ca3-b_de-skew", 1037 "cke1_null_null_null_de-skew", 1038 "csb1_ba0_null_null_de-skew", 1039 "odt1_a0_a0_odt1-b_de-skew", 1040 }; 1041 1042 static const char * const rv1126_dts_cs0_a_timing[] = { 1043 "cs0_dm0_rx_de-skew", 1044 "cs0_dq0_rx_de-skew", 1045 "cs0_dq1_rx_de-skew", 1046 "cs0_dq2_rx_de-skew", 1047 "cs0_dq3_rx_de-skew", 1048 "cs0_dq4_rx_de-skew", 1049 "cs0_dq5_rx_de-skew", 1050 "cs0_dq6_rx_de-skew", 1051 "cs0_dq7_rx_de-skew", 1052 "cs0_dqs0p_rx_de-skew", 1053 "cs0_dqs0n_rx_de-skew", 1054 "cs0_dm1_rx_de-skew", 1055 "cs0_dq8_rx_de-skew", 1056 "cs0_dq9_rx_de-skew", 1057 "cs0_dq10_rx_de-skew", 1058 "cs0_dq11_rx_de-skew", 1059 "cs0_dq12_rx_de-skew", 1060 "cs0_dq13_rx_de-skew", 1061 "cs0_dq14_rx_de-skew", 1062 "cs0_dq15_rx_de-skew", 1063 "cs0_dqs1p_rx_de-skew", 1064 "cs0_dqs1n_rx_de-skew", 1065 "cs0_dm0_tx_de-skew", 1066 "cs0_dq0_tx_de-skew", 1067 "cs0_dq1_tx_de-skew", 1068 "cs0_dq2_tx_de-skew", 1069 "cs0_dq3_tx_de-skew", 1070 "cs0_dq4_tx_de-skew", 1071 "cs0_dq5_tx_de-skew", 1072 "cs0_dq6_tx_de-skew", 1073 "cs0_dq7_tx_de-skew", 1074 "cs0_dqs0p_tx_de-skew", 1075 "cs0_dqs0n_tx_de-skew", 1076 "cs0_dm1_tx_de-skew", 1077 "cs0_dq8_tx_de-skew", 1078 "cs0_dq9_tx_de-skew", 1079 "cs0_dq10_tx_de-skew", 1080 "cs0_dq11_tx_de-skew", 1081 "cs0_dq12_tx_de-skew", 1082 "cs0_dq13_tx_de-skew", 1083 "cs0_dq14_tx_de-skew", 1084 "cs0_dq15_tx_de-skew", 1085 "cs0_dqs1p_tx_de-skew", 1086 "cs0_dqs1n_tx_de-skew", 1087 }; 1088 1089 static const char * const rv1126_dts_cs0_b_timing[] = { 1090 "cs0_dm2_rx_de-skew", 1091 "cs0_dq16_rx_de-skew", 1092 "cs0_dq17_rx_de-skew", 1093 "cs0_dq18_rx_de-skew", 1094 "cs0_dq19_rx_de-skew", 1095 "cs0_dq20_rx_de-skew", 1096 "cs0_dq21_rx_de-skew", 1097 "cs0_dq22_rx_de-skew", 1098 "cs0_dq23_rx_de-skew", 1099 "cs0_dqs2p_rx_de-skew", 1100 "cs0_dqs2n_rx_de-skew", 1101 "cs0_dm3_rx_de-skew", 1102 "cs0_dq24_rx_de-skew", 1103 "cs0_dq25_rx_de-skew", 1104 "cs0_dq26_rx_de-skew", 1105 "cs0_dq27_rx_de-skew", 1106 "cs0_dq28_rx_de-skew", 1107 "cs0_dq29_rx_de-skew", 1108 "cs0_dq30_rx_de-skew", 1109 "cs0_dq31_rx_de-skew", 1110 "cs0_dqs3p_rx_de-skew", 1111 "cs0_dqs3n_rx_de-skew", 1112 "cs0_dm2_tx_de-skew", 1113 "cs0_dq16_tx_de-skew", 1114 "cs0_dq17_tx_de-skew", 1115 "cs0_dq18_tx_de-skew", 1116 "cs0_dq19_tx_de-skew", 1117 "cs0_dq20_tx_de-skew", 1118 "cs0_dq21_tx_de-skew", 1119 "cs0_dq22_tx_de-skew", 1120 "cs0_dq23_tx_de-skew", 1121 "cs0_dqs2p_tx_de-skew", 1122 "cs0_dqs2n_tx_de-skew", 1123 "cs0_dm3_tx_de-skew", 1124 "cs0_dq24_tx_de-skew", 1125 "cs0_dq25_tx_de-skew", 1126 "cs0_dq26_tx_de-skew", 1127 "cs0_dq27_tx_de-skew", 1128 "cs0_dq28_tx_de-skew", 1129 "cs0_dq29_tx_de-skew", 1130 "cs0_dq30_tx_de-skew", 1131 "cs0_dq31_tx_de-skew", 1132 "cs0_dqs3p_tx_de-skew", 1133 "cs0_dqs3n_tx_de-skew", 1134 }; 1135 1136 static const char * const rv1126_dts_cs1_a_timing[] = { 1137 "cs1_dm0_rx_de-skew", 1138 "cs1_dq0_rx_de-skew", 1139 "cs1_dq1_rx_de-skew", 1140 "cs1_dq2_rx_de-skew", 1141 "cs1_dq3_rx_de-skew", 1142 "cs1_dq4_rx_de-skew", 1143 "cs1_dq5_rx_de-skew", 1144 "cs1_dq6_rx_de-skew", 1145 "cs1_dq7_rx_de-skew", 1146 "cs1_dqs0p_rx_de-skew", 1147 "cs1_dqs0n_rx_de-skew", 1148 "cs1_dm1_rx_de-skew", 1149 "cs1_dq8_rx_de-skew", 1150 "cs1_dq9_rx_de-skew", 1151 "cs1_dq10_rx_de-skew", 1152 "cs1_dq11_rx_de-skew", 1153 "cs1_dq12_rx_de-skew", 1154 "cs1_dq13_rx_de-skew", 1155 "cs1_dq14_rx_de-skew", 1156 "cs1_dq15_rx_de-skew", 1157 "cs1_dqs1p_rx_de-skew", 1158 "cs1_dqs1n_rx_de-skew", 1159 "cs1_dm0_tx_de-skew", 1160 "cs1_dq0_tx_de-skew", 1161 "cs1_dq1_tx_de-skew", 1162 "cs1_dq2_tx_de-skew", 1163 "cs1_dq3_tx_de-skew", 1164 "cs1_dq4_tx_de-skew", 1165 "cs1_dq5_tx_de-skew", 1166 "cs1_dq6_tx_de-skew", 1167 "cs1_dq7_tx_de-skew", 1168 "cs1_dqs0p_tx_de-skew", 1169 "cs1_dqs0n_tx_de-skew", 1170 "cs1_dm1_tx_de-skew", 1171 "cs1_dq8_tx_de-skew", 1172 "cs1_dq9_tx_de-skew", 1173 "cs1_dq10_tx_de-skew", 1174 "cs1_dq11_tx_de-skew", 1175 "cs1_dq12_tx_de-skew", 1176 "cs1_dq13_tx_de-skew", 1177 "cs1_dq14_tx_de-skew", 1178 "cs1_dq15_tx_de-skew", 1179 "cs1_dqs1p_tx_de-skew", 1180 "cs1_dqs1n_tx_de-skew", 1181 }; 1182 1183 static const char * const rv1126_dts_cs1_b_timing[] = { 1184 "cs1_dm2_rx_de-skew", 1185 "cs1_dq16_rx_de-skew", 1186 "cs1_dq17_rx_de-skew", 1187 "cs1_dq18_rx_de-skew", 1188 "cs1_dq19_rx_de-skew", 1189 "cs1_dq20_rx_de-skew", 1190 "cs1_dq21_rx_de-skew", 1191 "cs1_dq22_rx_de-skew", 1192 "cs1_dq23_rx_de-skew", 1193 "cs1_dqs2p_rx_de-skew", 1194 "cs1_dqs2n_rx_de-skew", 1195 "cs1_dm3_rx_de-skew", 1196 "cs1_dq24_rx_de-skew", 1197 "cs1_dq25_rx_de-skew", 1198 "cs1_dq26_rx_de-skew", 1199 "cs1_dq27_rx_de-skew", 1200 "cs1_dq28_rx_de-skew", 1201 "cs1_dq29_rx_de-skew", 1202 "cs1_dq30_rx_de-skew", 1203 "cs1_dq31_rx_de-skew", 1204 "cs1_dqs3p_rx_de-skew", 1205 "cs1_dqs3n_rx_de-skew", 1206 "cs1_dm2_tx_de-skew", 1207 "cs1_dq16_tx_de-skew", 1208 "cs1_dq17_tx_de-skew", 1209 "cs1_dq18_tx_de-skew", 1210 "cs1_dq19_tx_de-skew", 1211 "cs1_dq20_tx_de-skew", 1212 "cs1_dq21_tx_de-skew", 1213 "cs1_dq22_tx_de-skew", 1214 "cs1_dq23_tx_de-skew", 1215 "cs1_dqs2p_tx_de-skew", 1216 "cs1_dqs2n_tx_de-skew", 1217 "cs1_dm3_tx_de-skew", 1218 "cs1_dq24_tx_de-skew", 1219 "cs1_dq25_tx_de-skew", 1220 "cs1_dq26_tx_de-skew", 1221 "cs1_dq27_tx_de-skew", 1222 "cs1_dq28_tx_de-skew", 1223 "cs1_dq29_tx_de-skew", 1224 "cs1_dq30_tx_de-skew", 1225 "cs1_dq31_tx_de-skew", 1226 "cs1_dqs3p_tx_de-skew", 1227 "cs1_dqs3n_tx_de-skew", 1228 }; 1229 1230 #endif /* __ROCKCHIP_DMC_TIMING_H__ */ 1231 1232