1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __RKXX_PWM_REMOTECTL_H__ 4 #define __RKXX_PWM_REMOTECTL_H__ 5 #include <linux/input.h> 6 7 #define MAX_NUM_KEYS 60 8 #define PWM_PWR_KEY_CAPURURE_MAX 10 9 10 /* PWM0 registers */ 11 #define PWM_REG_CNTR 0x00 /* Counter Register */ 12 #define PWM_REG_HPR 0x04 /* Period Register */ 13 #define PWM_REG_LPR 0x08 /* Duty Cycle Register */ 14 #define PWM_REG_CTRL 0x0c /* Control Register */ 15 #define PWM3_REG_INTSTS 0x10 /* Interrupt Status Refister For Pwm3*/ 16 #define PWM2_REG_INTSTS 0x20 /* Interrupt Status Refister For Pwm2*/ 17 #define PWM1_REG_INTSTS 0x30 /* Interrupt Status Refister For Pwm1*/ 18 #define PWM0_REG_INTSTS 0x40 /* Interrupt Status Refister For Pwm0*/ 19 #define PWM3_REG_INT_EN 0x14 /* Interrupt Enable Refister For Pwm3*/ 20 #define PWM2_REG_INT_EN 0x24 /* Interrupt Enable Refister For Pwm2*/ 21 #define PWM1_REG_INT_EN 0x34 /* Interrupt Enable Refister For Pwm1*/ 22 #define PWM0_REG_INT_EN 0x44 /* Interrupt Enable Refister For Pwm0*/ 23 24 /*REG_CTRL bits definitions*/ 25 #define PWM_ENABLE (1 << 0) 26 #define PWM_DISABLE (0 << 0) 27 28 /*operation mode*/ 29 #define PWM_MODE_ONESHOT (0x00 << 1) 30 #define PWM_MODE_CONTINUMOUS (0x01 << 1) 31 #define PWM_MODE_CAPTURE (0x02 << 1) 32 33 /*duty cycle output polarity*/ 34 #define PWM_DUTY_POSTIVE (0x01 << 3) 35 #define PWM_DUTY_NEGATIVE (0x00 << 3) 36 37 /*incative state output polarity*/ 38 #define PWM_INACTIVE_POSTIVE (0x01 << 4) 39 #define PWM_INACTIVE_NEGATIVE (0x00 << 4) 40 41 /*clock source select*/ 42 #define PWM_CLK_SCALE (1 << 9) 43 #define PWM_CLK_NON_SCALE (0 << 9) 44 45 #define PWM_CH0_INT (1 << 0) 46 #define PWM_CH1_INT (1 << 1) 47 #define PWM_CH2_INT (1 << 2) 48 #define PWM_CH3_INT (1 << 3) 49 #define PWM_PWR_KEY_INT (1 << 7) 50 51 #define PWM_CH0_POL (1 << 8) 52 #define PWM_CH1_POL (1 << 9) 53 #define PWM_CH2_POL (1 << 10) 54 #define PWM_CH3_POL (1 << 11) 55 56 #define PWM_CH0_INT_ENABLE (1 << 0) 57 #define PWM_CH0_INT_DISABLE (0 << 0) 58 59 #define PWM_CH1_INT_ENABLE (1 << 1) 60 #define PWM_CH1_INT_DISABLE (0 << 1) 61 62 #define PWM_CH2_INT_ENABLE (1 << 2) 63 #define PWM_CH2_INT_DISABLE (0 << 2) 64 65 #define PWM_CH3_INT_ENABLE (1 << 3) 66 #define PWM_CH3_INT_DISABLE (0 << 3) 67 68 #define PWM_INT_ENABLE 1 69 #define PWM_INT_DISABLE 0 70 71 /*prescale factor*/ 72 #define PWMCR_MIN_PRESCALE 0x00 73 #define PWMCR_MAX_PRESCALE 0x07 74 75 #define PWMDCR_MIN_DUTY 0x0001 76 #define PWMDCR_MAX_DUTY 0xFFFF 77 78 #define PWMPCR_MIN_PERIOD 0x0001 79 #define PWMPCR_MAX_PERIOD 0xFFFF 80 81 #define PWMPCR_MIN_PERIOD 0x0001 82 #define PWMPCR_MAX_PERIOD 0xFFFF 83 84 85 enum pwm_div { 86 PWM_DIV1 = (0x0 << 12), 87 PWM_DIV2 = (0x1 << 12), 88 PWM_DIV4 = (0x2 << 12), 89 PWM_DIV8 = (0x3 << 12), 90 PWM_DIV16 = (0x4 << 12), 91 PWM_DIV32 = (0x5 << 12), 92 PWM_DIV64 = (0x6 << 12), 93 PWM_DIV128 = (0x7 << 12), 94 }; 95 96 /* NEC Protocol */ 97 #define RK_PWM_TIME_PRE_MIN 4000 98 #define RK_PWM_TIME_PRE_MAX 5000 99 100 #define RK_PWM_TIME_PRE_MIN_LOW 8000 101 #define RK_PWM_TIME_PRE_MAX_LOW 10000 102 103 #define RK_PWM_TIME_BIT0_MIN 390 104 #define RK_PWM_TIME_BIT0_MAX 730 105 106 #define RK_PWM_TIME_BIT1_MIN 1300 107 #define RK_PWM_TIME_BIT1_MAX 2000 108 109 #define RK_PWM_TIME_BIT_MIN_LOW 390 110 #define RK_PWM_TIME_BIT_MAX_LOW 730 111 112 #define RK_PWM_TIME_RPT_MIN 2000 113 #define RK_PWM_TIME_RPT_MAX 2500 114 115 #define RK_PWM_TIME_SEQ1_MIN 95000 116 #define RK_PWM_TIME_SEQ1_MAX 98000 117 118 #define RK_PWM_TIME_SEQ2_MIN 30000 119 #define RK_PWM_TIME_SEQ2_MAX 55000 120 121 122 #define PWM_REG_INTSTS(n) ((3 - (n)) * 0x10 + 0x10) 123 #define PWM_REG_INT_EN(n) ((3 - (n)) * 0x10 + 0x14) 124 #define RK_PWM_VERSION_ID(n) ((3 - (n)) * 0x10 + 0x2c) 125 #define PWM_REG_PWRMATCH_CTRL(n) ((3 - (n)) * 0x10 + 0x50) 126 #define PWM_REG_PWRMATCH_LPRE(n) ((3 - (n)) * 0x10 + 0x54) 127 #define PWM_REG_PWRMATCH_HPRE(n) ((3 - (n)) * 0x10 + 0x58) 128 #define PWM_REG_PWRMATCH_LD(n) ((3 - (n)) * 0x10 + 0x5C) 129 #define PWM_REG_PWRMATCH_HD_ZERO(n) ((3 - (n)) * 0x10 + 0x60) 130 #define PWM_REG_PWRMATCH_HD_ONE(n) ((3 - (n)) * 0x10 + 0x64) 131 #define PWM_PWRMATCH_VALUE(n) ((3 - (n)) * 0x10 + 0x68) 132 #define PWM_PWRCAPTURE_VALUE(n) ((3 - (n)) * 0x10 + 0x9c) 133 134 #define PWM_CH_INT(n) BIT(n) 135 #define PWM_CH_POL(n) BIT(n+8) 136 137 #define PWM_CH_INT_ENABLE(n) BIT(n) 138 #define PWM_PWR_INT_ENABLE BIT(7) 139 #define CH3_PWRKEY_ENABLE BIT(3) 140 141 142 143 144 typedef enum _RMC_STATE { 145 RMC_IDLE, 146 RMC_PRELOAD, 147 RMC_USERCODE, 148 RMC_GETDATA, 149 RMC_SEQUENCE, 150 } eRMC_STATE; 151 152 153 struct RKxx_remotectl_platform_data { 154 int nbuttons; 155 int rep; 156 int timer; 157 int wakeup; 158 }; 159 160 #endif 161