1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #ifndef _RK628_CGU_H 9 #define _RK628_CGU_H 10 11 #define CGU_CLK_CPLL 1 12 #define CGU_CLK_GPLL 2 13 #define CGU_CLK_CPLL_MUX 3 14 #define CGU_CLK_GPLL_MUX 4 15 #define CGU_PCLK_GPIO0 5 16 #define CGU_PCLK_GPIO1 6 17 #define CGU_PCLK_GPIO2 7 18 #define CGU_PCLK_GPIO3 8 19 #define CGU_PCLK_TXPHY_CON 9 20 #define CGU_PCLK_EFUSE 10 21 #define CGU_PCLK_DSI0 11 22 #define CGU_PCLK_DSI1 12 23 #define CGU_PCLK_CSI 13 24 #define CGU_PCLK_HDMITX 14 25 #define CGU_PCLK_RXPHY 15 26 #define CGU_PCLK_HDMIRX 16 27 #define CGU_PCLK_DPRX 17 28 #define CGU_PCLK_GVIHOST 18 29 #define CGU_CLK_CFG_DPHY0 19 30 #define CGU_CLK_CFG_DPHY1 20 31 #define CGU_CLK_TXESC 21 32 #define CGU_CLK_DPRX_VID 22 33 #define CGU_CLK_IMODET 23 34 #define CGU_CLK_HDMIRX_AUD 24 35 #define CGU_CLK_HDMIRX_CEC 25 36 #define CGU_CLK_RX_READ 26 37 #define CGU_SCLK_VOP 27 38 #define CGU_PCLK_LOGIC 28 39 #define CGU_CLK_GPIO_DB0 29 40 #define CGU_CLK_GPIO_DB1 30 41 #define CGU_CLK_GPIO_DB2 31 42 #define CGU_CLK_GPIO_DB3 32 43 #define CGU_CLK_I2S_8CH_SRC 33 44 #define CGU_CLK_I2S_8CH_FRAC 34 45 #define CGU_MCLK_I2S_8CH 35 46 #define CGU_I2S_MCLKOUT 36 47 #define CGU_BT1120DEC 37 48 #define CGU_CLK_TESTOUT 38 49 #define CGU_NR_CLKS 39 50 51 #endif 52