1 /* 2 * Copyright (c) 2021 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __STM32MP1_PWM_H__ 17 #define __STM32MP1_PWM_H__ 18 19 #include "stm32mp1xx_hal.h" 20 #include "stm32mp1xx_hal_tim.h" 21 #include "device_resource_if.h" 22 #include "hdf_device_desc.h" 23 #include "hdf_log.h" 24 #include "hdf_base.h" 25 #include "osal_io.h" 26 #include "osal_mem.h" 27 #include "osal_time.h" 28 #include "pwm_core.h" 29 30 #ifdef __cplusplus 31 #if __cplusplus 32 { 33 #endif /* __cplusplus */ 34 #endif /* __cplusplus */ 35 36 #define PWM_DEFAULT_PSC (209 - 1) 37 #define PWM_DEFAULT_TICK 1000 38 39 #define PWM_DEFAULT_PERIOD (500 - 1) 40 #define PWM_DEFAULT_DUTY_CYCLE (250 - 1) 41 42 struct Mp1xxPwmRegs { 43 volatile uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 44 volatile uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 45 volatile uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 46 volatile uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 47 volatile uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 48 volatile uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 49 volatile uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 50 volatile uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 51 volatile uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 52 volatile uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 53 volatile uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 54 volatile uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 55 volatile uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 56 volatile uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 57 volatile uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 58 volatile uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 59 volatile uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 60 volatile uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 61 volatile uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 62 volatile uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 63 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ 64 volatile uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 65 volatile uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 66 volatile uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ 67 volatile uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ 68 volatile uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ 69 volatile uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ 70 uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ 71 volatile uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ 72 volatile uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ 73 volatile uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ 74 }; 75 76 enum gpioPort { 77 GPIO_A = 0, 78 GPIO_B = 1, 79 GPIO_C = 2, 80 GPIO_D = 3, 81 GPIO_E = 4, 82 GPIO_F = 5, 83 GPIO_G = 6, 84 GPIO_H = 7, 85 GPIO_I = 8, 86 GPIO_J = 9, 87 GPIO_K = 10, 88 GPIO_Z = 11, 89 }; 90 91 enum timNum { 92 TIM_1 = 1, 93 TIM_2 = 2, 94 TIM_3 = 3, 95 TIM_4 = 4, 96 TIM_5 = 5, 97 TIM_8 = 8, 98 TIM_12 = 12, 99 TIM_13 = 13, 100 TIM_14 = 14, 101 TIM_15 = 15, 102 TIM_16 = 16, 103 TIM_17 = 17, 104 }; 105 106 #ifdef __cplusplus 107 #if __cplusplus 108 } 109 #endif /* __cplusplus */ 110 #endif /* __cplusplus */ 111 112 #endif 113