1 /* 2 * Copyright (c) 2021 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __STM32MP1_SPI_H__ 17 #define __STM32MP1_SPI_H__ 18 19 #include "osal_sem.h" 20 #include "spi_core.h" 21 22 #ifdef __cplusplus 23 #if __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 #endif /* __cplusplus */ 27 28 #define MP1XX_SPI2S_CR1_OFFSET 0x00 29 #define MP1XX_SPI_CR2_OFFSET 0x04 30 #define MP1XX_SPI_CFG1_OFFSET 0x08 31 #define MP1XX_SPI_CFG2_OFFSET 0x0C 32 #define MP1XX_SPI2S_IER_OFFSET 0x10 33 #define MP1XX_SPI2S_SR_OFFSET 0x14 34 #define MP1XX_SPI2S_IFCR_OFFSET 0x18 35 #define MP1XX_SPI2S_TXDR_OFFSET 0x20 36 #define MP1XX_SPI2S_RXDR_OFFSET 0x30 37 #define MP1XX_SPI_CRCPOLY_OFFSET 0x40 38 #define MP1XX_SPI_TXCRC_OFFSET 0x44 39 #define MP1XX_SPI_RXCRC_OFFSET 0x48 40 #define MP1XX_SPI_UDRDR_OFFSET 0x4C 41 #define MP1XX_SPI2S_CFGR_OFFSET 0x50 42 #define MP1XX_SPI2S_HWCFGR_OFFSET 0x3F0 43 #define MP1XX_SPI2S_VERR_OFFSET 0x3F4 44 #define MP1XX_SPI2S_IPIDR_OFFSET 0x3F8 45 #define MP1XX_SPI2S_SIDR_OFFSET 0x3FC 46 47 #define MP1XX_SPI_CS_SHIFT 12 48 #define MP1XX_SPI_CS (0x1U << MP1XX_SPI_CS_SHIFT) 49 #define MP1XX_SPI_SSI_SITFT 12 50 #define MP1XX_SPI_SSI (0x1U << MP1XX_SPI_SSI_SITFT) 51 #define MP1XX_SPI_MBR_SHIFT 28 52 #define MP1XX_SPI_MBR_MAX 0x7U 53 #define MP1XX_SPI_MBR_MASK (MP1XX_SPI_MBR_MAX << MP1XX_SPI_MBR_SHIFT) 54 #define MP1XX_SPI_SSM_SHIFT 26 55 #define MP1XX_SPI_SSM (0x1U << MP1XX_SPI_SSM_SHIFT) 56 #define MP1XX_SPI_CPOL_SHIFT 25 57 #define MP1XX_SPI_CPOL (0x1U << MP1XX_SPI_CPOL_SHIFT) 58 #define MP1XX_SPI_CPHA_SHIFT 24 59 #define MP1XX_SPI_CPHA (0x1U << MP1XX_SPI_CPHA_SHIFT) 60 #define MP1XX_SPI_LSBFRST_SHIFT 23 61 #define MP1XX_SPI_LSBFRST (0x1U << MP1XX_SPI_LSBFRST_SHIFT) 62 #define MP1XX_SPI_MASTER_SHIFT 22 63 #define MP1XX_SPI_MASTER (0x1U << MP1XX_SPI_MASTER_SHIFT) 64 #define MP1XX_SPI_COMM_SHIFT 17 65 #define MP1XX_SPI_COMM_MASK (0x3U << MP1XX_SPI_COMM_SHIFT) 66 #define MP1XX_SPI_HALF_DUPLEX_MODE 0x3U 67 #define MP1XX_SPI_FTHLV_SHIFT 5 68 #define MP1XX_SPI_FTHLV_MASK (0xFU << MP1XX_SPI_FTHLV_SHIFT) 69 #define MP1XX_SPI_DSIZE_MASK 0x1FU 70 #define MP1XX_SPI_DSIZE_MASK 0x1FU 71 #define MP1XX_SPI_FIFO_MASK 0xFU 72 #define MP1XX_SPI_RXFCFG_SHIFT 4 73 #define MP1XX_SPI_CSTART_MASK (0x1U << 9) 74 #define MP1XX_SPI_SR_TXP_MASK (0x1U << 1) 75 #define MP1XX_SPI_SR_RXP_MASK 0x1U 76 #define MP1XX_SPI_SR_TXTF_MASK 0x1U 77 #define MP1XX_SPI_MODF_MASK (0x1U << 9) 78 #define MP1XX_SPI_SSOE_MASK (0x1U << 29) 79 80 #define MP1XX_SPI2S_FIFO_SIZE 0x5 // 32 bytes 81 #define MP1XX_SPI_MAX_SPEED 50000000 82 #define MP1XX_SPI_MAX_CLK_DIV 128 83 #define MP1XX_SPI_MIN_CLK_DIV 16 84 #define BITS_PER_WORD_MIN 4 85 #define BITS_PER_WORD_EIGHT 8 86 #define BITS_PER_WORD_MAX 16 87 #define MAX_WAIT 10000 88 #define SPI_MAX_LEVEL 8 89 #define DEFAULT_SPEED 2000000 90 #define SPI_CS_ACTIVE 0 91 #define SPI_CS_INACTIVE 1 92 93 #define MP1XX_AHB4_GPIO_BASE 0x50002000 94 #define MP1XX_AHB5_GPIOZ_BASE 0x54004000 95 #define MP1XX_GPIOZ 25 96 #define MP1XX_GPIO_MODE_REG 0x0 97 #define MP1XX_GPIO_AF_LOW_REG 0x20 98 #define MP1XX_GPIO_AF_HIGH_REG 0x24 99 #define MP1XX_GPIO_MODE_BITS 2 100 #define MP1XX_MODER_MASK 0x3 101 #define MP1XX_GPIO_AF_BITS 4 102 #define MP1XX_GPIO_AF_MASK 0xF 103 #define MP1XX_GPIOZ 25 104 #define MP1XX_GPIO_GROUP_STEP 0x1000 105 #define MP1XX_GPIO_REG_SIZE 0x400 106 #define MP1XX_GPIO_GROUP_NUM 11 107 #define MP1XX_SPI_PIN_NUM 4 108 #define MP1XX_MEMBER_PER_PIN 3 109 #define MP1XX_PIN_AF_MODE 0x2 110 #define MP1XX_PIN_NUM_PER_AF_REG 8 111 #define SPI_ALL_IRQ_DISABLE 0x0 112 #define SPI_ALL_IRQ_ENABLE 0x205 113 #define SPI_RX_INTR_MASK 0x1 114 #define SPI_ALL_IRQ_CLEAR 0xFF8 115 116 enum busNum { 117 SPI_1 = 1, 118 SPI_2 = 2, 119 SPI_3 = 3, 120 SPI_4 = 4, 121 SPI_5 = 5, 122 SPI_6 = 6, 123 }; 124 125 enum busModeSel { 126 SPI2S_DISABLED = 0, 127 SPI2S_SPI_MODE = 1, 128 SPI2S_I2S_MODE = 2, 129 }; 130 131 enum pinArray { 132 PIN_GROUP = 0, 133 PIN_NUM = 1, 134 PIN_AF = 2, 135 }; 136 137 struct Mp1xxSpiCntlr { 138 struct SpiCntlr *cntlr; 139 struct DListHead deviceList; 140 struct OsalSem sem; 141 volatile unsigned char *regBase; 142 uint32_t irqNum; 143 uint32_t busNum; 144 uint32_t numCs; 145 uint32_t curCs; 146 uint32_t speed; 147 uint32_t fifoSize; 148 uint32_t clkRate; 149 uint32_t maxSpeedHz; 150 uint32_t minSpeedHz; 151 uint32_t busModeSel; 152 uint8_t pins[MP1XX_SPI_PIN_NUM * MP1XX_MEMBER_PER_PIN]; 153 uint16_t mode; 154 uint8_t bitsPerWord; 155 uint8_t transferMode; 156 }; 157 158 #ifdef __cplusplus 159 #if __cplusplus 160 } 161 #endif /* __cplusplus */ 162 #endif /* __cplusplus */ 163 164 #endif /* __STM32MP1_ADC_H__ */ 165