1 /**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @version V1.4.0
6 * @date 04-August-2014
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 * This file contains the system clock configuration for STM32F4xx devices.
9 *
10 * 1. This file provides two functions and one global variable to be called from
11 * user application:
12 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
13 * and Divider factors, AHB/APBx prescalers and Flash settings),
14 * depending on the configuration made in the clock xls tool.
15 * This function is called at startup just after reset and
16 * before branch to main program. This call is made inside
17 * the "startup_stm32f4xx.s" file.
18 *
19 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
20 * by the user application to setup the SysTick
21 * timer or configure other parameters.
22 *
23 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
24 * be called whenever the core clock is changed
25 * during program execution.
26 *
27 * 2. After each device reset the HSI (16 MHz) is used as system clock source.
28 * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
29 * configure the system clock before to branch to main program.
30 *
31 * 3. If the system clock source selected by user fails to startup, the SystemInit()
32 * function will do nothing and HSI still used as system clock source. User can
33 * add some code to deal with this issue inside the SetSysClock() function.
34 *
35 * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
36 * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
37 * through PLL, and you are using different crystal you have to adapt the HSE
38 * value to your own configuration.
39 *
40 * 5. This file configures the system clock as follows:
41 *=============================================================================
42 *=============================================================================
43 * Supported STM32F40xxx/41xxx devices
44 *-----------------------------------------------------------------------------
45 * System Clock source | PLL (HSE)
46 *-----------------------------------------------------------------------------
47 * SYSCLK(Hz) | 168000000
48 *-----------------------------------------------------------------------------
49 * HCLK(Hz) | 168000000
50 *-----------------------------------------------------------------------------
51 * AHB Prescaler | 1
52 *-----------------------------------------------------------------------------
53 * APB1 Prescaler | 4
54 *-----------------------------------------------------------------------------
55 * APB2 Prescaler | 2
56 *-----------------------------------------------------------------------------
57 * HSE Frequency(Hz) | 25000000
58 *-----------------------------------------------------------------------------
59 * PLL_M | 25
60 *-----------------------------------------------------------------------------
61 * PLL_N | 336
62 *-----------------------------------------------------------------------------
63 * PLL_P | 2
64 *-----------------------------------------------------------------------------
65 * PLL_Q | 7
66 *-----------------------------------------------------------------------------
67 * PLLI2S_N | NA
68 *-----------------------------------------------------------------------------
69 * PLLI2S_R | NA
70 *-----------------------------------------------------------------------------
71 * I2S input clock | NA
72 *-----------------------------------------------------------------------------
73 * VDD(V) | 3.3
74 *-----------------------------------------------------------------------------
75 * Main regulator output voltage | Scale1 mode
76 *-----------------------------------------------------------------------------
77 * Flash Latency(WS) | 5
78 *-----------------------------------------------------------------------------
79 * Prefetch Buffer | ON
80 *-----------------------------------------------------------------------------
81 * Instruction cache | ON
82 *-----------------------------------------------------------------------------
83 * Data cache | ON
84 *-----------------------------------------------------------------------------
85 * Require 48MHz for USB OTG FS, | Disabled
86 * SDIO and RNG clock |
87 *-----------------------------------------------------------------------------
88 *=============================================================================
89 *=============================================================================
90 * Supported STM32F42xxx/43xxx devices
91 *-----------------------------------------------------------------------------
92 * System Clock source | PLL (HSE)
93 *-----------------------------------------------------------------------------
94 * SYSCLK(Hz) | 180000000
95 *-----------------------------------------------------------------------------
96 * HCLK(Hz) | 180000000
97 *-----------------------------------------------------------------------------
98 * AHB Prescaler | 1
99 *-----------------------------------------------------------------------------
100 * APB1 Prescaler | 4
101 *-----------------------------------------------------------------------------
102 * APB2 Prescaler | 2
103 *-----------------------------------------------------------------------------
104 * HSE Frequency(Hz) | 25000000
105 *-----------------------------------------------------------------------------
106 * PLL_M | 25
107 *-----------------------------------------------------------------------------
108 * PLL_N | 360
109 *-----------------------------------------------------------------------------
110 * PLL_P | 2
111 *-----------------------------------------------------------------------------
112 * PLL_Q | 7
113 *-----------------------------------------------------------------------------
114 * PLLI2S_N | NA
115 *-----------------------------------------------------------------------------
116 * PLLI2S_R | NA
117 *-----------------------------------------------------------------------------
118 * I2S input clock | NA
119 *-----------------------------------------------------------------------------
120 * VDD(V) | 3.3
121 *-----------------------------------------------------------------------------
122 * Main regulator output voltage | Scale1 mode
123 *-----------------------------------------------------------------------------
124 * Flash Latency(WS) | 5
125 *-----------------------------------------------------------------------------
126 * Prefetch Buffer | ON
127 *-----------------------------------------------------------------------------
128 * Instruction cache | ON
129 *-----------------------------------------------------------------------------
130 * Data cache | ON
131 *-----------------------------------------------------------------------------
132 * Require 48MHz for USB OTG FS, | Disabled
133 * SDIO and RNG clock |
134 *-----------------------------------------------------------------------------
135 *=============================================================================
136 *=============================================================================
137 * Supported STM32F401xx devices
138 *-----------------------------------------------------------------------------
139 * System Clock source | PLL (HSE)
140 *-----------------------------------------------------------------------------
141 * SYSCLK(Hz) | 84000000
142 *-----------------------------------------------------------------------------
143 * HCLK(Hz) | 84000000
144 *-----------------------------------------------------------------------------
145 * AHB Prescaler | 1
146 *-----------------------------------------------------------------------------
147 * APB1 Prescaler | 2
148 *-----------------------------------------------------------------------------
149 * APB2 Prescaler | 1
150 *-----------------------------------------------------------------------------
151 * HSE Frequency(Hz) | 25000000
152 *-----------------------------------------------------------------------------
153 * PLL_M | 25
154 *-----------------------------------------------------------------------------
155 * PLL_N | 336
156 *-----------------------------------------------------------------------------
157 * PLL_P | 4
158 *-----------------------------------------------------------------------------
159 * PLL_Q | 7
160 *-----------------------------------------------------------------------------
161 * PLLI2S_N | NA
162 *-----------------------------------------------------------------------------
163 * PLLI2S_R | NA
164 *-----------------------------------------------------------------------------
165 * I2S input clock | NA
166 *-----------------------------------------------------------------------------
167 * VDD(V) | 3.3
168 *-----------------------------------------------------------------------------
169 * Main regulator output voltage | Scale1 mode
170 *-----------------------------------------------------------------------------
171 * Flash Latency(WS) | 2
172 *-----------------------------------------------------------------------------
173 * Prefetch Buffer | ON
174 *-----------------------------------------------------------------------------
175 * Instruction cache | ON
176 *-----------------------------------------------------------------------------
177 * Data cache | ON
178 *-----------------------------------------------------------------------------
179 * Require 48MHz for USB OTG FS, | Disabled
180 * SDIO and RNG clock |
181 *-----------------------------------------------------------------------------
182 *=============================================================================
183 *=============================================================================
184 * Supported STM32F411xx devices
185 *-----------------------------------------------------------------------------
186 * System Clock source | PLL (HSI)
187 *-----------------------------------------------------------------------------
188 * SYSCLK(Hz) | 100000000
189 *-----------------------------------------------------------------------------
190 * HCLK(Hz) | 100000000
191 *-----------------------------------------------------------------------------
192 * AHB Prescaler | 1
193 *-----------------------------------------------------------------------------
194 * APB1 Prescaler | 2
195 *-----------------------------------------------------------------------------
196 * APB2 Prescaler | 1
197 *-----------------------------------------------------------------------------
198 * HSI Frequency(Hz) | 16000000
199 *-----------------------------------------------------------------------------
200 * PLL_M | 16
201 *-----------------------------------------------------------------------------
202 * PLL_N | 400
203 *-----------------------------------------------------------------------------
204 * PLL_P | 4
205 *-----------------------------------------------------------------------------
206 * PLL_Q | 7
207 *-----------------------------------------------------------------------------
208 * PLLI2S_N | NA
209 *-----------------------------------------------------------------------------
210 * PLLI2S_R | NA
211 *-----------------------------------------------------------------------------
212 * I2S input clock | NA
213 *-----------------------------------------------------------------------------
214 * VDD(V) | 3.3
215 *-----------------------------------------------------------------------------
216 * Main regulator output voltage | Scale1 mode
217 *-----------------------------------------------------------------------------
218 * Flash Latency(WS) | 3
219 *-----------------------------------------------------------------------------
220 * Prefetch Buffer | ON
221 *-----------------------------------------------------------------------------
222 * Instruction cache | ON
223 *-----------------------------------------------------------------------------
224 * Data cache | ON
225 *-----------------------------------------------------------------------------
226 * Require 48MHz for USB OTG FS, | Disabled
227 * SDIO and RNG clock |
228 *-----------------------------------------------------------------------------
229 *=============================================================================
230 ******************************************************************************
231 * @attention
232 *
233 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
234 *
235 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
236 * You may not use this file except in compliance with the License.
237 * You may obtain a copy of the License at:
238 *
239 * http://www.st.com/software_license_agreement_liberty_v2
240 *
241 * Unless required by applicable law or agreed to in writing, software
242 * distributed under the License is distributed on an "AS IS" BASIS,
243 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
244 * See the License for the specific language governing permissions and
245 * limitations under the License.
246 *
247 ******************************************************************************
248 */
249
250 /** @addtogroup CMSIS
251 * @{
252 */
253
254 /** @addtogroup stm32f4xx_system
255 * @{
256 */
257
258 /** @addtogroup STM32F4xx_System_Private_Includes
259 * @{
260 */
261
262 #include "stm32f4xx.h"
263
264 /**
265 * @}
266 */
267
268 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
269 * @{
270 */
271
272 /**
273 * @}
274 */
275
276 /** @addtogroup STM32F4xx_System_Private_Defines
277 * @{
278 */
279
280 /************************* Miscellaneous Configuration ************************/
281 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
282 on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */
283 #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
284 /* #define DATA_IN_ExtSRAM */
285 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
286
287 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
288 /* #define DATA_IN_ExtSDRAM */
289 #endif /* STM32F427_437x || STM32F429_439xx */
290
291 #if defined (STM32F411xE)
292 /*!< Uncomment the following line if you need to clock the STM32F411xE by HSE Bypass
293 through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
294 and is fixed at 8 MHz.
295 Hardware configuration needed for Nucleo Board:
296 ?SB54, SB55 OFF
297 ?R35 removed
298 ?SB16, SB50 ON */
299 /* #define USE_HSE_BYPASS */
300
301 #if defined (USE_HSE_BYPASS)
302 #define HSE_BYPASS_INPUT_FREQUENCY 8000000
303 #endif /* USE_HSE_BYPASS */
304 #endif /* STM32F411xE */
305
306 /*!< Uncomment the following line if you need to relocate your vector Table in
307 Internal SRAM. */
308 /* #define VECT_TAB_SRAM */
309 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
310 This value must be a multiple of 0x200. */
311 /******************************************************************************/
312
313 /************************* PLL Parameters *************************************/
314 #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
315 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
316 #define PLL_M 8
317 #else /* STM32F411xE */
318 #if defined (USE_HSE_BYPASS)
319 #define PLL_M 8
320 #else /* STM32F411xE */
321 #define PLL_M 16
322 #endif /* USE_HSE_BYPASS */
323 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
324
325 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
326 #define PLL_Q 7
327
328 #if defined (STM32F40_41xxx)
329 #define PLL_N 336
330 /* SYSCLK = PLL_VCO / PLL_P */
331 #define PLL_P 2
332 #endif /* STM32F40_41xxx */
333
334 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
335 #define PLL_N 360
336 /* SYSCLK = PLL_VCO / PLL_P */
337 #define PLL_P 2
338 #endif /* STM32F427_437x || STM32F429_439xx */
339
340 #if defined (STM32F401xx)
341 #define PLL_N 336
342 /* SYSCLK = PLL_VCO / PLL_P */
343 #define PLL_P 4
344 #endif /* STM32F401xx */
345
346 #if defined (STM32F411xE)
347 #define PLL_N 400
348 /* SYSCLK = PLL_VCO / PLL_P */
349 #define PLL_P 4
350 #endif /* STM32F411xx */
351
352 /******************************************************************************/
353
354 /**
355 * @}
356 */
357
358 /** @addtogroup STM32F4xx_System_Private_Macros
359 * @{
360 */
361
362 /**
363 * @}
364 */
365
366 /** @addtogroup STM32F4xx_System_Private_Variables
367 * @{
368 */
369
370 #if defined (STM32F40_41xxx)
371 uint32_t SystemCoreClock = 168000000;
372 #endif /* STM32F40_41xxx */
373
374 // #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
375 // uint32_t SystemCoreClock = 180000000;
376 // #endif /* STM32F427_437x || STM32F429_439xx */
377
378 // #if defined (STM32F401xx)
379 // uint32_t SystemCoreClock = 84000000;
380 // #endif /* STM32F401xx */
381
382 // #if defined (STM32F411xE)
383 // uint32_t SystemCoreClock = 100000000;
384 // #endif /* STM32F401xx */
385
386 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
387
388 /**
389 * @}
390 */
391
392 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
393 * @{
394 */
395
396 static void SetSysClock(void);
397
398 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
399 static void SystemInit_ExtMemCtl(void);
400 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
401
402 /**
403 * @}
404 */
405
406 /** @addtogroup STM32F4xx_System_Private_Functions
407 * @{
408 */
409
410 /**
411 * @brief Setup the microcontroller system
412 * Initialize the Embedded Flash Interface, the PLL and update the
413 * SystemFrequency variable.
414 * @param None
415 * @retval None
416 */
SystemInit(void)417 void SystemInit(void)
418 {
419 /* FPU settings ------------------------------------------------------------*/
420 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
421 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
422 #endif
423 /* Reset the RCC clock configuration to the default reset state ------------*/
424 /* Set HSION bit */
425 RCC->CR |= (uint32_t)0x00000001;
426
427 /* Reset CFGR register */
428 RCC->CFGR = 0x00000000;
429
430 /* Reset HSEON, CSSON and PLLON bits */
431 RCC->CR &= (uint32_t)0xFEF6FFFF;
432
433 /* Reset PLLCFGR register */
434 RCC->PLLCFGR = 0x24003010;
435
436 /* Reset HSEBYP bit */
437 RCC->CR &= (uint32_t)0xFFFBFFFF;
438
439 /* Disable all interrupts */
440 RCC->CIR = 0x00000000;
441
442 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
443 SystemInit_ExtMemCtl();
444 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
445
446 /* Configure the System clock source, PLL Multiplier and Divider factors,
447 AHB/APBx prescalers and Flash settings ----------------------------------*/
448 SetSysClock();
449
450 /* Configure the Vector Table location add offset address ------------------*/
451 #ifdef VECT_TAB_SRAM
452 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
453 #else
454 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
455 #endif
456 }
457
458 /**
459 * @brief Update SystemCoreClock variable according to Clock Register Values.
460 * The SystemCoreClock variable contains the core clock (HCLK), it can
461 * be used by the user application to setup the SysTick timer or configure
462 * other parameters.
463 *
464 * @note Each time the core clock (HCLK) changes, this function must be called
465 * to update SystemCoreClock variable value. Otherwise, any configuration
466 * based on this variable will be incorrect.
467 *
468 * @note - The system frequency computed by this function is not the real
469 * frequency in the chip. It is calculated based on the predefined
470 * constant and the selected clock source:
471 *
472 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
473 *
474 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
475 *
476 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
477 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
478 *
479 * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
480 * 16 MHz) but the real value may vary depending on the variations
481 * in voltage and temperature.
482 *
483 * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
484 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
485 * frequency of the crystal used. Otherwise, this function may
486 * have wrong result.
487 *
488 * - The result of this function could be not correct when using fractional
489 * value for HSE crystal.
490 *
491 * @param None
492 * @retval None
493 */
SystemCoreClockUpdate(void)494 void SystemCoreClockUpdate(void)
495 {
496 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
497
498 /* Get SYSCLK source -------------------------------------------------------*/
499 tmp = RCC->CFGR & RCC_CFGR_SWS;
500
501 switch (tmp)
502 {
503 case 0x00: /* HSI used as system clock source */
504 SystemCoreClock = HSI_VALUE;
505 break;
506 case 0x04: /* HSE used as system clock source */
507 SystemCoreClock = HSE_VALUE;
508 break;
509 case 0x08: /* PLL used as system clock source */
510 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
511 SYSCLK = PLL_VCO / PLL_P
512 */
513 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
514 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
515
516 #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
517 if (pllsource != 0)
518 {
519 /* HSE used as PLL clock source */
520 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
521 }
522 else
523 {
524 /* HSI used as PLL clock source */
525 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
526 }
527 #elif defined (STM32F411xE)
528 #if defined (USE_HSE_BYPASS)
529 if (pllsource != 0)
530 {
531 /* HSE used as PLL clock source */
532 pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
533 }
534 #else
535 if (pllsource == 0)
536 {
537 /* HSI used as PLL clock source */
538 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
539 }
540 #endif /* USE_HSE_BYPASS */
541 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
542 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
543 SystemCoreClock = pllvco/pllp;
544 break;
545 default:
546 SystemCoreClock = HSI_VALUE;
547 break;
548 }
549 /* Compute HCLK frequency --------------------------------------------------*/
550 /* Get HCLK prescaler */
551 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
552 /* HCLK frequency */
553 SystemCoreClock >>= tmp;
554 }
555
556 /**
557 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
558 * AHB/APBx prescalers and Flash settings
559 * @Note This function should be called only once the RCC clock configuration
560 * is reset to the default reset state (done in SystemInit() function).
561 * @param None
562 * @retval None
563 */
SetSysClock(void)564 static void SetSysClock(void)
565 {
566 #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
567 /******************************************************************************/
568 /* PLL (clocked by HSE) used as System clock source */
569 /******************************************************************************/
570 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
571
572 /* Enable HSE */
573 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
574
575 /* Wait till HSE is ready and if Time out is reached exit */
576 do
577 {
578 HSEStatus = RCC->CR & RCC_CR_HSERDY;
579 StartUpCounter++;
580 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
581
582 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
583 {
584 HSEStatus = (uint32_t)0x01;
585 }
586 else
587 {
588 HSEStatus = (uint32_t)0x00;
589 }
590
591 if (HSEStatus == (uint32_t)0x01)
592 {
593 /* Select regulator voltage output Scale 1 mode */
594 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
595 PWR->CR |= PWR_CR_VOS;
596
597 /* HCLK = SYSCLK / 1*/
598 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
599
600 #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
601 /* PCLK2 = HCLK / 2*/
602 RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
603
604 /* PCLK1 = HCLK / 4*/
605 RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
606 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
607
608 #if defined (STM32F401xx)
609 /* PCLK2 = HCLK / 2*/
610 RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
611
612 /* PCLK1 = HCLK / 4*/
613 RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
614 #endif /* STM32F401xx */
615
616 /* Configure the main PLL */
617 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
618 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
619
620 /* Enable the main PLL */
621 RCC->CR |= RCC_CR_PLLON;
622
623 /* Wait till the main PLL is ready */
624 while((RCC->CR & RCC_CR_PLLRDY) == 0)
625 {
626 }
627
628 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
629 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
630 PWR->CR |= PWR_CR_ODEN;
631 while((PWR->CSR & PWR_CSR_ODRDY) == 0)
632 {
633 }
634 PWR->CR |= PWR_CR_ODSWEN;
635 while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
636 {
637 }
638 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
639 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
640 #endif /* STM32F427_437x || STM32F429_439xx */
641
642 #if defined (STM32F40_41xxx)
643 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
644 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
645 #endif /* STM32F40_41xxx */
646
647 #if defined (STM32F401xx)
648 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
649 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
650 #endif /* STM32F401xx */
651
652 /* Select the main PLL as system clock source */
653 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
654 RCC->CFGR |= RCC_CFGR_SW_PLL;
655
656 /* Wait till the main PLL is used as system clock source */
657 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
658 {
659 }
660 }
661 else
662 { /* If HSE fails to start-up, the application will have wrong clock
663 configuration. User can add here some code to deal with this error */
664 }
665 #elif defined (STM32F411xE)
666 #if defined (USE_HSE_BYPASS)
667 /******************************************************************************/
668 /* PLL (clocked by HSE) used as System clock source */
669 /******************************************************************************/
670 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
671
672 /* Enable HSE and HSE BYPASS */
673 RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
674
675 /* Wait till HSE is ready and if Time out is reached exit */
676 do
677 {
678 HSEStatus = RCC->CR & RCC_CR_HSERDY;
679 StartUpCounter++;
680 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
681
682 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
683 {
684 HSEStatus = (uint32_t)0x01;
685 }
686 else
687 {
688 HSEStatus = (uint32_t)0x00;
689 }
690
691 if (HSEStatus == (uint32_t)0x01)
692 {
693 /* Select regulator voltage output Scale 1 mode */
694 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
695 PWR->CR |= PWR_CR_VOS;
696
697 /* HCLK = SYSCLK / 1*/
698 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
699
700 /* PCLK2 = HCLK / 2*/
701 RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
702
703 /* PCLK1 = HCLK / 4*/
704 RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
705
706 /* Configure the main PLL */
707 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
708 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
709
710 /* Enable the main PLL */
711 RCC->CR |= RCC_CR_PLLON;
712
713 /* Wait till the main PLL is ready */
714 while((RCC->CR & RCC_CR_PLLRDY) == 0)
715 {
716 }
717
718 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
719 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
720
721 /* Select the main PLL as system clock source */
722 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
723 RCC->CFGR |= RCC_CFGR_SW_PLL;
724
725 /* Wait till the main PLL is used as system clock source */
726 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
727 {
728 }
729 }
730 else
731 { /* If HSE fails to start-up, the application will have wrong clock
732 configuration. User can add here some code to deal with this error */
733 }
734 #else /* HSI will be used as PLL clock source */
735 /* Select regulator voltage output Scale 1 mode */
736 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
737 PWR->CR |= PWR_CR_VOS;
738
739 /* HCLK = SYSCLK / 1*/
740 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
741
742 /* PCLK2 = HCLK / 2*/
743 RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
744
745 /* PCLK1 = HCLK / 4*/
746 RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
747
748 /* Configure the main PLL */
749 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
750
751 /* Enable the main PLL */
752 RCC->CR |= RCC_CR_PLLON;
753
754 /* Wait till the main PLL is ready */
755 while((RCC->CR & RCC_CR_PLLRDY) == 0)
756 {
757 }
758
759 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
760 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
761
762 /* Select the main PLL as system clock source */
763 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
764 RCC->CFGR |= RCC_CFGR_SW_PLL;
765
766 /* Wait till the main PLL is used as system clock source */
767 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
768 {
769 }
770 #endif /* USE_HSE_BYPASS */
771 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
772 }
773
774 /**
775 * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
776 * before jump to __main
777 * @param None
778 * @retval None
779 */
780 #ifdef DATA_IN_ExtSRAM
781 /**
782 * @brief Setup the external memory controller.
783 * Called in startup_stm32f4xx.s before jump to main.
784 * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
785 * This SRAM will be used as program data memory (including heap and stack).
786 * @param None
787 * @retval None
788 */
SystemInit_ExtMemCtl(void)789 void SystemInit_ExtMemCtl(void)
790 {
791 /*-- GPIOs Configuration -----------------------------------------------------*/
792 /*
793 +-------------------+--------------------+------------------+--------------+
794 + SRAM pins assignment +
795 +-------------------+--------------------+------------------+--------------+
796 | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
797 | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
798 | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
799 | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
800 | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
801 | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
802 | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
803 | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
804 | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
805 | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
806 | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
807 | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
808 | | PE15 <-> FMC_D12 |
809 +------------------+------------------+
810 */
811 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
812 RCC->AHB1ENR |= 0x00000078;
813
814 /* Connect PDx pins to FMC Alternate function */
815 GPIOD->AFR[0] = 0x00cc00cc;
816 GPIOD->AFR[1] = 0xcccccccc;
817 /* Configure PDx pins in Alternate function mode */
818 GPIOD->MODER = 0xaaaa0a0a;
819 /* Configure PDx pins speed to 100 MHz */
820 GPIOD->OSPEEDR = 0xffff0f0f;
821 /* Configure PDx pins Output type to push-pull */
822 GPIOD->OTYPER = 0x00000000;
823 /* No pull-up, pull-down for PDx pins */
824 GPIOD->PUPDR = 0x00000000;
825
826 /* Connect PEx pins to FMC Alternate function */
827 GPIOE->AFR[0] = 0xcccccccc;
828 GPIOE->AFR[1] = 0xcccccccc;
829 /* Configure PEx pins in Alternate function mode */
830 GPIOE->MODER = 0xaaaaaaaa;
831 /* Configure PEx pins speed to 100 MHz */
832 GPIOE->OSPEEDR = 0xffffffff;
833 /* Configure PEx pins Output type to push-pull */
834 GPIOE->OTYPER = 0x00000000;
835 /* No pull-up, pull-down for PEx pins */
836 GPIOE->PUPDR = 0x00000000;
837
838 /* Connect PFx pins to FMC Alternate function */
839 GPIOF->AFR[0] = 0x00cccccc;
840 GPIOF->AFR[1] = 0xcccc0000;
841 /* Configure PFx pins in Alternate function mode */
842 GPIOF->MODER = 0xaa000aaa;
843 /* Configure PFx pins speed to 100 MHz */
844 GPIOF->OSPEEDR = 0xff000fff;
845 /* Configure PFx pins Output type to push-pull */
846 GPIOF->OTYPER = 0x00000000;
847 /* No pull-up, pull-down for PFx pins */
848 GPIOF->PUPDR = 0x00000000;
849
850 /* Connect PGx pins to FMC Alternate function */
851 GPIOG->AFR[0] = 0x00cccccc;
852 GPIOG->AFR[1] = 0x000000c0;
853 /* Configure PGx pins in Alternate function mode */
854 GPIOG->MODER = 0x00080aaa;
855 /* Configure PGx pins speed to 100 MHz */
856 GPIOG->OSPEEDR = 0x000c0fff;
857 /* Configure PGx pins Output type to push-pull */
858 GPIOG->OTYPER = 0x00000000;
859 /* No pull-up, pull-down for PGx pins */
860 GPIOG->PUPDR = 0x00000000;
861
862 /*-- FMC Configuration ------------------------------------------------------*/
863 /* Enable the FMC/FSMC interface clock */
864 RCC->AHB3ENR |= 0x00000001;
865
866 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
867 /* Configure and enable Bank1_SRAM2 */
868 FMC_Bank1->BTCR[2] = 0x00001011;
869 FMC_Bank1->BTCR[3] = 0x00000201;
870 FMC_Bank1E->BWTR[2] = 0x0fffffff;
871 #endif /* STM32F427_437xx || STM32F429_439xx */
872
873 #if defined (STM32F40_41xxx)
874 /* Configure and enable Bank1_SRAM2 */
875 FSMC_Bank1->BTCR[2] = 0x00001011;
876 FSMC_Bank1->BTCR[3] = 0x00000201;
877 FSMC_Bank1E->BWTR[2] = 0x0fffffff;
878 #endif /* STM32F40_41xxx */
879
880 /*
881 Bank1_SRAM2 is configured as follow:
882 In case of FSMC configuration
883 NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
884 NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
885 NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
886 NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
887 NORSRAMTimingStructure.FSMC_CLKDivision = 0;
888 NORSRAMTimingStructure.FSMC_DataLatency = 0;
889 NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
890
891 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
892 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
893 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
894 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
895 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
896 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
897 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
898 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
899 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
900 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
901 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
902 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
903 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
904 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
905 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
906
907 In case of FMC configuration
908 NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
909 NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
910 NORSRAMTimingStructure.FMC_DataSetupTime = 2;
911 NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
912 NORSRAMTimingStructure.FMC_CLKDivision = 0;
913 NORSRAMTimingStructure.FMC_DataLatency = 0;
914 NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
915
916 FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
917 FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
918 FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
919 FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
920 FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
921 FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
922 FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
923 FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
924 FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
925 FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
926 FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
927 FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
928 FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
929 FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
930 FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
931 FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
932 */
933
934 }
935 #endif /* DATA_IN_ExtSRAM */
936
937 #ifdef DATA_IN_ExtSDRAM
938 /**
939 * @brief Setup the external memory controller.
940 * Called in startup_stm32f4xx.s before jump to main.
941 * This function configures the external SDRAM mounted on STM324x9I_EVAL board
942 * This SDRAM will be used as program data memory (including heap and stack).
943 * @param None
944 * @retval None
945 */
SystemInit_ExtMemCtl(void)946 void SystemInit_ExtMemCtl(void)
947 {
948 register uint32_t tmpreg = 0, timeout = 0xFFFF;
949 register uint32_t index;
950
951 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
952 clock */
953 RCC->AHB1ENR |= 0x000001FC;
954
955 /* Connect PCx pins to FMC Alternate function */
956 GPIOC->AFR[0] = 0x0000000c;
957 GPIOC->AFR[1] = 0x00007700;
958 /* Configure PCx pins in Alternate function mode */
959 GPIOC->MODER = 0x00a00002;
960 /* Configure PCx pins speed to 50 MHz */
961 GPIOC->OSPEEDR = 0x00a00002;
962 /* Configure PCx pins Output type to push-pull */
963 GPIOC->OTYPER = 0x00000000;
964 /* No pull-up, pull-down for PCx pins */
965 GPIOC->PUPDR = 0x00500000;
966
967 /* Connect PDx pins to FMC Alternate function */
968 GPIOD->AFR[0] = 0x000000CC;
969 GPIOD->AFR[1] = 0xCC000CCC;
970 /* Configure PDx pins in Alternate function mode */
971 GPIOD->MODER = 0xA02A000A;
972 /* Configure PDx pins speed to 50 MHz */
973 GPIOD->OSPEEDR = 0xA02A000A;
974 /* Configure PDx pins Output type to push-pull */
975 GPIOD->OTYPER = 0x00000000;
976 /* No pull-up, pull-down for PDx pins */
977 GPIOD->PUPDR = 0x00000000;
978
979 /* Connect PEx pins to FMC Alternate function */
980 GPIOE->AFR[0] = 0xC00000CC;
981 GPIOE->AFR[1] = 0xCCCCCCCC;
982 /* Configure PEx pins in Alternate function mode */
983 GPIOE->MODER = 0xAAAA800A;
984 /* Configure PEx pins speed to 50 MHz */
985 GPIOE->OSPEEDR = 0xAAAA800A;
986 /* Configure PEx pins Output type to push-pull */
987 GPIOE->OTYPER = 0x00000000;
988 /* No pull-up, pull-down for PEx pins */
989 GPIOE->PUPDR = 0x00000000;
990
991 /* Connect PFx pins to FMC Alternate function */
992 GPIOF->AFR[0] = 0xcccccccc;
993 GPIOF->AFR[1] = 0xcccccccc;
994 /* Configure PFx pins in Alternate function mode */
995 GPIOF->MODER = 0xAA800AAA;
996 /* Configure PFx pins speed to 50 MHz */
997 GPIOF->OSPEEDR = 0xAA800AAA;
998 /* Configure PFx pins Output type to push-pull */
999 GPIOF->OTYPER = 0x00000000;
1000 /* No pull-up, pull-down for PFx pins */
1001 GPIOF->PUPDR = 0x00000000;
1002
1003 /* Connect PGx pins to FMC Alternate function */
1004 GPIOG->AFR[0] = 0xcccccccc;
1005 GPIOG->AFR[1] = 0xcccccccc;
1006 /* Configure PGx pins in Alternate function mode */
1007 GPIOG->MODER = 0xaaaaaaaa;
1008 /* Configure PGx pins speed to 50 MHz */
1009 GPIOG->OSPEEDR = 0xaaaaaaaa;
1010 /* Configure PGx pins Output type to push-pull */
1011 GPIOG->OTYPER = 0x00000000;
1012 /* No pull-up, pull-down for PGx pins */
1013 GPIOG->PUPDR = 0x00000000;
1014
1015 /* Connect PHx pins to FMC Alternate function */
1016 GPIOH->AFR[0] = 0x00C0CC00;
1017 GPIOH->AFR[1] = 0xCCCCCCCC;
1018 /* Configure PHx pins in Alternate function mode */
1019 GPIOH->MODER = 0xAAAA08A0;
1020 /* Configure PHx pins speed to 50 MHz */
1021 GPIOH->OSPEEDR = 0xAAAA08A0;
1022 /* Configure PHx pins Output type to push-pull */
1023 GPIOH->OTYPER = 0x00000000;
1024 /* No pull-up, pull-down for PHx pins */
1025 GPIOH->PUPDR = 0x00000000;
1026
1027 /* Connect PIx pins to FMC Alternate function */
1028 GPIOI->AFR[0] = 0xCCCCCCCC;
1029 GPIOI->AFR[1] = 0x00000CC0;
1030 /* Configure PIx pins in Alternate function mode */
1031 GPIOI->MODER = 0x0028AAAA;
1032 /* Configure PIx pins speed to 50 MHz */
1033 GPIOI->OSPEEDR = 0x0028AAAA;
1034 /* Configure PIx pins Output type to push-pull */
1035 GPIOI->OTYPER = 0x00000000;
1036 /* No pull-up, pull-down for PIx pins */
1037 GPIOI->PUPDR = 0x00000000;
1038
1039 /*-- FMC Configuration ------------------------------------------------------*/
1040 /* Enable the FMC interface clock */
1041 RCC->AHB3ENR |= 0x00000001;
1042
1043 /* Configure and enable SDRAM bank1 */
1044 FMC_Bank5_6->SDCR[0] = 0x000039D0;
1045 FMC_Bank5_6->SDTR[0] = 0x01115351;
1046
1047 /* SDRAM initialization sequence */
1048 /* Clock enable command */
1049 FMC_Bank5_6->SDCMR = 0x00000011;
1050 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1051 while((tmpreg != 0) & (timeout-- > 0))
1052 {
1053 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1054 }
1055
1056 /* Delay */
1057 for (index = 0; index<1000; index++);
1058
1059 /* PALL command */
1060 FMC_Bank5_6->SDCMR = 0x00000012;
1061 timeout = 0xFFFF;
1062 while((tmpreg != 0) & (timeout-- > 0))
1063 {
1064 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1065 }
1066
1067 /* Auto refresh command */
1068 FMC_Bank5_6->SDCMR = 0x00000073;
1069 timeout = 0xFFFF;
1070 while((tmpreg != 0) & (timeout-- > 0))
1071 {
1072 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1073 }
1074
1075 /* MRD register program */
1076 FMC_Bank5_6->SDCMR = 0x00046014;
1077 timeout = 0xFFFF;
1078 while((tmpreg != 0) & (timeout-- > 0))
1079 {
1080 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1081 }
1082
1083 /* Set refresh count */
1084 tmpreg = FMC_Bank5_6->SDRTR;
1085 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
1086
1087 /* Disable write protection */
1088 tmpreg = FMC_Bank5_6->SDCR[0];
1089 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
1090
1091 /*
1092 Bank1_SDRAM is configured as follow:
1093
1094 FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
1095 FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
1096 FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
1097 FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
1098 FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
1099 FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
1100 FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
1101
1102 FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
1103 FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
1104 FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
1105 FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
1106 FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
1107 FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
1108 FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
1109 FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
1110 FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
1111 FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
1112 FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
1113 */
1114
1115 }
1116 #endif /* DATA_IN_ExtSDRAM */
1117
1118
1119 /**
1120 * @}
1121 */
1122
1123 /**
1124 * @}
1125 */
1126
1127 /**
1128 * @}
1129 */
1130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1131