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1/******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 *     http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18#if 0	/*default is close*/
19    .section .vectors, "ax"
20
21    //.org  and linker's relaxation (-flto) cannot be used at the same time
22    //Pop corresponds to push. Before using .option norelax, use push to save the current .option configuration
23    //and then modify .option. After using norelax, use pop to restore
24	.option push
25	.option norelax
26    .org 0x0
27
28
29    .global _RESET_ENTRY
30 	.type _RESET_ENTRY,@function
31
32    .align 2
33_RESET_ENTRY:
34	j 		 _START
35	//free the 6th ~ 7th byte to store the crc type of the bin file
36    .org 0x18
37    .word (BIN_SIZE)
38
39    .org 0x20
40    .word ('T'<<24 | 'L'<<16 | 'N'<<8 | 'K')
41
42    .org 0x26
43    //.short (0x0003)           //READ:    cmd:1x, addr:1x, data:1x, dummy:0
44    //.short (0x070B)           //FREAD:   cmd:1x, addr:1x, data:1x, dummy:8
45    .short (0x173B)           //DREAD:   cmd:1x, addr:1x, data:2x, dummy:8
46    //.short (0x53BB)           //X2READ:  cmd:1x, addr:2x, data:2x, dummy:4
47    //.short (0x276B)           //QREAD:   cmd:1x, addr:1x, data:4x, dummy:8
48    //.short (0x65EB)             //X4READ:  cmd:1x, addr:4x, data:4x, dummy:6
49    .option pop
50    .align 2
51
52_START:
53
54#if 0
55	// add debug, PB4 output 1
56	lui		t0,0x80140 			//0x8014030a
57	li		t1, 0xef
58	li		t2, 0x10
59	sb		t1 , 0x30a(t0)		 //0x8014030a  PB oen     =  0xef
60	sb		t2 , 0x30b(t0)		 //0x8014030b  PB output  =  0x10
61#endif
62	/* Initialize global pointer */
63    .option push
64    .option norelax
65    la     gp, __global_pointer$
66    .option pop
67
68	/* Initialize stack pointer */
69    la     t0, _STACK_TOP
70    mv     sp, t0
71
72#ifdef __nds_execit
73	/* Initialize EXEC.IT table */
74	la t0, _ITB_BASE_
75	csrw uitb, t0
76#endif
77
78#ifdef __riscv_flen
79	/* Enable FPU */
80	li t0, 0x00006000
81	csrrs t0, mstatus, t0
82	/* Initialize FCSR */
83	fscsr zero
84#endif
85
86    /* Initial machine trap-vector Base */
87    la     t0, __vectors
88    csrw   mtvec, t0
89
90    /* Enable vectored external plic interrupt */
91    csrsi  mmisc_ctl, 2
92/*
93*#if (SUPPORT_PFT_ARCH)
94*	plic_set_feature(FLD_FEATURE_PREEMPT_PRIORITY_INT_EN | FLD_FEATURE_VECTOR_MODE_EN);//enable vectored in PLIC
95*   =(0xe4000000))= 0x03
96*#else
97*	plic_set_feature(FLD_FEATURE_VECTOR_MODE_EN);//enable vectored in PLIC
98*	=(0xe4000000))= 0x02
99*#endif
100*/
101	/*vector mode enable bit (VECTORED) of the Feature Enable Register */
102    lui		t0, 0xe4000
103	li		t1, 0x03
104	sw		t1, 0x0(t0)		 //(*(volatile unsigned long*)(0xe4000000))= 0x02
105
106    /* Enable I/D-Cache */
107    csrr   t0,  mcache_ctl
108    ori    t0,  t0,  1  #/I-Cache
109    ori    t0,  t0,  2  #/D-Cache
110    csrw   mcache_ctl,  t0
111    fence.i
112	/* Move retention reset from flash to sram */
113_RETENTION_RESET_INIT:
114
115    la     t1, _RETENTION_RESET_LMA_START
116    la     t2, _RETENTION_RESET_VMA_START
117    la     t3, _RETENTION_RESET_VMA_END
118_RETENTION_RESET_BEGIN:
119    bleu    t3, t2, _RETENTION_DATA_INIT
120    lw     t0, 0(t1)
121    sw     t0, 0(t2)
122    addi   t1, t1, 4
123    addi   t2, t2, 4
124    j      _RETENTION_RESET_BEGIN
125
126	/* Move retention from flash to sram */
127_RETENTION_DATA_INIT:
128
129    la     t1, _RETENTION_DATA_LMA_START
130    la     t2, _RETENTION_DATA_VMA_START
131    la     t3, _RETENTION_DATA_VMA_END
132_RETENTION_DATA_INIT_BEGIN:
133    bleu   t3, t2, _RAMCODE_INIT
134    lw     t0, 0(t1)
135    sw     t0, 0(t2)
136    addi   t1, t1, 4
137    addi   t2, t2, 4
138    j      _RETENTION_DATA_INIT_BEGIN
139
140	/* Move ramcode from flash to sram */
141_RAMCODE_INIT:
142
143    la     t1, _RAMCODE_LMA_START
144    la     t2, _RAMCODE_VMA_START
145    la     t3, _RAMCODE_VMA_END
146_RAMCODE_INIT_BEGIN:
147    bleu    t3, t2, _DATA_INIT
148    lw     t0, 0(t1)
149    sw     t0, 0(t2)
150    addi   t1, t1, 4
151    addi   t2, t2, 4
152    j      _RAMCODE_INIT_BEGIN
153
154	/* Move DLM_Data from flash to sram */
155_DLM_DATA_INIT:
156    la     t1, _DLM_DATA_LMA_START
157    la     t2, _DLM_DATA_VMA_START
158    la     t3, _DLM_DATA_VMA_END
159_DLM_DATA_INIT_BEGIN:
160    bleu   t3, t2, _DATA_INIT
161    lw     t0, 0(t1)
162    sw     t0, 0(t2)
163    addi   t1, t1, 4
164    addi   t2, t2, 4
165    j      _DLM_DATA_INIT_BEGIN
166
167	/* Move Data from flash to sram */
168_DATA_INIT:
169    la     t1, _DATA_LMA_START
170    la     t2, _DATA_VMA_START
171    la     t3, _DATA_VMA_END
172_DATA_INIT_BEGIN:
173    bleu   t3, t2, _ZERO_BSS
174    lw     t0, 0(t1)
175    sw     t0, 0(t2)
176    addi   t1, t1, 4
177    addi   t2, t2, 4
178    j      _DATA_INIT_BEGIN
179
180
181
182	/* Zero .bss section in sram */
183_ZERO_BSS:
184    lui    t0, 0
185    la     t2, _BSS_VMA_START
186    la     t3, _BSS_VMA_END
187_ZERO_BSS_BEGIN:
188    bleu   t3, t2, _ZERO_AES
189    sw     t0, 0(t2)
190    addi   t2, t2, 4
191    j      _ZERO_BSS_BEGIN
192
193	/* Zero .aes section in sram */
194_ZERO_AES:
195    lui    t0, 0
196    la     t2, _AES_VMA_START
197    la     t3, _AES_VMA_END
198_ZERO_AES_BEGIN:
199    bleu   t3, t2, _FILL_STK
200    sw     t0, 0(t2)
201    addi   t2, t2, 4
202    j      _ZERO_AES_BEGIN
203
204	/* Fill the remaining section in sram */
205_FILL_STK:
206#if 0
207    lui    t0, 0x55555
208    addi   t0, t0, 0x555
209    la     t2, _BSS_VMA_END
210    la     t3, _STACK_TOP
211_FILL_STK_BEGIN:
212    bleu   t3, t2, _MAIN_FUNC
213    sw     t0, 0(t2)
214    addi   t2, t2, 4
215    j      _FILL_STK_BEGIN
216#endif
217	/* Jump to the main function */
218_MAIN_FUNC:
219    nop
220
221    la     t0, main
222    jalr   t0
223
224    nop
225    nop
226    nop
227    nop
228    nop
229_END:
230    j    _END
231
232
233 .section .retention_reset, "ax"
234    .option push
235    .option norelax
236    .global _IRESET_ENTRY
237 	.type _IRESET_ENTRY,@function
238
239    .align 2
240_IRESET_ENTRY:
241	/* Decide whether this is an NMI or cold reset */
242	j 		_ISTART
243
244	.org 0x22
245_ISTART:
246#if 0
247	// add debug, PB4 output 1
248	lui		t0,0x80140 			//0x8014030a
249	li		t1, 0xef
250	li		t2, 0x10
251	sb		t1 , 0x30a(t0)		 //0x8014030a  PB oen     =  0xef
252	sb		t2 , 0x30b(t0)		 //0x8014030b  PB output  =  0x10
253#endif
254	/* Initialize global pointer */
255
256    la     gp, __global_pointer$
257    .option pop
258
259	/* Initialize stack pointer */
260    la     t0, _STACK_TOP
261    mv     sp, t0
262
263#ifdef __nds_execit
264	/* Initialize EXEC.IT table */
265	la t0, _ITB_BASE_
266	csrw uitb, t0
267#endif
268
269#ifdef __riscv_flen
270	/* Enable FPU */
271	li t0, 0x00006000
272	csrrs t0, mstatus, t0
273	/* Initialize FCSR */
274	fscsr zero
275#endif
276
277    /* Initial machine trap-vector Base */
278    la     t0, __vectors
279    csrw   mtvec, t0
280
281    /* Enable vectored external plic interrupt */
282    csrsi  mmisc_ctl, 2
283
284/*
285*#if (SUPPORT_PFT_ARCH)
286*	plic_set_feature(FLD_FEATURE_PREEMPT_PRIORITY_INT_EN | FLD_FEATURE_VECTOR_MODE_EN);//enable vectored in PLIC
287*   =(0xe4000000))= 0x03
288*#else
289*	plic_set_feature(FLD_FEATURE_VECTOR_MODE_EN);//enable vectored in PLIC
290*	=(0xe4000000))= 0x02
291*#endif
292*/
293	/*vector mode enable bit (VECTORED) of the Feature Enable Register */
294    lui		t0, 0xe4000
295	li		t1, 0x03
296	sw		t1, 0x0(t0)		 //(*(volatile unsigned long*)(0xe4000000))= 0x03
297
298    /* Enable I/D-Cache */
299    csrr   t0,  mcache_ctl
300    ori    t0,  t0,  1  #/I-Cache
301    ori    t0,  t0,  2  #/D-Cache
302    csrw   mcache_ctl,  t0
303    fence.i
304
305
306/* flash wakeup */
307_WAKEUP_FLASH:
308	lui		t0 , 0x80140
309	li		t1 , 0xff
310	li		t2 , 0x0
311	li		t3 , 0xab
312	sb		t1 , 0x329(t0)			 //mspi ie enable	:0x140329:0x1f
313	sb		t2 , 0x101(t0)			 //cs_low			:0x140101:0x00
314	sb		t3 , 0x100(t0)			 //wakeup_cmd		:0x140100:0xab
315_MSPI_WAIT:
316	lui		t0 , 0x80140
317	lb		t2 , 0x102(t0)			//read reg_mspi_status FLD_MSPI_BUSY(bit0)
318	li		t3 , 0x1
319	li		t4 , 0x10
320	beq 	t3 , t2 ,_MSPI_WAIT
321	sb		t4 , 0x101(t0)			//cs_high			:0x140101:0x10
322#if 0
323	// add debug, PB4 output 1
324	lui		t0,0x80140 			//0x8014030a
325	li		t1, 0x00
326	sb		t1 , 0x30b(t0)		 //0x8014030b  PB output  =  0x00
327#endif
328/*efuse load need delay about 18us */
329	li		t0 , 0
330	li		t1 , 226
331_WAIT_EFUSE_LOAD_FINISH:
332	addi 	t0 , t0 , 1
333	bgeu 	t1 , t0 , _WAIT_EFUSE_LOAD_FINISH
334
335#if 0
336	// add debug, PB4 output 1
337	lui		t0,0x80140 			//0x8014030a
338	li		t1, 0x10
339	sb		t1 , 0x30b(t0)		 //0x8014030b  PB output  =  0x00
340#endif
341_MULTI_ADDRESS_BEGIN:
342	lui		t0 , 0x80140
343	la		t1 , tl_multi_addr
344	lw		t2 , 0(t1)
345	sw		t2 , 0x104(t0)			 //g_pm_multi_addr->0x80140104
346
347#if 0
348	/* Move ramcode from flash to sram */
349_IRAMCODE_INIT:
350
351    la     t1, _RAMCODE_LMA_START
352    la     t2, _RAMCODE_VMA_START
353    la     t3, _RAMCODE_VMA_END
354_IRAMCODE_INIT_BEGIN:
355    bleu   t3, t2, _IDATA_INIT
356    lw     t0, 0(t1)
357    sw     t0, 0(t2)
358    addi   t1, t1, 4
359    addi   t2, t2, 4
360    j      _IRAMCODE_INIT_BEGIN
361#endif
362
363	/* Move DLM_Data from flash to sram */
364_IDLM_DATA_INIT:
365    la     t1, _DLM_DATA_LMA_START
366    la     t2, _DLM_DATA_VMA_START
367    la     t3, _DLM_DATA_VMA_END
368_IDLM_DATA_INIT_BEGIN:
369    bleu   t3, t2, _IDATA_INIT
370    lw     t0, 0(t1)
371    sw     t0, 0(t2)
372    addi   t1, t1, 4
373    addi   t2, t2, 4
374    j      _IDLM_DATA_INIT_BEGIN
375
376	/* Move Data from flash to sram */
377_IDATA_INIT:
378    la     t1, _DATA_LMA_START
379    la     t2, _DATA_VMA_START
380    la     t3, _DATA_VMA_END
381_IDATA_INIT_BEGIN:
382    bleu   t3, t2, _IZERO_BSS
383    lw     t0, 0(t1)
384    sw     t0, 0(t2)
385    addi   t1, t1, 4
386    addi   t2, t2, 4
387    j      _IDATA_INIT_BEGIN
388
389
390
391	/* Zero .bss section in sram */
392_IZERO_BSS:
393    lui    t0, 0
394    la     t2, _BSS_VMA_START
395    la     t3, _BSS_VMA_END
396_IZERO_BSS_BEGIN:
397    bleu   t3, t2, _IZERO_AES
398    sw     t0, 0(t2)
399    addi   t2, t2, 4
400    j      _IZERO_BSS_BEGIN
401
402	/* Zero .aes section in sram */
403_IZERO_AES:
404    lui    t0, 0
405    la     t2, _AES_VMA_START
406    la     t3, _AES_VMA_END
407_IZERO_AES_BEGIN:
408    bleu   t3, t2, _IFILL_STK
409    sw     t0, 0(t2)
410    addi   t2, t2, 4
411    j      _IZERO_AES_BEGIN
412
413
414	/* Fill the remaining section in sram */
415_IFILL_STK:
416#if 0
417    lui    t0, 0x55555
418    addi   t0, t0, 0x555
419    la     t2, _BSS_VMA_END
420    la     t3, _STACK_TOP
421_IFILL_STK_BEGIN:
422    bleu   t3, t2, _IMAIN_FUNC
423    sw     t0, 0(t2)
424    addi   t2, t2, 4
425    j      _IFILL_STK_BEGIN
426#endif
427	/* Jump to the main function */
428_IMAIN_FUNC:
429    nop
430
431    la     t0, main
432    jalr   t0
433
434    nop
435    nop
436    nop
437    nop
438    nop
439_IEND:
440    j    _IEND
441
442
443.text
444	.global default_irq_entry
445	.align 2
446
447default_irq_entry:
4481:	j 1b
449
450       .weak trap_handler
451
452 trap_handler:
4531:	j 1b
454
455	.macro INTERRUPT num
456	.weak entry_irq\num
457	.set entry_irq\num, default_irq_entry
458	.long entry_irq\num
459	.endm
460
461#define VECTOR_NUMINTRS         63
462
463   	.section .ram_code, "ax"
464
465	.global __vectors
466	.balign 256
467
468
469__vectors:
470	/* Trap vector */
471	.long trap_entry
472
473	/* PLIC interrupt vector */
474	.altmacro
475	.set irqno, 1
476	.rept VECTOR_NUMINTRS/*  .rept  .endr  */
477	INTERRUPT %irqno
478	.set irqno, irqno+1
479	.endr
480#endif
481