1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 /** @page CLOCK 19 * 20 * Introduction 21 * =============== 22 * TLSRB91 clock setting. 23 * 24 * API Reference 25 * =============== 26 * Header File: clock.h 27 */ 28 29 #ifndef CLOCK_H_ 30 #define CLOCK_H_ 31 32 #include "compiler.h" 33 #include "reg_include/register_b91.h" 34 35 /********************************************************************************************************************** 36 * global constants * 37 *********************************************************************************************************************/ 38 39 /********************************************************************************************************************** 40 * global macro * 41 *********************************************************************************************************************/ 42 #define CCLK_16M_HCLK_16M_PCLK_16M \ 43 clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV12_TO_CCLK, CCLK_DIV1_TO_HCLK, HCLK_DIV1_TO_PCLK, \ 44 PLL_DIV4_TO_MSPI_CLK) 45 #define CCLK_24M_HCLK_24M_PCLK_24M \ 46 clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV8_TO_CCLK, CCLK_DIV1_TO_HCLK, HCLK_DIV1_TO_PCLK, PLL_DIV4_TO_MSPI_CLK) 47 #define CCLK_32M_HCLK_32M_PCLK_16M \ 48 clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV6_TO_CCLK, CCLK_DIV1_TO_HCLK, HCLK_DIV2_TO_PCLK, PLL_DIV4_TO_MSPI_CLK) 49 #define CCLK_48M_HCLK_48M_PCLK_24M \ 50 clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV4_TO_CCLK, CCLK_DIV1_TO_HCLK, HCLK_DIV2_TO_PCLK, PLL_DIV4_TO_MSPI_CLK) 51 52 /********************************************************************************************************************** 53 * global data type * 54 *********************************************************************************************************************/ 55 56 /** 57 * @brief Define sys_clk struct. 58 */ 59 typedef struct { 60 unsigned short pll_clk; /**< pll clk */ 61 unsigned char cclk; /**< cpu clk */ 62 unsigned char hclk; /**< hclk */ 63 unsigned char pclk; /**< pclk */ 64 unsigned char mspi_clk; /**< mspi_clk */ 65 } sys_clk_t; 66 67 /** 68 * @brief system clock type 69 * | | | | 70 * | :-------- | :----------- | :------------ | 71 * | <1:0> | <6:2> | <15:8> | 72 * |ana_09<3:2>|analog_80<4:0>| clk | 73 */ 74 typedef enum { 75 PLL_CLK_48M = (0 | (16 << 2) | (48 << 8)), 76 PLL_CLK_54M = (0 | (17 << 2) | (54 << 8)), 77 PLL_CLK_60M = (0 | (18 << 2) | (60 << 8)), 78 PLL_CLK_66M = (0 | (19 << 2) | (66 << 8)), 79 PLL_CLK_96M = (1 | (16 << 2) | (96 << 8)), 80 PLL_CLK_108M = (1 | (17 << 2) | (108 << 8)), 81 PLL_CLK_120M = (1 | (18 << 2) | (120 << 8)), 82 PLL_CLK_132M = (1 | (19 << 2) | (132 << 8)), 83 PLL_CLK_192M = (2 | (16 << 2) | (192 << 8)), 84 PLL_CLK_216M = (2 | (17 << 2) | (216 << 8)), 85 PLL_CLK_240M = (2 | (18 << 2) | (240 << 8)), 86 PLL_CLK_264M = (2 | (19 << 2) | (264 << 8)), 87 } sys_pll_clk_e; 88 89 /** 90 * @brief system clock type. 91 */ 92 typedef enum { 93 RC24M, 94 PAD24M, 95 PAD_PLL_DIV, 96 PAD_PLL, 97 } sys_clock_src_e; 98 99 /** 100 * @brief 32K clock type. 101 */ 102 typedef enum { 103 CLK_32K_RC = 0, 104 CLK_32K_XTAL = 1, 105 } clk_32k_type_e; 106 107 /** 108 * @brief pll div to cclk. 109 */ 110 typedef enum { 111 PLL_DIV2_TO_CCLK = 2, 112 PLL_DIV3_TO_CCLK = 3, 113 PLL_DIV4_TO_CCLK = 4, 114 PLL_DIV5_TO_CCLK = 5, 115 PLL_DIV6_TO_CCLK = 6, 116 PLL_DIV7_TO_CCLK = 7, 117 PLL_DIV8_TO_CCLK = 8, 118 PLL_DIV9_TO_CCLK = 9, 119 PLL_DIV10_TO_CCLK = 10, 120 PLL_DIV11_TO_CCLK = 11, 121 PLL_DIV12_TO_CCLK = 12, 122 PLL_DIV13_TO_CCLK = 13, 123 PLL_DIV14_TO_CCLK = 14, 124 PLL_DIV15_TO_CCLK = 15, 125 } sys_pll_div_to_cclk_e; 126 127 /** 128 * @brief cclk/pll_div to mspi clk. 129 */ 130 typedef enum { 131 CCLK_TO_MSPI_CLK = 1, 132 PLL_DIV2_TO_MSPI_CLK = 2, 133 PLL_DIV3_TO_MSPI_CLK = 3, 134 PLL_DIV4_TO_MSPI_CLK = 4, 135 PLL_DIV5_TO_MSPI_CLK = 5, 136 PLL_DIV6_TO_MSPI_CLK = 6, 137 PLL_DIV7_TO_MSPI_CLK = 7, 138 PLL_DIV8_TO_MSPI_CLK = 8, 139 PLL_DIV9_TO_MSPI_CLK = 9, 140 PLL_DIV10_TO_MSPI_CLK = 10, 141 PLL_DIV11_TO_MSPI_CLK = 11, 142 PLL_DIV12_TO_MSPI_CLK = 12, 143 PLL_DIV13_TO_MSPI_CLK = 13, 144 PLL_DIV14_TO_MSPI_CLK = 14, 145 PLL_DIV15_TO_MSPI_CLK = 15, 146 } sys_pll_div_to_mspi_clk_e; 147 148 /** 149 * @brief hclk div to pclk. 150 */ 151 typedef enum { 152 HCLK_DIV1_TO_PCLK = 1, 153 HCLK_DIV2_TO_PCLK = 2, 154 HCLK_DIV4_TO_PCLK = 4, 155 } sys_hclk_div_to_pclk_e; 156 157 /** 158 * @brief cclk div to hclk. 159 */ 160 typedef enum { 161 CCLK_DIV1_TO_HCLK = 1, 162 CCLK_DIV2_TO_HCLK = 2, /* < can not use in A0. if use reboot when hclk = 1/2cclk will cause problem */ 163 } sys_cclk_div_to_hclk_e; 164 165 /** 166 * @brief Define rc_24M_cal enable/disable. 167 */ 168 typedef enum { 169 RC_24M_CAL_DISABLE = 0, 170 RC_24M_CAL_ENABLE, 171 } rc_24M_cal_e; 172 173 /********************************************************************************************************************** 174 * global variable declaration * 175 *********************************************************************************************************************/ 176 extern sys_clk_t sys_clk; 177 extern clk_32k_type_e g_clk_32k_src; 178 179 /********************************************************************************************************************** 180 * global function prototype * 181 *********************************************************************************************************************/ 182 183 /** 184 * @brief This function use to select the system clock source. 185 * @param[in] pll - pll clock. 186 * @param[in] src - cclk source. 187 * @param[in] cclk_div - the cclk divide from pll.it is useless if src is not PAD_PLL_DIV. cclk max is 96M 188 * @param[in] hclk_div - the hclk divide from cclk.hclk max is 48M. 189 * @param[in] pclk_div - the pclk divide from hclk.pclk max is 24M. 190 * @param[in] mspi_clk_div - mspi_clk has two source. pll div and hclk.mspi max is 64M. 191 * @return none 192 */ 193 _attribute_ram_code_sec_noinline_ void clock_init(sys_pll_clk_e pll, sys_clock_src_e src, 194 sys_pll_div_to_cclk_e cclk_div, sys_cclk_div_to_hclk_e hclk_div, 195 sys_hclk_div_to_pclk_e pclk_div, 196 sys_pll_div_to_mspi_clk_e mspi_clk_div); 197 198 /** 199 * @brief This function serves to set 32k clock source. 200 * @param[in] src - variable of 32k type. 201 * @return none. 202 */ 203 void clock_32k_init(clk_32k_type_e src); 204 205 /** 206 * @brief This function serves to kick 32k xtal. 207 * @param[in] xtal_times - kick times. 208 * @return 1 success, 0 error. 209 */ 210 unsigned char clock_kick_32k_xtal(unsigned char xtal_times); 211 212 /** 213 * @brief This function performs to select 24M as the system clock source. 214 * @return none. 215 */ 216 _attribute_ram_code_sec_noinline_ void clock_cal_24m_rc(void); 217 218 /** 219 * @brief This function performs to select 32K as the system clock source. 220 * @return none. 221 */ 222 void clock_cal_32k_rc(void); 223 224 /** 225 * @brief This function serves to get the 32k tick. 226 * @return none. 227 */ 228 _attribute_ram_code_sec_noinline_ unsigned int clock_get_32k_tick(void); 229 230 /** 231 * @brief This function serves to set the 32k tick. 232 * @param tick - the value of to be set to 32k. 233 * @return none. 234 */ 235 _attribute_ram_code_sec_noinline_ void clock_set_32k_tick(unsigned int tick); 236 #endif 237